CS3308

CS3308 CIRRUS | Alldatasheet

Document overview

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Technical content

Features

 Complete Analog Volume Control

8 Independently Controllable Channels

3 Configurable Master Volume and Muting

 Wide Adjustable Volume Range -96 dB to +22 dB in ¼ dB Steps  Low Distortion & Noise -112 dB THD+N 123 dB Dynamic Range  Noise-Free Level Transitions Zero-Crossing Detection with Programmable Time-Out  Low Channel-to-Channel Crosstalk 120 dB Inter-Channel Isolation  Comprehensive Serial Control Port Supports I²C® and SPITM Communication Independent Control of up to 128 Devices on a Shared 2-Wire I²C or 3-Wire SPI Control Bus Supports Individual and Grouped Control of all CS3308 Devices on the I²C or SPI Control Bus  Standard Power Supply Voltages ±5 V Analog Supply +3.3 V Digital Supply

Description

The CS3308 is an 8-channel digitally controlled analog volume control designed specifically for high-end audio systems. It features a comprehensive I²C/SPI serial control port for easy device and volume configuration. The CS3308 includes arrays of well-matched resistors and complementary low-noise active output stages. A total adjustable range of 118 dB, in ¼ dB steps, is spread evenly over 96 dB of attenuation and 22 dB of gain. The CS3308 implements configurable zero-crossing detection to provide glitch-free volume-level changes. The I²C/SPI control interface provides for easy system integration of up to 128 CS3308 devices over a single 2- wire I²C or 3-wire SPI bus, allowing many channels of volume control with minimal system controller I/O re- quirements. Devices may be controlled on an individual and grouped basis, simplifying simultaneous configura- tion of a group of channels across multiple devices, while allowing discrete control over all channels on an individual basis. The device operates from ±5 V analog supplies and has an input/output voltage range of ±3.65 V. The digital control interface operates at +3.3 V. The CS3308 is available in a 48-pin LQFP package in Commercial grade (-10° to 70° C). The CS3308 Cus- tomer Demonstration board is also available for device evaluation. Refer to “Ordering Information” on page 44 for complete details. ±5 V +3.3 V 8-Channel Analog Outputs I²C/SPI Serial Control Zero Crossing Detector I²C / SPI Control Port 8-Channel Analog Inputs DECEMBER '06 DS702F1 CS3308

1. PIN DESCRIPTIONS Pin Name Pin Description IN1 IN2 IN3 IN4 IN5 IN6 IN7 IN8 Analog Inputs (Input) - The full-scale level is specified in the Analog Characteristics specification table. 13 14 15 16 17 18 19 20 21 22 23 24 47 46 45 44 43 42 41 40 39 38 37 VA- IN1 REFO8 REFO1 REFI1 RESET MUTE SCL/CCLK SDA/MOSI AD0/CS ENOut DGND VD REFI8 IN8 OUT8 VA- OUT7 REF07 IN7 REFI7 REFI6 IN6 REFO6 OUT6 VA+ VA+ OUT4 REFO4 IN4 REFI4 REFI5 IN5 REFO5 OUT5 VA- VA+ OUT1 VA- VA+ OUT2 REFO2 IN2 REFI2 REFI3 IN3 REFO3 OUT3 CS3308

Analog Outputs (Output) - The full-scale output level is specified in the Analog Characteristics specifi- cation table. REFI1 REFI2 REFI3 REFI4 REFI5 REFI6 REFI7 REFI8 Reference In (Input) - Analog reference pin. REFO1 REFO2 REFO3 REFO4 REFO5 REFO6 REFO7 REFO8 Reference Out (Output) - Analog reference pin. VA+ 15, 25, 35, Positive Analog Power (Input) - Positive power for the internal analog section. VA- 16, 26, 36, Negative Analog Power (Input) - Negative power for the internal analog section. RESET Reset (Input) - The device enters a low-power mode when this pin is driven low. MUTE Mute (Input) - This pin defaults to an active low mute input, and may be configured as an active high mute input. SCL/CCLK Serial Control Port Clock (Input) - Serial clock for the serial control port. SDA/MOSI Serial Control Data (Input/Output) - SDA is a data I/O line for the control port interface in I²C Mode. MOSI is the input data line for the control port interface in SPI Mode. AD0/CS Default Address Bit 0 (I²C) / Control Port Chip Select (SPI) (Input) - AD0 sets the LSB of the default chip address in I²C Mode. CS is the chip-select signal for SPI format. ENOut Enable Output (Output) - Enable output signal for multi-device serial control chain configuration. DGND Digital Ground (Input) - Ground reference for the internal digital section. VD Digital Power (Input) - Positive power for the internal digital section. Pin Name Pin Description

1. CHARACTERISTICS AND SPECIFICATIONS All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical performance characteristics and specifications are derived from measurements taken at nominal supply voltages and TA = 25°C. SPECIFIED OPERATING CONDITIONS (DGND = 0 V; All voltages with respect to ground.) ABSOLUTE MAXIMUM RATINGS (DGND = 0 V; All voltages with respect to ground. (Note 1) Notes: Operation beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. Any pin except supplies. Transient currents of up to ±100 mA on the analog input pins will not cause SCR latch-up. Parameters Symbol Min Nom Max Units DC Power Supplies: Positive Analog Negative Analog Digital VA+ VA- VD 4.75 -5.25 3.1 3.3 5.25 -4.75 3.5 V V V Ambient Operating Temperature (Power Applied) TA -10 +70 Parameter Symbol Min Max Units DC Power Supplies: Positive Analog Negative Analog Digital VA+ VA- VD -0.3 -7.0 -0.3 7.0 0.3 3.63 V V V Input Current (Note 2) Iin ±10 mA Analog Input Voltage VINA (VA-) - 0.3 (VA+) + 0.3 V Digital Input Voltage VIND VD - 0.3 VD + 0.3 V Ambient Operating Temperature (Power Applied) TA -55 +125 Storage Temperature Tstg -65 +150

(Test conditions (unless otherwise specified): RS = 0; RL = 2 kΩ; CL = 20 pF; 10 Hz to 20 kHz Measurement Band- width) Vin = [(VFS Max - VFS Min) - 1.6 V] Vp-p, 1 kHz, Volume = 0 dB. Note that for (VA+) = -(VA-) = 5 V, Vin = 5.7 Vp-p = 2 VRMS. Measured with input grounded and volume = 0 dB. Will increase as a function of volume settings >0 dB. Power-down is defined as RESET = low, all clock and data lines held static, and no analog input signals applied. Parameter Symbol Min Typ Max Unit DC Characteristics Step Size 0.25 dB Gain Error (Vol = +22 dB) ±0.5 dB Gain Matching Between Channels (Vol = +22 dB) ±0.1 dB Input Resistance RIN kΩ Input Capacitance CIN pF AC Characteristics Total Harmonic Distortion + Noise (Note 3) THD+N 0.00025 0.00063 Dynamic Range 117 123 dB Input/Output Voltage Range (THD+N < 1 %) VFS (VA-) + 1.35 (VA+) - 1.35 V Output Noise (Note 4) 1.8 3.6 μVrms Interchannel Isolation (1 kHz) -120 dB Output Buffer Offset Voltage (Note 4) VOS 0.75 mV Output Resistance ROUT 100 Ω AC Load Resistance RLOAD kΩ Load Capacitance 100 pF Short Circuit Current mA Unity Gain Bandwidth, Small Signal MHz Power Supplies Supply Current (No Load, Vin = 0 V) Normal Operation Power-Down, All Supplies (Note 5) IVA+ IVA- IVD IPD 0.6 1.07 mA mA mA μA Power Consumption Normal Operation Power Down (Note 5) 362 300 500 mW μW Power Supply Rejection Ratio (250 Hz) PSRR dB

DIGITAL INTERFACE CHARACTERISTICS MUTE SWITCHING CHARACTERISTICS (Inputs: Logic 0 = DGND, Logic 1 = VD) The MUTE active state (low/high) is set by the MutePolarity bit in the Device Configuration 1 register (see page 33). Parameters Symbol Min Typ Max Units High-Level Input Voltage VIH 0.7 x VD V Low-Level Input Voltage VIL 0.2 x VD V High-Level Output Voltage at Io=2 mA VOH VD - 1.0 V Low-Level Output Voltage at Io=2 mA VOL 0.4 V Input Leakage Current Iin ±10 μA Input Capacitance pF Parameters Symbol Min Typ Max Units MUTE Active Pulse Width (Note 6) ms

Data must be held for sufficient time to bridge the transition time, tfc, of SCL. Figure 1. Control Port Timing - I²C Format

Data must be held for sufficient time to bridge the transition time of CCLK. Figure 2. Control Port Timing - SPI Format

1. TYPICAL CONNECTION DIAGRAM

Figure 3. Typical Connection Diagram

8 ENOut

9 DGND

Figure 4. Detailed Block Diagram

1. APPLICATIONS 5.1 General Description The CS3308 is an 8-channel digitally controlled analog volume control designed for audio systems. It incor- porates a total adjustable range of 118 dB in ¼ dB steps, spread evenly over 96 dB of attenuation and 22 dB of gain. The internal analog architecture includes one op-amp per channel, each with an input resistor network for attenuation and a feedback resistor network for gain. Analog switch arrays are used to select taps in the input and feedback resistor networks, thereby setting the gain or attenuation of each channel. These switch arrays are controlled via the digital control port, bridging the gap between the analog and digital domains. Figure 4 on page 13 provides a detailed diagram of the CS3308’s internal architecture. The CS3308 incorporates highly configurable zero-crossing detection for glitch-free volume level changes. Volume changes may be configured to occur immediately or on a signal zero-crossing. In the event that the signal does not cross zero, the CS3308 provides 8 selectable time-out periods in the range of 5 ms to 50 ms after which the volume level will be changed immediately. When the CS3308 receives more than one vol- ume change command before a zero-crossing or a time-out, the CS3308 is able to implement the previous volume change command immediately or discard it and act only on the most recent command. The “Zero- Crossing Detection” section on page 22 provides a detailed description of the CS3308’s zero-crossing de- tection functionality and controls. The CS3308 includes a comprehensive I²C/SPI serial control port interface for volume changes and device configuration. This interface provides for easy system integration of up to 128 CS3308 devices over a single 2-wire I²C or 3-wire SPI bus, allowing many channels of volume control with minimal system controller I/O requirements. Devices may be addressed on an individual and grouped basis, simplifying simultaneous configuration of a group of channels across multiple devices, while allowing discrete control over all chan- nels on an individual basis. The “System Serial Control Configuration” section on page 23 provides a de- tailed description of the serial control port features and functionality. 5.2 System Design Very few external components are required to support the CS3308. Typical power supply decoupling com- ponents are the only external requirements, as shown in Figure 3 on page 12. 5.2.1 Analog Inputs No external circuitry is required to interface between the audio source and the CS3308’s inputs. However, as with any adjustable gain stage, the affects of a DC offset at the input must be considered. Capacitively coupling the analog inputs may be required to prevent “clicks and pops” which occur with gain changes if an appreciable offset is present. The addition of an input coupling capacitor will form a high-pass filter with the CS3308’s input impedance. Given nominal values of input impedance and coupling capacitor, a 10 µF coupling capacitor will result in less than 0.03 dB of attenuation at 20 Hz. If additional low-frequency attenuation can be tolerated, a small- er coupling capacitor may be used. The CS3308 requires a low source impedance to achieve maximum performance, and a source-imped- ance of 600 Ω or less is recommended. The maximum input level is limited by the input signal swing capability of the internal op-amp. Signals ap- proaching the analog supply voltages may be applied to the analog input pins if the internal attenuator limits the output signal to within 1.35 V of the analog supply rails.

5.2.2 Analog Outputs The analog outputs are capable of driving 2 kΩ loads to within 1.35 V of the analog supply rails and are short-circuit protected to 20 mA. The minimum output load resistance is 2 kΩ; a load smaller than 2 kΩ may cause increased distortion. As the load resistance decreases, the potential for increased internal heating and the possibility of dam- age to the device is introduced. Additionally, the load capacitance should be less than 100 pF. Increased load capacitance may cause increased distortion, and the potential for instability in the output amplifiers. If a low-impedance or high-capacitance load must be driven, an external amplifier should be used to iso- late the outputs of the CS3308. 5.2.3 Recommended Layout, Grounding, and Power Supply Decoupling As with any high-performance device that contains both analog and digital circuitry, careful attention must be provided to power supply and grounding arrangements to optimize performance. Figure 3 on page 12 shows the recommended power arrangements, with VA+, VA-, and VD connected to clean supplies. Power supply decoupling capacitors should be placed as near to the CS3308 as possible, with the low value ceramic capacitor being the nearest. Care should be taken to ensure that there is minimal resis- tance in the analog ground leads to the device to prevent any changes in the defined gain/attenuation set- tings. The use of a unified ground plane is recommended for optimal performance and minimal radiated noise. The CS3308 evaluation board demonstrates the optimum layout and power supply arrangements. Should the printed circuit board have separate analog and digital regions with independent ground planes, the CS3308 should reside in the analog region of the board. Extensive use of ground plane fill on the circuit board will yield large reductions in radiated noise effects. 5.3 Power-Up and Power-Down The CS3308 will remain in a completely powered-down state with the control port inaccessible until the RE- SET pin is brought high. Once RESET is high, the control port will be accessible, but the internal amplifiers will remain powered-down until the PDN_ALL bit is cleared. To bring a channel out of power-down, both the PDN_ALL and the channel’s PDNx bit must be cleared. By default, all channels’ PDNx bits are cleared, and the PDN_ALL bit is set. To minimize audible artifacts during power-up process, the CS3308 automatically holds each channel’s volume at mute until its amplifier has completed its power-up sequence. Once the power-up process is complete, each channel’s volume will au- tomatically be set to the correct level according to the CS3308’s control port settings. To place a channel in power-down, either the channel’s PDNx bit or the PDN_ALL bit must be set. To min- imize audible artifacts during the power-down process, the CS3308 automatically places each channel in mute before the amplifier begins its power-down sequence. The power-up and power-down muting/volume changes are implemented as dictated by the zero-crossing detection settings (see “Zero-Crossing Detection” on page 22). If an immediate power-up or power-down is required, the zero-crossing mode should be set to immediate before changing the power-down state of the device or channel. Referenced Control Register Location

5.3.1 Recommended Power-Up Sequence Hold RESET low until the power supplies are stable. In this state, the control port is reset to its default settings. Bring RESET high. The device will remain in a low power state with the PDN_ALL bit set by default. The control port will be accessible. The desired register settings can be loaded while the PDN_ALL bit remains set. Clear the PDN_ALL bit to initiate the power-up sequence. 5.3.2 Recommended Power-Down Sequence Set the PDN_ALL bit to mute all channels and power-down all internal amplifiers. If desired, hold RESET low to bring the CS3308’s power consumption to an absolute minimum.

5.5 Volume Controls The CS3308 provides comprehensive volume control functionality, allowing each channel’s volume to be changed on an individual or master basis. Refer to the “Volume & Muting Control Architecture” section on page 17 for complete details about the configuration of the CS3308’s individual and master controls. The CS3308 incorporates zero-crossing detection capabilities, and all volume changes are implemented as dictated by the zero-crossing detection settings (see “Zero-Crossing Detection” on page 22). 5.5.1 Individual Channel Volume Controls The CS3308 provides 8 individual channel volume controls. These controls can be used to independently gain and/or attenuate each of the input/output channels over a range of +22 dB to -96 dB in ¼ dB steps. Each channel has a corresponding Ch. X Volume register used to gain or attenuate the channel from +22 dB to -96 dB in ½ dB steps. The ¼ dB Control register contains one bit per channel used to add an additional ¼ dB gain to the channel’s volume as set by its Ch. X Volume register. 5.5.2 Master Volume Controls The CS3308 master volume controls allow the user to simultaneously gain or attenuate a user defined set of channels from +22 dB to -96 dB in ¼ dB increments. A total of 3 master volume controls, Master 1, Master 2, and Master 3, are provided for comprehensive and flexible control. Each master volume control has a corresponding Master X Volume register which is used to gain or at- tenuate the control’s respective unmasked channels from +22 dB to -96 dB in ½ dB steps. The LSB of the corresponding Master X Control register contains one bit used to add an additional ¼ dB gain to the mas- ter volume control’s value as set by its Master X Volume register. As discussed in the “Volume & Muting Control Architecture” section on page 17, each master volume con- trol has a corresponding Master X Mask register which allows the user to select which channels are af- fected by the control. By default, each master control is configured to affect all channels within the device. The effective volume setting of an individual channel is determined by the following equation: EffVolChN = IndividualChN + (Master 1 & Mask 1ChN) + (Master 2 & Mask 2ChN) + (Master 3 & Mask 3ChN) In this equation, EffVolChN represents the actual gain or attenuation level, in dB, of the individual channel “N” as determined by the its constituent volume settings within the CS3308. The effective volume is limited to the range of +22 dB to -96 dB; see “Volume Limits” on page 20. IndividualChN is the individual channel volume setting in dB as set by the channel’s individual volume con- trol register and ¼ dB bit (see “Individual Channel Volume Controls” on page 19). Master X is the Master X volume setting in dB as set by the master volume control registers and their re- spective ¼ dB bits. Mask XChN is the channel N mask bit associated with the Master X volume control setting. This volume control architecture in combination with the multiple group addressing capabilities of the CS3308 (as detailed in section 5.8.2 on page 24) allows easy volume control of multiple channels across multiple devices in a system while eliminating the system controller overhead typically associated digitally driven analog volume control devices. Referenced Control Register Location Equation 1. Effective Volume Setting

Table 1 shows example volume settings using individual and master volume controls. Refer to Figure 6 on page 18 for a graphical representation of the volume controls’ functionality. +22 dB to -96 dB. Values outside this range may, however, be written to the CS3308’s internal registers. channel’s volume will be set to +22 dB. Table 1. Example Volume Settings

5.6 Muting Controls The CS3308 provides flexible muting capabilities to complement its comprehensive volume control abilities. Each channel’s mute state may be controlled on an individual channel basis, by any of 3 master mute con- trols, and by the hardware MUTE input pin. The mute state of any channel within the CS3308 is determined by the logical OR of four conditions, and the channel will mute if any one or more of the conditions are met. These conditions are: The channel’s individual mute condition is set. One or more of the channel’s unmasked master mute conditions are set. The hardware mute input is enabled and active. The channel’s effective volume (See Equation 1 on page 19) is less than -96 dB. The CS3308 incorporates zero-crossing detection capabilities, and all muting changes are implemented as dictated by the zero-crossing detection settings (see “Zero-Crossing Detection” on page 22). 5.6.1 Individual Channel Mute Controls The CS3308 provides 8 individual channel mute controls. These controls can be used to individually mute each of the input/output channels independent of all other volume and mute settings. Individual channel mute control is accomplished by setting or clearing the channel’s corresponding MuteChX bit in the Mute Control register. 5.6.2 Master Mute Controls The CS3308 master mute controls allow the user to simultaneously control the mute state of all channels, or a user-defined subset of all channels within a device. A total of 3 master mute controls, M1_Mute, M2_Mute, and M3_Mute, are provided for comprehensive and flexible control. Master mute control is accomplished by setting or clearing the MX_Mute bit in the corresponding Master Control register. Each master mute control affects only those channels unmasked in its corresponding Master X Mask register. 5.6.3 Hardware Mute Control The CS3308 implements a hardware MUTE input pin to allow the user to control the mute state of all chan- nels with an external level-active signal. By default, the MUTE input is configured for active low operation, and all channels will be held in a mute state whenever this input is low. For enhanced flexibility, setting the MutePolarity bit will configure the MUTE input pin for active high op- eration. Additionally, the EnMuteIn bit may be cleared to disable the CS3308’s response to the MUTE in- put signal. Referenced Control Register Location Referenced Control Register Location “Master 2 Mute (Bit 1)” on page 38 “Master 3 Mute (Bit 1)” on page 39 “Master 2 Mask - Address 13h” on page 37 “Master 3 Mask - Address 16h” on page 38 Referenced Control Register Location

hanced flexibility. Zero-crossing detection and time-out is implemented independently for each channel. ods ranging from 5 ms to 50 ms; these are shown in Table 3. bits in the Device Config 2 register. The time-out period is set to 18 ms (setting 3) by default. Volume changes take effect immediately. ting will take effect when a zero-crossing is detected or the time-out period elapses. zero-crossing is detected or the time-out period elapses. Table 2. Zero-Crossing Modes Table 3. Zero-Crossing Time-Out Periods

standard I²C or SPI bus protocol. isters, may be set to the same value across multiple CS3308’s on the shared serial communication bus. located in the LSB of its respective Group address register, must be set. Up to 128 CS3308’s sharing the same CS signal may be connected to a common SPI serial control bus. must be connected as shown in Figure 9. Figure 9. SPI Serial Control Connections

able Next Device (Bit 0)” on page 41) is set, at which time the ENOut signal will be driven high. grams this configuration process. the Enable bit set) to the Individual address register. each subsequent device in a reset state. addressed with this new Individual device address. addressed with its Group 1 or Group 2 address. communication cycle is initiated. chain out of its reset state. new Individual device address. Figure 10. Individual Device Address Configuration Process

SPI communication cycle using the device’s newly assigned Individual device addresses. able Next Device (Bit 0)” on page 41) is set, at which time the ENOut signal will be driven high. grams this configuration process. the Enable bit set) to the Individual address register. I²C communication cycle using the device’s newly assigned Individual device addresses. Figure 11. I²C Serial Control Connections

the clock is high. All other transitions of SDA occur while the clock is low. either the Individual, Group 1, or Group 2 device address as set by their respective control port registers. bus until a Stop and Start condition occurs. input to the CS3308 from the microcontroller after each transmitted byte. Table 4. I²C Mode Default Chip Address Figure 12. Control Port Timing, I²C Write

clocked in on the rising edge of CCLK. The default chip address in SPI Mode is 1000000b. next eight bits are the data which will be placed into the register designated by the MAP. crement after each byte is written, allowing block writes of successive registers. Figure 13. Control Port Timing, I²C Read

1 Byte

Figure 14. SPI Write Cycle

1. CS3308 REGISTER QUICK REFERENCE This table shows the register names and their associated default values. Addr Function 01h Ch. 1 Volume Vol7 Vol6 Vol5 Vol4 Vol3 Vol2 Vol1 Vol0 page 31 02h Ch. 2 Volume Vol7 Vol6 Vol5 Vol4 Vol3 Vol2 Vol1 Vol0 page 31 03h Ch. 3 Volume Vol7 Vol6 Vol5 Vol4 Vol3 Vol2 Vol1 Vol0 page 31 04h Ch. 4 Volume Vol7 Vol6 Vol5 Vol4 Vol3 Vol2 Vol1 Vol0 page 31 05h Ch. 5 Volume Vol7 Vol6 Vol5 Vol4 Vol3 Vol2 Vol1 Vol0 page 31 06h Ch. 6 Volume Vol7 Vol6 Vol5 Vol4 Vol3 Vol2 Vol1 Vol0 page 31 07h Ch. 7 Volume Vol7 Vol6 Vol5 Vol4 Vol3 Vol2 Vol1 Vol0 page 31 08h Ch. 8 Volume Vol7 Vol6 Vol5 Vol4 Vol3 Vol2 Vol1 Vol0 page 31 09h ¼ dB Control Quarter8 Quarter7 Quarter6 Quarter5 Quarter4 Quarter3 Quarter2 Quarter1 page 32 0Ah Mute Control MuteCh8 MuteCh7 MuteCh6 MuteCh5 MuteCh4 MuteCh3 MuteCh2 MuteCh1 page 33 0Bh Device Config 1 Reserved Reserved EnMuteIn MutePolarity Ch8=7 Ch6=5 Ch4=3 Ch2=1 page 33 0Ch Device Config 2 Reserved Reserved Reserved TimeOut2 TimeOut1 TimeOut0 ZCMode1 ZCMode0 page 34 0Dh Channel Power PDN8 PDN7 PDN6 PDN5 PDN4 PDN3 PDN2 PDN1 page 35 0Eh Master Power Reserved Reserved Reserved Reserved Reserved Reserved Reserved PDN_ALL page 35 0Fh Freeze Control Reserved Reserved Reserved Reserved Reserved Reserved Reserved Freeze page 36

M1_Ch8M M1_Ch7M M1_Ch6M M1_Ch5M M1_Ch4M M1_Ch3M M1_Ch2M M1_Ch1M page 36 11h Master 1 Vol- ume M1_Vol7 M1_Vol6 M1_Vol5 M1_Vol4 M1_Vol3 M1_Vol2 M1_Vol1 M1_Vol0 page 36 12h Master 1 Con- trol Reserved Reserved Reserved Reserved Reserved Reserved M1_Mute M1_Qtr page 37 13h Master 2 Mask M2_Ch8M M2_Ch7M M2_Ch6M M2_Ch5M M2_Ch4M M2_Ch3M M2_Ch2M M2_Ch1M page 37 14h Master 2 Vol- ume M2_Vol7 M2_Vol6 M2_Vol5 M2_Vol4 M2_Vol3 M2_Vol2 M2_Vol1 M2_Vol0 page 37 15h Master 2 Con- trol Reserved Reserved Reserved Reserved Reserved Reserved M2_Mute M2_Qtr page 38 16h Master 3 Mask M3_Ch8M M3_Ch7M M3_Ch6M M3_Ch5M M3_Ch4M M3_Ch3M M3_Ch2M M3_Ch1M page 38 17h Master 3 Vol- ume M3_Vol7 M3_Vol6 M3_Vol5 M3_Vol4 M3_Vol3 M3_Vol2 M3_Vol1 M3_Vol0 page 38 18h Master 3 Con- trol Reserved Reserved Reserved Reserved Reserved Reserved M3_Mute M3_Qtr page 39 19h Group 2 Chip Addr G2_Addr6 G2_Addr5 G2_Addr4 G2_Addr3 G2_Addr2 G2_Addr1 G2_Addr0 EnG2Addr page 40 X 1Ah Group 1 Chip Addr G1_Addr6 G1_Addr5 G1_Addr4 G1_Addr3 G1_Addr2 G1_Addr1 G1_Addr0 EnG1Addr page 40 X 1Bh Individual Chip Addr Ind_Addr6 Ind_Addr5 Ind_Addr4 Ind_Addr3 Ind_Addr2 Ind_Addr1 Ind_Addr0 Enable page 41 X 1Ch Chip ID ID3 ID2 ID1 ID0 Rev3 Rev2 Rev1 Rev0 page 41 X X X X Addr Function

1. CS3308 REGISTER DESCRIPTIONS

and write-only in SPI Mode, unless otherwise noted. resolution volume setting down to ½ dB resolution.

• QuarterX = ‘0’. See “¼ dB Control (Bit 0 - 7)” on page 32.

Table 5. Example Volume Settings

“Device Configuration 2 - Address 0Ch” on page 34). Table 6 shows example volume settings using the ¼ dB control. Table 6. Example Volume Settings

7.3 Mute Control - Address 0Ah 7.3.1 Mute Channel X (Bit 0 - 7) Default = 0 Function: Each bit controls the individual mute state of its respective channel. When set, the mute condition is active. When cleared, the mute condition is released. See “Muting Controls” on page 21 for more information about the muting behavior of the CS3308. 7.4 Device Configuration 1 - Address 0Bh (Bit 5) 7.4.1 Enable MUTE Input (Bit 5) Default = 1 Function: When set, the MUTE input pin is enabled and will generate a mute condition when active. When cleared, the MUTE input pin is ignored and will not generate a mute condition. 7.4.2 MUTE Input Polarity (Bit 4) Default = 0 Function: This bit controls the active level of the MUTE input pin. When set, the mute condition is active when the MUTE pin is high. When cleared, the mute condition is active when the MUTE pin is low. MuteCh8 MuteCh7 MuteCh6 MuteCh5 MuteCh4 MuteCh3 MuteCh2 MuteCh1 Reserved Reserved EnMuteIn MutePolarity Ch8=7 Ch6=5 Ch4=3 Ch2=1

the Channel A volume and muting register settings, and the Channel B register settings are ignored. trolled by the A and B volume and muting bits. Time-Out” section on page 22 for more information. settings. Channel 8 register settings are ignored. settings. Channel 6 register settings are ignored. Table 7. Channel B = Channel A Settings Table 8. Zero-Crossing Time-Out Settings

ing Modes” section on page 22 for more information. bit must be cleared for normal operation to occur. their contents are retained while the device is in power-down. Volume changes take effect immediately. take effect when a zero-crossing is detected or the time-out period elapses. a zero-crossing is detected or the time-out period elapses. Table 9. Zero-Crossing Mode Settings

7.8 Freeze Control - Address 0Fh 7.8.1 Freeze (Bit 7) Default = 0 Function: When the Freeze bit is set, the Freeze function allows modifications to the control port registers with- out changes taking effect until Freeze bit is cleared. To make multiple changes in the Control Port registers take effect simultaneously, set the Freeze bit, make all register changes, then clear the Freeze bit. 7.9 Master 1 Mask - Address 10h Each bit in this register serves as a Master 1 mask for its corresponding channel. If a mask bit is set to ‘1’, the corresponding channel is unmasked, meaning that it will be affected by the Master 1 volume and muting controls. If a mask bit is set to ‘0’, the corresponding channel is masked, meaning that it will not be affected by the Master 1 volume and muting controls. This register defaults to FFh (all channels unmasked). 7.10 Master 1 Volume - Address 11h 7.10.1 Master 1 Volume Control (Bits 7:0) Default = 11010010 Function: The Master 1 volume control register allows the user to simultaneously gain or attenuate all un- masked channels in 0.5 dB increments. The volume changes are implemented as dictated by the ZC- Mode[1:0] and TimeOut[2:0] bits in the Device Config 2 register (see “Device Configuration 2 - Address 0Ch” on page 34). The value of the Master 1 volume control register is mapped to the desired 0.5 dB step Master 1 vol- ume setting by the following equation: In the equation above, “Desired Volume Setting in dB” is determined by rounding the desired ¼ dB resolution volume setting down to ½ dB resolution. It should be noted that input values outside the CS3308’s analog range of +22 dB to -96 dB are valid, however, the volume of each channel will be limited to the CS3308’s analog range (see “Volume Lim- its” on page 20). See Table 5 on page 31 for example register settings. Reserved Reserved Reserved Reserved Reserved Reserved Reserved Freeze M1_Ch8M M1_Ch7M M1_Ch6M M1_Ch5M M1_Ch4M M1_Ch3M M1_Ch2M M1_Ch1M M1_Vol7 M1_Vol6 M1_Vol5 M1_Vol4 M1_Vol3 M1_Vol2 M1_Vol1 M1_Vol0 Register Value Desired Volume Setting in dB 210

7.11 Master 1 Control - Address 12h 7.11.1 Master 1 Mute (Bit 1) Default = 0 Function: This bit controls the Master 1 mute state. When set, the Master 1 mute condition is active. When cleared, the Master 1 mute condition is released. See “Muting Controls” on page 21 for more information about the muting behavior of the CS3308. 7.11.2 Master 1 ¼ dB Control (Bit 0) Default = 0 Function: When set, ¼ dB of gain will be added to the Master 1 volume level. See Table 6 on page 32 for an example of volume settings using the ¼ dB control. 7.12 Master 2 Mask - Address 13h Each bit in this register serves as a Master 2 mask for its corresponding channel. If a mask bit is set to ‘1’, the corresponding channel is unmasked, meaning that it will be affected by the Master 2 volume and muting controls. If a mask bit is set to ‘0’, the corresponding channel is masked, meaning that it will not be affected by the Master 2 volume and muting controls. This register defaults to FFh (all channels unmasked). 7.13 Master 2 Volume - Address 14h 7.13.1 Master 2 Volume Control (Bits 7:0) Default = 11010010 Function: The Master 2 volume control register allows the user to simultaneously gain or attenuate all un- masked channels from +22 dB to -96 dB in 0.5 dB increments. The volume changes are implemented as dictated by the ZCMode[1:0] and TimeOut[2:0] bits in the Device Config 2 register (see “Device Configuration 2 - Address 0Ch” on page 34). The value of the Master 2 volume control register is mapped to the desired 0.5 dB step Master 2 vol- ume setting by the following equation: Reserved Reserved Reserved Reserved Reserved Reserved M1_Mute M1_Qtr M2_Ch8M M2_Ch7M M2_Ch6M M2_Ch5M M2_Ch4M M2_Ch3M M2_Ch2M M2_Ch1M M2_Vol7 M2_Vol6 M2_Vol5 M2_Vol4 M2_Vol3 M2_Vol2 M2_Vol1 M2_Vol0 Register Value Desired Volume Setting in dB 210

In the equation above, “Desired Volume Setting in dB” is determined by rounding the desired ¼ dB resolution volume setting down to ½ dB resolution. It should be noted that input values outside the CS3308’s analog range of +22 dB to -96 dB are valid; however, the volume of each channel will be limited to the CS3308’s analog range (see “Volume Lim- its” on page 20). See Table 5 on page 31 for example register settings. 7.14 Master 2 Control - Address 15h 7.14.1 Master 2 Mute (Bit 1) Default = 0 Function: This bit controls the Master 2 mute state. When set, the Master 1 mute condition is active. When cleared, the Master 2 mute condition is released. See “Muting Controls” on page 21 for more information about the muting behavior of the CS3308. 7.14.2 Master 2 ¼ dB Control (Bit 0) Default = 0 Function: When set, ¼ dB of gain will be added to the Master 2 volume level. See Table 6 on page 32 for an example of volume settings using the ¼ dB control. 7.15 Master 3 Mask - Address 16h Each bit in this register serves as a Master 3 mask for its corresponding channel. If a mask bit is set to ‘1’, the corresponding channel is unmasked, meaning that it will be affected by the Master 3 volume and muting controls. If a mask bit is set to ‘0’, the corresponding channel is masked, meaning that it will not be affected by the Master 3 volume and muting controls. This register defaults to FFh (all channels unmasked). 7.16 Master 3 Volume - Address 17h 7.16.1 Master 3 Volume Control (Bits 7:0) Default = 11010010 Function: The Master 3 volume control register allows the user to simultaneously gain or attenuate all un- masked channels from +22 dB to -96 dB in 0.5 dB increments. The volume changes are implemented Reserved Reserved Reserved Reserved Reserved Reserved M2_Mute M2_Qtr M3_Ch8M M3_Ch7M M3_Ch6M M3_Ch5M M3_Ch4M M3_Ch3M M3_Ch2M M3_Ch1M M3_Vol7 M3_Vol6 M3_Vol5 M3_Vol4 M3_Vol3 M3_Vol2 M3_Vol1 M3_Vol0

as dictated by the ZCMode[1:0] and TimeOut[2:0] bits in the Device Config 2 register (see “Device Configuration 2 - Address 0Ch” on page 34). The value of the Master 3 volume control register is mapped to the desired 0.5 dB step Master 3 vol- ume setting by the following equation: In the equation above, “Desired Volume Setting in dB” is determined by rounding the desired ¼ dB resolution volume setting down to ½ dB resolution. It should be noted that input values outside the CS3308’s analog range of +22 dB to -96 dB are valid, however, the volume of each channel will be limited to the CS3308’s analog range (see “Volume Lim- its” on page 20). See Table 5 on page 31 for example register settings. 7.17 Master 3 Control - Address 18h 7.17.1 Master 3 Mute (Bit 1) Default = 0 Function: This bit controls the Master 3 mute state. When set, the Master 3 mute condition is active. When cleared, the Master 3 mute condition is released. See “Muting Controls” on page 21 for more information about the muting behavior of the CS3308. 7.17.2 Master 3 ¼ dB Control (Bit 0) Default = 0 Function: When set, ¼ dB of gain will be added to the Master 3 volume level. See Table 6 on page 32 for an example of volume settings using the ¼ dB control. Reserved Reserved Reserved Reserved Reserved Reserved M3_Mute M3_Qtr Register Value Desired Volume Setting in dB 210

7.18 Group 2 Chip Address 19h 7.18.1 Group 2 Chip Address (Bits 7:1) SPI Mode Default = 1000000b I²C Mode Default = See Table 4 on page 27. Function: These bits set the Group 2 chip address, and may be modified at any time. See “System Serial Con- trol Configuration” on page 23 and “I²C/SPI Serial Control Formats” on page 27 for more information. 7.18.2 Enable Group 2 Address (Bit 0) Default = 0 Function: This bit controls the device’s recognition of the Group 2 address. When set, the device will respond to serial communication when addressed with the Group 2 address. When cleared, the device will ig- nore all serial communication when addressed with the Group 2 address. 7.19 Group 1 Chip Address 1Ah 7.19.1 Group 1 Chip Address (Bits 7:1) SPI Mode Default = 1000000b I²C Mode Default = See Table 4 on page 27. Function: These bits set the Group 1 chip address, and may be modified at any time. See “System Serial Con- trol Configuration” on page 23 and “I²C/SPI Serial Control Formats” on page 27 for more information. 7.19.2 Enable Group 1 Address (Bit 0) Default = 0 Function: This bit controls the device’s recognition of the Group 1 address. When set, the device will respond to serial communication when addressed with the Group 1 address. When cleared, the device will ig- nore all serial communication when addressed with the Group 1 address. G2_Addr6 G2_Addr5 G2_Addr4 G2_Addr3 G2_Addr2 G2_Addr1 G2_Addr0 EnG2Addr G1_Addr6 G1_Addr5 G1_Addr4 G1_Addr3 G1_Addr2 G1_Addr1 G1_Addr0 EnG1Addr

trol Configuration” on page 23 and “I²C/SPI Serial Control Formats” on page 27 for more information. enable output pin (ENOut) will be driven low. This is a Read-Only register. Chip ID code for the CS3308. Permanently set to 1110. Chip revision code for the CS3308. Encoded as shown in Table 10. Table 10. Chip Revision Register Codes

1. PARAMETER DEFINITIONS Dynamic Range Full-scale (RMS) signal to broadband noise ratio. The broadband noise is measured over the specified bandwidth with the input grounded. Expressed in decibels. Total Harmonic Distortion + Noise The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels. Frequency Response A measure of the amplitude response variation from 10 Hz to 20 kHz relative to the amplitude response at 1 kHz. Units in decibels. Interchannel Isolation A measure of crosstalk between channels. Measured for each channel at the device’s output with a full- scale signal applied to one channel adjacent to the channel under test, and no signal applied to all other channels. Units in decibels. Gain Error The deviation from the nominal full-scale analog output for a full-scale digital input. Gain Drift The change in gain value with temperature. Units in ppm/°C.

1. PACKAGE DIMENSIONS 10.THERMAL CHARACTERISTICS AND SPECIFICATIONS θJA is specified according to JEDEC specifications for multi-layer PCBs. INCHES MILLIMETERS DIM MIN NOM MAX MIN NOM MAX A --- 0.055 0.063 --- 1.40 1.60 0.002 0.004 0.006 0.05 0.10 0.15 B 0.007 0.009 0.011 0.17 0.22 0.27 D 0.343 0.354 0.366 8.70

9.0 BSC

9.30 0.272 0.28 0.280 6.90

7.0 BSC

7.10 E 0.343 0.354 0.366 8.70 9.30 0.272 0.28 0.280 6.90 7.10 0.016 0.020 0.024 0.40

0.50 BSC

0.60 L 0.018 0.24 0.030 0.45 0.60 0.75 0.000° 7.000° 0.00° 7.00° * Nominal pin pitch is 0.50 mm *Controlling dimension is mm. *JEDEC Designation: MS022 Parameters Symbol Min Typ Max Units Package Thermal Resistance (Note 1) 48-LQFP θJA θJC °C/Watt °C/Watt Allowable Junction Temperature 125 48L LQFP PACKAGE DRAWING E D e B L A

11.ORDERING INFORMATION 12.REVISION HISTORY Product Order # CS3308 8-Channel Analog Volume Control 48-pin LQFP YES Commercial -10° to +70° C Tray CS3308-CQZ Tape & Reel CS3308-CQZR CDB3308 CS3308 Evaluation Board No CDB3308 Release Changes Initial Release of Advance Datasheet PP1 Initial Release of Preliminary Datasheet Updated THD+N shown on cover page. Updated THD+N specification in the Analog Characteristics table on page 8 Updated Supply Current specifications in the Analog Characteristics table on page 8. Updated Power Consumption specification in the Analog Characteristics table on page 8. Updated Input/Output Voltage Range specification in the Analog Characteristics table on page 8. Updated Chip Revision bit description shown on page 41. Final Release Contacting Cirrus Logic Support For all product questions and inquiries, contact a Cirrus Logic Sales Representative. To find the one nearest you, go to www.cirrus.com. IMPORTANT NOTICE Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives con- sent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROP- ERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DE- VICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDER- STOOD TO BE FULLY AT THE CUSTOMER’S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER’S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS’ FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. I²C is a registered trademark of Philips Semiconductor. SPI is a trademark of Motorola, Inc.