CS3301A CIRRUS | Alldatasheet

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Copyright © Cirrus Logic, Inc. 2007 (All Rights Reserved)http://www.cirrus.com CS3301A Low-noise, Programmable Gain, Differential Amplifier Features & Desription z Signal Bandwidth: DC to 2 kHz z Selectable Gain: x1, x2, x4, x8, x16, x32, x64 z Differential Inputs, Differential Outputs

  • Multiplexed inputs: INA, INB, 800 Ω termination
  • Rough / fine outputs for CS5371A / 72A / 73A
  • Max signal amplitude: 5 V pp differential
  • Low input bias: 1 nA typical z Outstanding Noise Performance
  • 8.5 from 0.1 Hz to 2 kHz
  • 0 . 1 8 0µVp-p between 0.1 Hz and 10 Hz z Low Total Harmonic Distortion
  • -121 dB THD typical (0.0000891%)
  • -112 dB THD maximum (0.0002512%) z Low Power Consumption
  • Normal operation: 5.5 mA typical
  • Power down: 10 µA typical z Small 24-pin SSOP Package z Bipolar Power Supply Configuration

Description

The CS3301A is a low-noise differential input, dif- ferential output amplifier with programmable gain, optimized for amplifying signals from low-imped- ance sensors such as geophones. The gain settings are binary weighted (x1, x2, x4, x8, x16, x32, x64) and are selected using simple pin set- tings. Two sets of external inputs, INA and INB, simplify system design as inputs from a sensor and test DAC. An internal 800 Ω termination can also be selected for noise tests. Amplifier noise performance is outstanding with a noise density of 8.5 over the 0.1 Hz to 2 kHz bandwidth. Distortion performance is also ex- tremely good, typically -121 dB THD at x1 gain. Flat noise down to 0.1 Hz and low total harmonic distor- tion make this amplifier ideal for low-frequency, low-amplitude, differential signals requiring maxi- mum dynamic range.

ORDERING INFORMATION

See page 15. nV/ Hz nV/ Hz INA+ INB+ MUX0 MUX1 INB- INA- VA+ VA- VD GND CLK OUTR+ OUTF+ GAIN0 GAIN1 GAIN2 OUTF- OUTR- PWDN 400 Ω 400 Ω MAR ‘07 DS757F1

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  1. CHARACTERISTICS AND SPECIFICATIONS
  • Min / Max characteristics and spec ifications are guaranteed over the Specified Operating Conditions.
  • Typical performance characteristics and specificatio ns are measured at nominal supply voltages and TA = 25°C.
  • GND = 0 V. Single-ended voltages with respect to GND, differential voltages with respect to opposite half.
  • Device is connected as shown in Figure 5 on page 12 unless otherwise noted. SPECIFIED OPERATING CONDITIONS Notes: 1. VA- must be the most negative voltag e to avoid potential SCR latch-up conditions. 2. VD must conform to Digit al Supply Differential under Absolute Maximum Ratings. ABSOLUTE MAXIMUM RATINGS WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. Notes: 3. Transient currents up to ±100 mA will not cause SCR latch-up. TEMPERATURE CONDITIONS Parameter Symbol Min Nom Max Unit Bipolar Power Supplies Positive Analog ± 2% VA+ 2.45 2.50 2.55 V Negative Analog ( Note 1) ± 2% VA- -2.55 -2.50 -2.45 V Positive Digital ( Note 2) ± 3% VD 3.20 3.30 3.40 V Thermal Ambient Operating Temperature Industrial (-IS, -ISZ) T A -40 25 85 °C Parameter Symbol Min Max Parameter DC Power Supplies Positive Analog Negative Analog Digital VA+ VA- VD -0.5 -6.8 -0.5 6.8 0.5 6.8 V V V Analog Supply Differential [(VA+) - (VA-)] VA DIFF -6 . 8 V Digital Supply Differential [(VD) - (VA-)] VD DIFF -6 . 8 V Input Current, Power Supplies ( Note 3)I PWR -± 5 0 m A Input Current, Any Pin Except Supplies ( Note 3)I IN -± 1 0 m A Output Current ( Note 3)I OUT -± 2 5 m A Power Dissipation PD - 500 mW Analog Input Voltages V INA (VA-) - 0.5 (VA+) + 0.5 V Digital Input Voltages V IND -0.5 (VD) + 0.5 V Storage Temperature Range T STG -65 150 ºC Parameter Symbol Min Typ Max Unit Ambient Operating Temperature T A -40 - 85 ºC Storage Temperature Range T STR -65 - 150 ºC Allowable Junction Temperature T JCT -- 1 2 5 º C Junction to Ambient Thermal Impedance ΘJA - 65 - ºC / W

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Notes: 4. Guaranteed by design and/or characterization.

  1. Tested with a full scale input signal of 31.25 Hz.

Figure 1. CS3301A Noise Performance

ANALOG CHARACTERISTICS (CONT.) 6. Common mode signals pass unchanged through the differential amplifier architecture and are rejected by the CS5371A / 72A / 73A modulator CMRR. 7. Absolute gain accuracy tests the matching of x1 gain across multiple CS3301A devices. 8. Relative gain accuracy tests the tra cking of x2, x4, x8, x16, x32, x64 gain relative to x1 gain on a single CS3301A device. 9. Specification is for the parameter over the specif ied temperature range and is for the CS3301A device only. It does not include the effects of external components. 10. Offset voltage is tested with the amplif ier inputs connected to the internal 800 Ω termination. 11. The absolute offset after calibration specification ap plies to the effective offset voltage of the CS3301A output when used with the CS5371A / 72A / 73A modulator and CS5376A / 78 digital filter, and is measured from the digitally calibrated output codes of the digital filter. 12. The CS3301A offset calibration is performed di gitally with the CS5371A / 72A / 73A modulator and CS5376A / 78 digital filter and includes the full scale signal range. Calibration offsets of greater than ± 5% of full scale will begin to subtract from system dynamic range. Parameter Symbol CS3301A UnitMin Typ Max Gain Gain, Differential GAIN x1 - x64 Gain, Common Mode ( Note 6)G A I N CM -x 1- Gain Accuracy, Absolute ( Note 7)G A I N ABS -± 1 ± 2 % Gain Accuracy, Relative ( Note 8)2 x GAINREL -0.4 -0.2 0 4x - -0.2 - 8x - -0.2 - 16x - -0.2 - 32x - -0.3 - 64x - -0.3 - Gain Drift ( Note 4, 9)G A I N TC -5- p p m / º C Offset Offset Voltage, Input Referred ( Note 10) OFST - ±5 ±15 µV Offset After Calibration, Absolute ( Note 11)O F S T CAL -± 1- µV Offset Calibration Range ( Note 12)O F S TRNG -1 0 0- % F S Offset Voltage Drift ( Note 4, 9)O F S T TC -0 . 1- µV/º C

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ANALOG CHARACTERISTICS (CONT.) Notes: 13. Ratio of input common mode amplitude vs. output differential mode amplitude for a perfectly matched common mode input signal. Characterized with a 50 Hz, 500 mVpeak common mode sine wave applied to the analog inputs. 14. Output impedance characteristic s are approximate and can vary up to ±30% depending on process parameters. Parameter Symbol CS3301A UnitMin Typ Max Analog Input Characteristics Input Signal Frequencies BW DC - 2000 Hz Input Voltage Range (Vcm ± Signal) x1 x2 to x64 V IN (VA-)+0.7 (VA-)+0.7 (VA+)-1.25 (VA+)-1.75 V Full Scale Input, Differential x1 x16 x32 x64 V INFS - 2.5 1.25 625 312.5 156.25 78.125 V p-p Vp-p Vp-p mVp-p mVp-p mVp-p mVp-p Input Impedance, Differential Z INDIFF -1 , 5 0- G Ω, pF Input Impedance, Common Mode Z INCM -1- M Ω Input Bias Current I IN -12 n A Crosstalk, Multiplexed Inputs ( Note 4)X T - - 1 3 0 - d B Common to Differential Mode Rejection ( Note 4, 7, 13)C D M R 9 5 1 2 0 - d B Analog Output Characteristics Full Scale Output, Differential V OUT --5 V p-p Output Voltage Range (Vcm ± Signal) V RNG (VA-)+0.5 - (VA+)-0.5 V Output Impedance (Note 14)Z OUT -4 0- Ω Output Impedance Drift (Note 14)Z TC -0 . 2 4- Ω/°C Output Current I OUT -- ± 2 5 m A Load Capacitance C L --1 n F

Notes: 15. Device is intended to be driven with CMOS logic levels.

  1. When CLK is tied to GND, an in ternal oscillator provides a master clock at approximately 2 MHz. CLK

should be driven for synchronous system operation. Figure 2. Digital Input Rise and Fall Times Table 1. Digital Selections for Gain and Input Mux Control

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POWER SUPPLY CHARACTERISTICS Notes: 17. All outputs unloaded. Analog inputs connected to the internal 800 Ω termination. Digital inputs forced to VD or GND respectively. 18. Power supply rejection characterized with a 50 Hz , 400 mVp-p sine wave applied separately to each supply. Parameter Symbol CS3301A UnitMin Typ Max Power Supply Current, Normal Analog Power Supply Current ( Note 17)I A -5 . 5 6 . 8 m A Digital Power Supply Current ( Note 17)I D - 0.2 0.25 mA Power Supply Current, Power Down (PWDN=1) Analog Power Supply Current ( Note 17)I A -8 1 2 µA Digital Power Supply Current ( Note 17)I D -28 µA Power Supply Rejection Power Supply Rejection Ratio ( Note 4, 18) PSRR 100 120 - dB

using a CS3301A, CS5373A, and CS5378.

2.1 Analog Signals

2.1.1 Analog Inputs

input is connected to the amplifier.

2.1.2 Analog Outputs

Figure 3. Multi-Channel System Architecture

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2.1.3 Differential Signals

properly read 1.767 Vrms, or 5 Vpp.

2.2 Digital Signals

2.2.1 Clock Input

clock and use an external clock if one is supplied. pin should be connected to GND.

2.2.2 Gain Selection

2.2.3 Mux Selection

Figure 4. Single-Channel System Architecture

made using the MUX0 and MUX1 pins as shown in Table 1 on page 7. Although a mux selection is provided to enable the INA and INB switches simultaneously, signal cur- rent should not be driven through them in this mode. The CS3301A mux switches will maintain good linearity only with minimal signal currents.

2.2.4 Power Down Selection

A power-down mode is available to shut down the amplifier when not in use. When enabled, all inter- nal circuitry is disabled, the analog inputs and out- puts go high-impedance, a nd the device enters a micro-power state. Powe r down mode is selected using the PWDN pin, which is active high.

2.3 Power Supplies

2.3.1 Analog Power Supplies

The analog power pins of the CS3301A are speci- fied to run from bipolar ±2.5 V power supplies. When using bipolar power supplies, the analog sig- nal common mode voltage should be biased to 0 V. The analog power supplies are recommended to be bypassed to system ground using 0.1 µF X7R type capacitors. The VA- supply is connect ed to the CMOS sub- strate and as such must remain the most negative applied voltage. It is re commended to clamp the VA- supply to system gr ound using a reversed bi- ased Schottky diode to prevent possible damage re- lated to mis-matched power supply initialization.

2.3.2 Digital Power Supplies

The digital voltage across the VD and GND pins is specified for a +3.3 V pow er supply. The digital power supply should be bypassed to system ground using a 0.01 µF X7R type capacitor.

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2.4 Connection Diagram

Figure 5. CS3301A Amplifier Connections

VA+ 1 I Positive analog supply voltage. VA- 4 I Negative analog supply voltage. VD 16 I Positive digital supply voltage. INA+, INA- 5, 6 I Channel A differential analog inputs. Selected via MUX pins. INB+, INB- 8, 7 I Channel B differential analog inputs. Selected via MUX pins. OUTR+, OUTR- 11, 2 O Rough charge differential analog outputs. OUTF+, OUTF- 10, 3 O Fine charge differential analog outputs. I Gain range select. See Gain Selection table in Digital Characteristics section. CLK 13 I Master clock input. Connect to GND to use internal oscillator. PWDN 19 I Power down mode enable. Active high. MUX0, MUX1 24, 23 I Analog input select. See Input Selectio n table in Digital Characteristics section. TEST0 12 I Test mode select, factory use only. Connect to VA- during normal operation. TEST1, TEST2 17, 14 I Test mode select, factory use only. Connect to GND during normal operation. TESTOUT 9O Test mode output, factory use only. No connect during normal operation. Table 2. Pin Descriptions Figure 6. CS3301A Pin Assignments

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  1. PACKAGE DIMENSIONS Notes: 1. “D” and “E1” are reference datums and do not included mold flash or protrusions, but do include mold mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per side. 2. Dimension “b” does not include dambar protrusion /intrusion. Allowable dambar protrusion shall be 0.13 mm total in excess of “b” dimension at maximum material condition. Dambar intrusion shall not reduce dimension “b” by more than 0.07 mm at least material condition. 3. These dimensions apply to the fl at section of the lead between 0.10 and 0.25 mm from lead tips. INCHES MILLIMETERS NOTE DIM MIN MAX MIN MAX A -- 0.084 -- 2.13 A1 0.002 0.010 0.05 0.25 A2 0.064 0.074 1.62 1.88 b 0.009 0.015 0.22 0.38 2,3 D 0.311 0.335 7.90 8.50 1 E 0.291 0.323 7.40 8.20 E1 0.197 0.220 5.00 5.60 1 e 0.024 0.027 0.61 0.69 L 0.025 0.040 0.63 1.03 ∝ 0° 8° 0° 8°

24 PIN SSOP PACKAGE DRAWING

E N 1 23 e b2 A1 A2 A D SEATING PLANE E11 L SIDE VIEW END VIEW TOP VIEW

  1. ORDERING INFORMATION 6. ENVIRONMENTAL, MANUFACTURI NG, & HANDLING INFORMATION * MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020. Model Temperature Package CS3301A-IS -40 to +85 °C 24-pin SSOP CS3301A-ISZ (lead free) Model Number Peak Reflow Temp MSL Rating* Max Floor Life CS3301A-IS 240 °C 2 365 Days CS3301A-ISZ (lead free) 260 °C 3 7 Days

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  1. REVISION HISTORY Revision Date Changes PP1 FEB 2007 Preliminary release. F1 MAR 2007 Updated to final for QPL (Quality Process Level). Contacting Cirrus Logic Support For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find one nearest you go to www.cirrus.com IMPORTANT NOTICE Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives con- sent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROP- ERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DE- VICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICA- TIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners.