CS3301 CIRRUS | Alldatasheet

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Copyright © Cirrus Logic, Inc. 2005 (All Rights Reserved) http://www.cirrus.com CS3301 Low-noise, Programmable Gain, Differential Amplifier Features & Desription zSignal Bandwidth: DC to 2 kHz zSelectable Gain: x1, x2, x4, x8, x16, x32, x64 zDifferential Inputs, Differential Outputs

  • Multiplexed inputs: INA, INB, 800Ω termination
  • Rough / fine charge outputs for CS5371/72
  • Max signal amplitude: 5 Vpp differential
  • Low input bias: 500 pA zOutstanding Noise Performance
  • 0.20 µVp-p between 0.1 Hz and 10 Hz
  • 8.5 from 0.1 Hz to 2 kHz zLow Total Harmonic Distortion
  • -118 dB THD typical (0.000126%)
  • -112 dB THD maximum (0.000251%) zLow Power Consumption
  • Normal/LPWR/PWDN: 5.5 mA, 3.5 mA, 10 µA zSingle or Dual Power Supply Configurations
  • VA+ = +5 V; VA- = 0 V; VD = +3.3 V to +5 V

Description

The CS3301 is a low-noise differential input, differential output amplifier with programmable gain, optimized for amplifying signals from low-impedance sensors such as geophones. The gain settings are binary weighted (x1, x2, x4, x8, x16, x32, x64) and are selected using simple pin settings. Two sets of external inputs, INA and INB, simplify system design as inputs from a sensor and test DAC. An internal 800 Ω termination can also be selected for noise tests. Amplifier noise performance is outstanding with a noise density of 8.5 over the 0.1 Hz to 2 kHz band- width. Distortion performance is also extremely good, typically -118 dB THD. Flat noise down to 0.1 Hz and low total harmonic distortion make this amplifier ideal for low-frequency, low-amplitude, differential signals requir- ing maximum dynamic range.

ORDERING INFORMATION

See page 15. nV/ Hz nV/ Hz INA+ INB+ MUX0 MUX1 INB- INA- VA+ VA- VD DGND CLK OUTR+ OUTF+ GAIN0 GAIN1 GAIN2 OUTF- OUTR- LPWR PWDN 400 Ω 400 Ω 500 Ω 500 Ω 500 Ω 500 Ω SEP ‘05 DS595F2 680 680 680 680

2.2.1. 2.3.2. 2.4.3. 2.6.1. 2.7.2. 2.8.3. 2.9.4.

CHARACTERISTICS AND SPECIFICATIONS Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical performance characteristics and specifications are derived from measurements taken at nom- inal supply voltages and TA = 25°C. DGND = 0 V, all voltages with respect to 0 V. SPECIFIED OPERATING CONDITIONS Notes: VA- must be the most negative voltage to avoid potential SCR latch-up conditions. VD must conform to Digital Supply Differential under Absolute Maximum Ratings. ABSOLUTE MAXIMUM RATINGS WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. Notes: Transient currents up to 100 mA will not cause SCR latch-up. Parameter Symbol Min Nom Max Unit Unipolar Power Supplies Positive Analog VA+ 4.75 5.0 5.25 V Negative Analog (Note 1) VA- -0.25 0.25 V Positive Digital (Note 2) VD 3.135 3.3 5.25 V Bipolar Power Supplies Positive Analog VA+ 2.375 2.5 2.625 V Negative Analog (Note 1) VA- -2.625 -2.5 -2.375 V Positive Digital (Note 2) VD 3.135 3.3 3.465 V Thermal Ambient Operating Temperature Industrial (-IS) TA -40 Parameter Symbol Min Max Parameter DC Power Supplies Positive Analog Negative Analog Digital VA+ VA- VD -0.3 -6.8 -0.3 6.8 0.3 6.8 V V V Analog Supply Differential [(VA+) - (VA-)] VADIFF 6.8 V Digital Supply Differential [(VD) - (VA-)] VDDIFF 6.8 V Input Current, Any Pin Except Supplies (Note 3) IIN +10 mA Input Current, Power Supplies (Note 3) IIN +50 mA Output Current (Note 3) IOUT +25 mA Power Dissipation PDN 500 mW Analog Input Voltages VINA (VA-)-0.5 (VA+)+0.5 V Digital Input Voltages VIND -0.5 (VD)+0.5 V Ambient Operating Temperature (Power Applied) TA -40 ºC Storage Temperature Range TSTG -65 150 ºC

Guaranteed by design and/or characterization. Tested with a full scale input signal of 31.25 Hz. Noise in the harmonic bins dominates THD and linearity measurements for x16, x32, x64 gains. Figure 1. CS3301 Noise Performance

ANALOG CHARACTERISTICS (CONT.) Common mode signals pass through the differential amplifier architecture. Relative gain accuracy tests the tracking of x1,x2,x4,x16,x32,x64 gain relative to x8 gain on a single CS3301 device. 10. Specification is for the parameter over the specified temperature range and is for the CS3301 device only. It does not include the effects of external components. 11. Offset voltage is tested with the amplifier inputs connected to the internal 800Ω termination. 12. The absolute offset after calibration specification applies to the effective offset voltage of the CS3301 output when used with the CS5371/72 modulator and CS5376A digital filter, and is measured from the digitally calibrated output codes of the CS5376A. 13. The CS3301 offset calibration is performed digitally with the CS5371/72 modulator and CS5376A digital filter and includes the full scale signal range. Calibration offsets of greater than + 5% of full scale will begin to subtract from system dynamic range. Parameter Symbol CS3301 Unit Min Typ Max Gain Gain, Differential GAIN x64 Gain, Common Mode (Note 7) GAINCM Gain Accuracy, Absolute (Note 8) GAINABS Gain Accuracy, Relative (Note 9) GAINREL +0.2 +0.5 Gain Drift (Note 4, 10) GAINTC ppm / ºC Offset Offset Voltage, Input Referred (Note 11) OFST +15 µV Offset After Calibration, Absolute (Note 12) OFSTCAL µV Offset Calibration Range (Note 13) OFSTRNG 100 % F.S. Offset Voltage Drift (Note 4, 10) OFSTTC 0.1 µV / ºC

ANALOG CHARACTERISTICS (CONT.) Notes: 14. No signals operating from external power supplies should be applied to pins of the device prior to its own supplies being established. Connecting any terminal to voltages greater than VA+ or less than VA- may cause destructive latch-up. 15. Ratio of common mode input amplitude vs. differential mode output amplitude for a perfectly matched common mode input signal. Characterized with a 50 Hz, 500 mVpeak common mode sine wave applied to the analog inputs. 16. Output impedance characteristics are primarily determined by the integrated anti-alias resistors. Values are approximate and can vary up to +/- 10% depending on process parameters. Parameter Symbol CS3301 Unit Min Typ Max Analog Input Characteristics Input Signal Frequencies BW DC 2000 Hz Input Voltage Range (Signal + Vcm) (Note 14) x2 - x64 VIN (VA-)+0.7 (VA-)+0.7 (VA+)-1.25 (VA+)-1.75 V Full Scale Input, Differential x16 x32 x64 VINFS 2.5 1.25 625 312.5 156.25 78.125 Vp-p Vp-p Vp-p mVp-p mVp-p mVp-p mVp-p Input Impedance, Differential ZINDIFF 1, 50 GΩ, pF Input Impedance, Common Mode ZINCM MΩ Input Bias Current IIN 500 1200 pA Crosstalk, Multiplexed Inputs (Note 4) XT -130 dB Common to Differential Mode Rejection (Note 4, 15) CDMR 100 dB Analog Output Characteristics Full Scale Output, Differential VOUT Vp-p Output Voltage Range (Signal + Vcm) VRNG (VA-)+0.5 (VA+)-0.5 V Output Impedance (Note 16) ZOUT 680 Ω Output Impedance Drift (Note 16) ZTC 0.24 Ω/°C Output Current IOUT 3.33 mA Load Capacitance CL 100 nF

Device is intended to be driven with CMOS logic levels. should be driven for synchronous system operation. Figure 2. Digital Input Rise and Fall Times Table 1. Digital Selections for Gain and Input Mux Control

POWER SUPPLY CHARACTERISTICS Notes: 19. All outputs unloaded. Analog inputs connected to the internal 800 Ω termination. Digital inputs forced to VD or DGND respectively. 20. Power supply rejection characterized with a 50 Hz, 400 mVp-p sine wave applied separately to each supply. Parameter Symbol CS3301 Unit Min Typ Max Power Supply Current, Normal Analog Power Supply Current (Note 19) IA 5.25 6.8 mA Digital Power Supply Current (Note 19) ID 0.2 0.25 mA Power Supply Current, Low Power (LPWR=1) Analog Power Supply Current (Note 19) IA 3.5 4.75 mA Digital Power Supply Current (Note 19) ID 0.2 0.25 mA Power Supply Current, Power Down (PWDN=1) Analog Power Supply Current (Note 19) IA µA Digital Power Supply Current (Note 19) ID µA Power Supply Rejection Power Supply Rejection Ratio (Note 4, 20) PSRR 120 dB

CS5372, one CS4373A, and one CS5376A. input is connected to the amplifier. Figure 3. Multi-Channel System Architecture

2.1.3 Differential Signals Analog signals into and out of the CS3301 are dif- ferential, consisting of two halves with equal but opposite magnitude varying about a common mode voltage. A full scale 5 Vpp differential signal centered on a -0.15 V common mode can have: SIG+ is +2.5 V relative to SIG- For the reverse case: SIG+ is -2.5 V relative to SIG- The total swing for SIG+ relative to SIG- is (+2.5 V) - (-2.5 V) = 5 Vpp. A similar calculation can be done for SIG- relative to SIG+. Note that a 5 Vpp differential signal centered on a -0.15 V common mode voltage never exceeds 1.1 V and never drops below -1.4 V on either half of the sig- nal. By definition, differential voltages are to be mea- sured with respect to the opposite half, not relative to ground. A multimeter differentially measuring between SIG+ and SIG- in the above example would properly read 1.767 Vrms, or 5 Vpp. 2.2 Digital Signals 2.2.1 Clock Input The clock signal is used by the chopper- stabilization circuitry of the amplifier analog in- puts. The CLK pin can be driven by an external clock source for synchronous operation, or CLK can be grounded to run from its own internally gen- erated clock signal. The CLK pin is connected to a clock detect circuit which will disable the internal clock and use an external clock if one is supplied. If the internal clock signal is to be used, the CLK pin should be connected to DGND. 2.2.2 Gain Selection The CS3301 supports gain ranges of x1, x2, x4, x8, x16, x32, and x64. They are selected using the GAIN0, GAIN1, and GAIN2 pins as shown in Table 1 on page 8. 2.2.3 Mux Selection The analog inputs to the amplifier are multiplexed, with external signals applied to the INA+, INA- or INB+, INB- pins. An internal termination is also available for noise tests. Input mux selection is made using the MUX0 and MUX1 pins as shown in Table 1 on page 8. Although a mux selection is provided to enable the INA and INB switches simultaneously, significant current should not be driven through them in this mode. The CS3301 mux switches will maintain good linearity only with minimal signal currents. 2.2.4 Low Power Selection For applications where power is critical, a low- power mode can be selected. This mode reduces amplifier power consumption at the expense of slightly degraded performance. Low power mode is selected using the LPWR pin, which is active high. 2.2.5 Power Down Selection A power-down mode is available to shut down the amplifier when not in use. When enabled, all inter- nal circuitry is disabled, the analog inputs and out- puts go high-impedance, and the device enters a micro-power state. Power down mode is selected using the PWDN pin, which is active high. 2.3 Power Supplies 2.3.1 Analog Power Supplies The analog power pins of the CS3301 are to be sup- plied with a total of 5 V between VA+ and VA-. This voltage is typically from a bipolar ±2.5 V power supply. When using bipolar power supplies, the analog signal common mode voltage should be biased to 0 V. The analog power supplies are rec-

ommended to be bypassed to system ground using 0.1 µF X7R type capacitors. The VA- supply is connected to the CMOS sub- strate and as such must remain the most negative applied voltage to prevent potential latch-up condi- tions. Care should be taken to ensure analog input voltages do not drop more than -0.3 V below the VA- supply. Care should also be taken to establish the VA- supply before analog signals are applied to the device. It is recommended to clamp the VA- supply to system ground using a reversed biased Schottky diode to prevent possible latch-up condi- tions related to mismatched supply rail initializa- tion. 2.3.2 Digital Power Supplies The digital power supply across the VD and DGND pins is flexible and can be set to interface with 3.3V or 5V logic. The digital power supply should be by- passed to system ground using a 0.01 µF X7R type capacitor.

Positive analog supply voltage. Negative analog supply voltage. Positive digital supply voltage. Channel A differential analog inputs. Selected via MUX pins. Channel B differential analog inputs. Selected via MUX pins. Rough charge differential analog outputs. Fine charge differential analog outputs. Gain range select. See Gain Selection table in Digital Characteristics section. Master clock input. Connect to DGND to use internal oscillator. Low power mode enable. Active high. Power down mode enable. Active high. Analog input select. See Input Selection table in Digital Characteristics section. Test mode select, factory use only. Connect to VA- during normal operation. Test mode select, factory use only. Connect to DGND during normal operation. Test mode output, factory use only. Connect to VA- during normal operation. Table 2. Pin Descriptions Figure 5. CS3301 Pin Assignments

ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION * MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020. Model Temperature Package CS3301-IS -40 to +85 °C 24-pin SSOP CS3301-ISZ (lead free) Model Number Peak Reflow Temp MSL Rating* Max Floor Life CS3301-IS 240 °C

365 Days

CS3301-ISZ (lead free) 260 °C

7 Days

Notes: 1. “D” and “E1” are reference datums and do not included mold flash or protrusions, but do include mold mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per side. Dimension “b” does not include dambar protrusion/intrusion. Allowable dambar protrusion shall be 0.13 mm total in excess of “b” dimension at maximum material condition. Dambar intrusion shall not reduce dimension “b” by more than 0.07 mm at least material condition. These dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips. INCHES MILLIMETERS NOTE DIM MIN MAX MIN MAX A 0.084 2.13 0.002 0.010 0.05 0.25 0.064 0.074 1.62 1.88 b 0.009 0.015 0.22 0.38 2,3 D 0.311 0.335 7.90 8.50 E 0.291 0.323 7.40 8.20 0.197 0.220 5.00 5.60 e 0.024 0.027 0.61 0.69 L 0.025 0.040 0.63 1.03

24 PIN SSOP PACKAGE DRAWING

E N 1 2 3 e A D SEATING PLANE E11 L SIDE VIEW END VIEW TOP VIEW