CS3011_07 CIRRUS | Alldatasheet
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http://www.cirrus.com Copyright © Cirrus Logic, Inc. 2007 (All Rights Reserved) CS3011 CS3012 Precision Low-voltage Amplifier; DC to 1 kHz Features & Description zLow Offset: 10 µV Max zLow Drift: 0.05 µV/°C Max zLow Noise –1 2 n V /√Hz @ 0.5 Hz – 0.1 to 10 Hz = 250 nVp-p – 1/f corner @ 0.08 Hz zOpen-loop Voltage Gain – 300 dB Typ –2 0 0 d B M i n zRail-to-rail Output Swing zSlew Rate: 2 V/µs
Applications
zThermocouple/Thermopile Amplifiers zLoad Cell and Bridge Transducer Amplifiers zPrecision Instrumentation zBattery-powered Systems
Description
The CS3011 single amplifier and the CS3012 dual am- plifier are designed for prec ision amplification of low- level signals and are ideally suited to applications that require very high closed-loop gains. These amplifiers achieve excellent offset st ability, super-high open-loop gain, and low noise over time and temperature. The de- vices also exhibit excellent CMRR and PSRR. The common mode input range includes the negative supply rail. The amplifiers operate with any total supply voltage Pin Configurations PDWN -In +In NC Output NC CS3011 8-lead SOIC Out A -In A +In A Out B -In B +In B A B CS3012 8-lead SOIC CS3011 100 64.9k 0.015µF Dexter Research Thermopile ST60 Thermopile Amplifier with a Gain of 650 V/V 100 0.001 0.010 0.1 1 10 Frequency (Hz) nV/√Hz Noise vs. Frequency (Measured) NOV ‘07 DS597F5
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- CHARACTERISTICS AND SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
V+ = +5 V, V- = 0V, VCM = 2.5 V (Note 1) Notes: 1. Symbol “ •” denotes specification applies over -40 to +85 ° C. 2. This parameter is guaranteed by design and labora tory characterization. Thermocouple effects prohibit accurate measurement of these parameters in automatic test systems. 3. 1000-hour life test data @ 125 °C indicates rando mly distributed variation approximately equal to measurement repeatability of 1 µV. 4. Measured within the specified common mode range limits. 5. Guaranteed within the output limits of (V+ -0.3 V) to (V- +0.3 V). Tested with proprietary production test method. 6. PWDN input has an internal pullup resistor to V+ of approximately 800 kΩ and is the major source of current consumption when PWDN is active (low). 7. The device has a controlled start-up behavior due to its complex open loop gain characteristics. Start- up time applies to when supply voltage is applied or when PDWN is released. Parameter CS3011/CS3012 UnitMin Typ Max Input Offset Voltage ( Note 2) • -- ± 1 0 µ V Average Input Offset Drift ( Note 2) • - ±0.01 ±0.05 µV/ºC Long Term Input Offset Voltage Stability (Note 3) Input Bias Current T A = 25º C ±50 ±1000 pA Input Offset Current T A = 25º C ±100 ±2000 pA Input Noise Voltage Density RS = 100 Ω, f0 = 1 Hz RS = 100 Ω, f0 = 1 kHz Input Noise Voltage 0.1 to 10 Hz - 250 nV p-p Input Noise Current Density f0 = 1 Hz - 100 Input Noise Current 0.1 to 10 Hz - 1.9 pA p-p Input Common Mode Voltage Range • -0.1 - (V+)-1.25 V Common Mode Rejection Ratio (dc) ( Note 4) • 115 120 - dB Power Supply Rejection Ratio • 120 136 - dB Large Signal Voltage Gain R L = 2 kΩ to V+/2 ( Note 5) • 200 300 - dB Output Voltage Swing R L = 2 kΩ to V+/2 RL = 100 kΩ to V+/2
- +4.7 - +4.99 V Slew Rate R L = 2 k, 100 pF 2 - V/µs Overload Recovery Time - 600 - µs Supply Current CS3011 CS3012 PWDN active (CS3011 Only) ( Note 6) -0 . 9 1.7 1.4 2.4 mA mA µA PWDN Threshold ( Note 6) • (V+) -1.0 Start-up Time ( Note 7) • -91 2 m s nV/ Hz nV/ Hz fA/ Hz
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- TYPICAL PERFORMANCE PLOTS
Figure 1. Noise vs. Frequency (Measured) Figure 3. 0.01 Hz to 10 Hz Noise Figure 5. Supply Current vs. Temperature, 3011 Figure 2. Noise vs. Frequency Figure 4. Offset Voltage Stability (DC to 3.2 Hz) Figure 6. Supply Current vs. Temperature, 3012
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10 K 100 K 1 M 10 M
Figure 10. Open Loop Gain and Phase vs Frequency (Expand- Figure 11. Input Bias Current vs Common Mode Voltage (CS3012)
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- CS3011/CS3012 OVERVIEW The CS3011/CS3012 amplifiers are designed for precision measurement of signals from DC to 1 kHz when operating from a supply voltage of ers are designed with a patented architecture that utilizes multiple amplifier stages to yield very high open loop gain at frequencies of 1 kHz and below. The amplifiers yield low noise and low offset drift while consuming relatively low supply current. An increase in noise floor above 1 kHz is the result of intermediate stages of the amplifier being operated at very low currents. The amplifiers are intended for amplifying small signals with large gains in ap- plications where the output of the amplifier can be band-limited to frequencies below 1 kHz.
3.1 Open Loop Gain and Phase Response
500 Hz and 30 kHz and transitions to –20 dB/de-
Figure 14. CS3011/CS3012 Open Loop Gain and Phase Response
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3.2 Open Loop Gain and Stability Compensation
3.2.1 Discussion
Figure 15. Non-Inverting Gain Configuration
Figure 16. Non-Inverting Gain Configuration with Compensation
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limit the amplifier’s rising noise above 1 kHz. Figure 17. Loop Gain Plot: Unity Gain and with Pole-Zero Compensation
2.4 MHz25 kHz 500 kHz
3.2.2 Gain Calculations Summary and
- |Av| = 1 configuration has 70° phase margin and 20 dB gain margin.
- |Av| = 50 configuration has phase margin be- tween 40° for C LOAD ≤ 100 pF and 60° for CLOAD = 0p F . Condition #2: |Av| ≤ 50 and R1 > 100 Ω Compensation capacitor C2 across R2 is required. Calculate C2 using the following formula:
- C 2 ≥ (R1 • Cin) / R2, where Cin = 50 pF Condition #3: |Av| > 50 Compensation capacitor C2 across R2 is required. Calculate and verify a value for C2 using the fol- lowing steps. Calculate the Compensation Capacitor Value: 1) Calculate a value for C2 using the following for- mula: C2 = 1 / [2π (R1| |R2) • P1], where P1 = 1 MHz To simplify the calculation, set the pole of the filter to P1 = 1 MHz. P1 must be set higher than the opamp’s internal 50 kHz crossover frequency. 2) Calculate a second value for C2 using the fol- lowing formula: C2 ≥ (R1 • Cin) / R2, where Cin = 50 pF 3) Use the larger of the two values calculated in steps 1 & 2. Verify the Opamp Compensation: Verify the opamp compensation using the open- loop gain and phase response Bode plot in
Figure 14. Plot the calculated closed loop gain
- Pole P1 > opamp internal 50 kHz crossover fre- quency -P 1 = 1/[ 2π (R1| |R2)• C2], where P1 = 1 MHz - To simplify the calculation, set the pole to P1 = 1 MHz.
- Z1 < opamp internal 50 kHz crossover frequency
- Gain margin above the open-loop gain transfer function is required. A gain margin of +20 dB above the open loop gain transfer function is optimal.
3.3 Powerdown (PDWN)
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3.4 Applications
for applications that require high gain and low drift. er. This circuit operates from +5 V. Figure 18. Thermopile Amplifier with a Gain of 650 V/V Figure 19. Load Cell Bridge Amplifier and A/D Converter
- ORDERING INFORMATION 5. ENVIRONMENTAL, MANUFACTURI NG, & HANDLING INFORMATION * MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020. Model Temperature Package CS3011-IS -40 to +85 °C 8-pin SOIC CS3011-ISZ (lead free) CS3012-IS CS3012-ISZ (lead free) Model Number Peak Reflow Temp MSL Rating* Max Floor Life CS3011-IS 240 °C 23 6 5 D a y s CS3011-ISZ (lead free) 260 °C CS3012-IS 240 °C CS3012-ISZ (lead free) 260 °C
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- PACKAGE DRAWING INCHES MILLIMETERS DIM MIN MAX MIN MAX A 0.053 0.069 1.35 1.75 A1 0.004 0.010 0.10 0.25 B 0.013 0.020 0.33 0.51 C 0.007 0.010 0.19 0.25 D 0.189 0.197 4.80 5.00 E 0.150 0.157 3.80 4.00 e 0.040 0.060 1.02 1.52 H 0.228 0.244 5.80 6.20 L 0.016 0.050 0.40 1.27 ∝ 0° 8° 0° 8° JEDEC # : MS-012 8L SOIC (150 MIL BODY) PACKAGE DRAWING D HE e b A c L ∝SEATING PLANE
- REVISION HISTORY Revision Date Changes F2 SEP 2004 Added lead-free dev ice ordering information. F3 AUG 2005 Added MSL specifications. Updated legal notice. Added leaded (Pb) devices. F4 AUG 2006 Updated Typical Performance Plots. Removed Powerdown feature. F5 NOV 2007 Added additional information regard ing open-loop and gain stability compensation.
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Contacting Cirrus Logic Support For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find the one nearest to you go to www.cirrus.com IMPORTANT NOTICE Cirrus Logic, Inc. and its subsidiaries (“Cirrus”) believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives con- sent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROP- ERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRIT- ICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIR- RUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUS- TOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING AT- TORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners.