CS2100-CP

CS2100-CP CIRRUS | Alldatasheet

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Technical content

Features

 Clock Multiplier / Jitter Reduction – Generates a Low Jitter 6 - 75 MHz Clock from a Jittery or Intermittent 50 Hz to 30 MHz Clock Source  Highly Accurate PLL Multiplication Factor – Maximum Error Less Than 1 PPM in High- Resolution Mode  I²C® / SPI™ Control Port  Configurable Auxiliary Output  Flexible Sourcing of Reference Clock – External Oscillator or Clock Source – Supports Inexpensive Local Crystal  Minimal Board Space Required – No External Analog Loop-filter Components General Description The CS2100-CP is an extremely versatile system clocking device that utilizes a programmable phase lock loop. The CS2100-CP is based on a hybrid ana- log-digital PLL architecture comprised of a unique combination of a Delta-Sigma Fractional-N Frequency Synthesizer and a Digital PLL. This architecture allows for generation of a low-jitter clock relative to an exter- nal noisy synchronization clock at frequencies as low as 50 Hz. The CS2100-CP supports both I²C and SPI for full software control. The CS2100-CP is available in a 10-pin MSOP pack- age in Commercial (-10°C to +70°C) grade. Customer development kits are also available for device evalua- tion. Please see “Ordering Information” on page 32 for complete details. I²C / SPI Auxiliary Output 6 to 75 MHz PLL Output 3.3 V I²C/SPI Software Control

8 MHz to 75 MHz

Digital PLL & Fractional N Logic Output to Input Clock Ratio N Timing Reference PLL Output Lock Indicator

50 Hz to 30 MHz

JUN '08 DS840PP1 CS2100-CP

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1. PIN DESCRIPTION Pin Name # Pin Description VD 1 Digital Power (Input) - Positive power supply for the digital and analog sections. GND 2 Ground (Input) - Ground reference. CLK_OUT 3 PLL Clock Output (Output) - PLL clock output. AUX_OUT 4 Auxiliary Output (Output) - This pin outputs a buffered version of one of the input or output clocks, or a status signal, depending on register configuration. CLK_IN 5 Frequency Reference Clock Input (Input) - Clock input for the Digital PLL frequency reference. XTO XTI/REF_CLK Crystal Connections (XTI/XTO) / Timing Reference Clock Input (REF_CLK) (Input/Output) - XTI/XTO are I/O pins for an external crystal which may be used to generate the low-jitter PLL input clock. REF_CLK is an input for an externally generated low-jitter reference clock. AD0/CS 8 Address Bit 0 (I²C) / Control Port Chip Select (SPI) (Input) - AD0 is a chip address pin in I²C Mode. CS is the chip select signal in SPI Mode. SCL/CCLK 9 Control Port Clock (Input) - SCL/CCLK is the serial clock for the serial control port in I²C and SPI mode. SDA/CDIN 10 Serial Control Data (Input/Output) - SDA is the data I/O line in I²C Mode. CDIN is the input data line for the control port interface in SPI Mode. 5 6 XTO CLK_OUT GND VD XTI/REF_CLK AD0/CS SCL/CCLK SDA/CDIN AUX_OUT CLK_IN

1. TYPICAL CONNEC TION DIAGRAM

Figure 1. Typical Connection Diagram

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1. CHARACTERISTICS AN D SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS GND = 0 V; all voltages with respect to ground. (Note 1) Notes: 1. Device functional operation is guaranteed within thes e limits. Functionality is not guaranteed or implied outside of these limits. Operation outside of these limits may adversely affect device reliability. ABSOLUTE MAXIMUM RATINGS GND = 0 V; all voltages with respect to ground. WARNING: Operation at or beyond these limits may result in permanent damage to the device. Notes: 1. The maximum over/under voltage is limited by the input current except on the power supply pin. DC ELECTRICAL CHARACTERISTICS Test Conditions (unless otherwise specified): VD = 3.1 V to 3.5 V; TA = -10°C to +70°C (Commercial Grade). Notes: 2. To calculate the additional curr ent consumption due to loading (per output pin), multiply clock output frequency by load capacitance and power supply voltage. For example, fCLK_OUT (49.152 MHz) * C L (15 pF) * VD (3.3 V) = 2.4 mA of additional current due to these loading conditions on CLK_OUT. Parameters Symbol Min Typ Max Units DC Power Supply VD 3.1 3.3 3.5 V Ambient Operating Temperature (Power Applied) Commercial Grade T AC -10 - +70 °C Parameters Symb ol Min Max Units DC Power Supply VD -0.3 6.0 V Input Current I IN -± 1 0 m A Digital Input Voltage (Note 1)V IN -0.3 VD + 0.4 V Ambient Operating Temperature (Power Applied) T A -55 125 °C Storage Temperature T stg -65 150 °C Parameters Symbol Min Typ Max Units Power Supply Current - Unloaded ( Note 2)I D -1 2 1 8 m A Power Dissipation - Unloaded ( Note 2)P D -4 0 6 0 m W Input Leakage Current I IN -- ± 1 0 µ A Input Capacitance I C -8-p F High-Level Input Voltage V IH 70% - - VD Low-Level Input Voltage V IL -- 3 0 % V D High-Level Output Voltage (IOH = -1.2 mA) V OH 80% - - VD Low-Level Output Voltage (IOH = 1.2 mA) V OL -- 2 0 % V D

AC ELECTRICAL CHARACTERISTICS Test Conditions (unless otherwise specified): VD = 3.1 V to 3.5 V; TA = -10°C to +70°C (Commercial Grade); CL =1 5p F . Notes: 3. 1 UI (unit interval) corresponds to t SYS_CLK or 1/fSYS_CLK. 4. t CS represents the time from the removal of CLK_IN by which CLK_IN must be re-applied to ensure that PLL_OUT continues while the PLL re-acquires lock. This timeout is based on the internal VCO frequen- cy, with the minimum timeout occurring at the maximum VCO frequency. Lower VCO frequencies will result in larger values of tCS. 5. Only valid in cloc k skipping mode; See “CLK_IN Skipping Mode” on page 13 for more information. 6. fCLK_OUT = 24.576 MHz; Sample size = 10,000 points; AuxOutSrc[1:0] = 11. 7. In accordance with AES-12id-2006 section 3.4.2. Measurements are Time Interval Error taken with 3rd order 100 Hz to 40 kHz bandpass filter. 8. In accordance with AES-12id-2006 section 3.4.1. Measurements are Time Interval Error taken with 3rd order 100 Hz Highpass filter. 9. 1 UI (unit interval) corresponds to t CLK_IN or 1/fCLK_IN. 10. The frequency accuracy of the PLL clock output is directly proportional to the frequency accuracy of the reference clock. Parameters Symbol Conditions Min Typ Max Units Crystal Frequency f XTAL Fundamental Mode 8 - 50 MHz Reference Clock Input Frequency f REF_CLK 8- 7 5 M H z Reference Clock Input Duty Cycle D REF_CLK 45 - 55 % Internal System Clock Frequency f SYS_CLK 8 18.75 MHz Clock Input Frequency (Auto R-Mod Disabled) f CLK_IN 50 Hz - 30 MHz Clock Input Frequency (Auto R-mod Enabled) f CLK_IN Auto R Modifier = 1 Auto R Modifier = 0.5 Auto R Modifier = 0.25 168 138 256 kHz kHz kHz Clock Input Pulse Width (Note 3)p w CLK_IN fCLK_IN < fSYS_CLK/96 fCLK_IN > fSYS_CLK/96 UI ns Clock Skipping Timeout t CS (Notes 4, 5)2 0 - - m s Clock Skipping Input Frequency f CLK_SKIP (Note 5) 50 Hz - 80 kHz PLL Clock Output Frequency f CLK_OUT 6- 7 5 M H z PLL Clock Output Duty Cycle t OD Measured at VD/2 48 50 52 % Clock Output Rise Time t OR 20% to 80% of VD - 1.7 3.0 ns Clock Output Fall Time t OF 80% to 20% of VD - 1.7 3.0 ns Period Jitter t JIT (Note 6) - 70 150 ps rms Base Band Jitter (100 Hz to 40 kHz) (Notes 6, 7) - 50 - ps rms Wide Band JItter (100 Hz Corner) (Notes 6, 8) - 175 - ps rms PLL Lock Time - CLK_IN (Note 9)t LC fCLK_IN < 200 kHz fCLK_IN > 200 kHz 100 200 UI ms PLL Lock Time - REF_CLK t LR fREF_CLK = 8 to 75 MHz - 1 2 ms Output Frequency Synthesis Resolution (Note 10)f err High Resolution High Multiplication ±0.5 ±112 ppm ppm

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Inputs: Logic 0 = GND; Logic 1 = VD; CL =2 0p F . Notes: 11. Data must be held for sufficient ti me to bridge the transition time, tf, of SCL. Figure 2. Control Port Timing - I²C Format

Inputs: Logic 0 = GND; Logic 1 = VD; CL =2 0p F . Notes: 12. tspi is only needed before first falling edge of CS after power is applied. tspi = 0 at all other times.

1. Data must be held for sufficient time to bridge the transition time of CCLK.

Figure 3. Control Port Timing - SPI Format (Write Only)

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4.1 Delta-Sigma Fractional- N Frequency Synthesizer

clock ratio is the value of N that is applied to the delta-sigma modulator (see Figure 4). clock should be stable and jitter-free. Figure 4. Delta-Sigma Fractional-N Frequency Synthesizer

4.2 Hybrid Analog-Digital Phase Locked Loop

to quickly achieve lock and then reduced for optimal jitter rejection.

Figure 5. Hybrid Analog-Digital PLL

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5.1 Timing Reference Clock Input

directly affects the performance of the PLL and hence the quality of the PLL output.

5.1.1 Internal Timing Reference Clock Divider

within the valid range as indicated in Figure 6. acteristics” on page 7 for more details.

5.1.2 Crystal Connections (XTI and XTO)

to the “AC Electrical Characteristics” on page 7 for the allowed crystal frequency range. Figure 6. Internal Timing Reference Clock Divider

50 MHz (XTI)

75 MHz (REF_CLK)

Figure 7. External Component Requirements for Crystal Circuit

5.1.3 External Reference Clock (REF_CLK)

5.2 Frequency Reference Clock Input, CLK_IN

PLL. The allowable frequency range for CLK_IN is found in the “AC Electrical Characteristics” on page 7.

5.2.1 CLK_IN Frequency Detector

internal SysClk and the CLK_IN input signal. device to determine the Auto R-Mod value. Table 1. PLL Input Clock Range Indicator ticularly useful when used in conjunction with the Auto R-Mod feature (see section 5.3.3 on page 17).

5.2.2 CLK_IN Skipping Mode

11 Reserved

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determined by the ClkOutUnl bit during this time. throughout the missing CLK_IN period including the time while the PLL re-acquires lock. Figure 8. CLK_IN removed for > 223 SysClk cycles

223 SysClk cycles 223 SysClk cycles

Figure 9. CLK_IN removed for < 223 SysClk cycles but > tCS Figure 10. CLK_IN removed for < tCS

5.2.3 Adjusting the Minimum Loop Bandwidth for CLK_IN

the lowest PLL bandwidth setting. See Figure 11. those synchronous to the PLL_OUT domain. the minimum value selected by the ClkIn_BW[2:0] bits. Figure 11. Low bandwidth and new clock domain Figure 12. High bandwidth with CLK_IN domain re-use

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5.3 Output to Input Freque ncy Ratio Configuration

5.3.1 User Defined Ratio (R UD)

The User Defined Ratio, R UD, is a 32-bit un-signed fixed-point number, stored in the Ratio register set, which determines the basis fo r the desired input to output clock ratio. The 32-bit R UD can be expressed in either a high resolution (12.20) or high mu ltiplication (20.12) format selectable by the LFRatioCfg bit, with 20.12 being the default. The RUD for high resolution (12.20) format is encoded with 12 MSBs representing the integer binary por- tion with the remaining 20 LSBs representing the frac tional binary portion. The maximum multiplication factor is approximately 4096 with a resolution of 0.954 PPM in this configuration. See “Calculating the User Defined Ratio” on page 30 for more information. The RUD for high multiplication (20.12) format is encod ed with 20 MSBs representing the integer binary portion with the remaining 12 LSBs representing the frac tional binary portion. In this configuration, the maximum multiplication factor is approximately 1,048,575 with a resolution of 244 PPM. It is recommend- ed that the 12.20 High-Reso lution format be utilized whenever the desired ratio is less than 4096 since the output frequency accuracy of the PLL is directly proportional to the accuracy of the timing reference clock and the resolution of the RUD. The status of internal dividers, such as the internal timing reference clock divider, are automatically taken into account. Therefore RUD is simply the desired ratio of the output to input clock frequencies. Referenced Control Register Location

5.3.2 Manual Ratio Modifier (R-Mod)

space remains unchanged). The available options for RMOD are summarized in Table 2 on page 17. Table 2. Ratio Modifier

5.3.3 Automatic Ratio Modifier (Auto R-Mod)

is enabled by the AutoRMod bit. Table 3. Automatic Ratio Modifier by the RModSel[2:0] bits and is used to calculate the Effective Ratio (see Section 5.3.4 on page 18).

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set to 10), the Frequency Range Indicator would then reflect the frequency range of the audio sample rate. An RUD of 512 would then generate the audio oversampling clocks as shown in Table 4.

5.3.4 Effective Ratio (R EFF)

to be altered to account for internal dividers. Table 4. Example Audio Oversampling Clock Generation from CLK_IN

5.3.5 Ratio Configuration Summary

value which controls the Frequency Synthesizer. Figure 13. Ratio Feature Summary

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5.4 PLL Clock Output

The PLL clock output pin (CLK_OUT) provides a buffered version of the output of the frequency synthesizer. The driver can be set to high-impedance with the ClkOutDis bit. CLK_OUT may then be unreliable during an unlock condition. Figure 14. PLL Clock Output Options

5.5 Auxiliary Output

then used to control the output driver ty pe and polarity of the LOCK signal (see section 8.6.2 on page 28). CLK_OUT pin. The driver for the pin can be set to high-impedance using the AuxOutDis bit. Figure 15. Auxiliary Output Selection

5.6 Clock Output Stability Considerations

5.6.1 Output Switching

CS2100 is designed such that re-configuration of the clock routing functions do not result in a partial clock period on any of the active outputs (CLK_OUT and/or AUX_OUT). In particular, enabling or disabling an output, changing the auxilia ry output source between REF_CLK and CLK_OU T, and the automatic dis- abling of the output(s) during unlock will not cause a runt or partial clock period. The following exceptions/limitations exist:

• Enabling/disabling AUX_OUT when AuxOutSrc = 11 (unlock indicator).
• Switching AuxOutSrc[1:0] to or from 01 (PLL cl ock input) and to or from 11 (unlock indicator) (Transitions between AuxOutSrc[1:0] = [00,10] will not produce a glitch).
• Changing the ClkOutUnl bit while the PLL is in operation. When any of these exceptions occur, a partial clock period on the output may result.

5.6.2 PLL Unlock Conditions

Certain changes to the clock inputs and registers can cause the PLL to lose lock which will affect the pres- ence the clock signal on CLK_OUT. The following outlines which conditions cause the PLL to go un- locked:

• Changes made to the registers which affect the Fr action-N value that is used by the Frequency Syn- thesizer. This includes all the bits shown in Figure 13 on page 19.
• Any discontinuities on the Ti ming Reference Clock, REF_CLK.
• Discontinuities on the Frequency Reference Clock, CLK_IN, except when the Clock Skipping feature is enabled and the requirements of Clock Skipping are satisfied (see “CLK_IN Skipping Mode” on page 13).
• Gradual changes in CLK_IN frequency great er than ±30% from the starting frequency.
• Step changes in CLK_IN frequency.

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the AD0/CS pin through a resistor to VD or GND, thereby permanently selecting the desired AD0 bit address state. In both modes the EnDevCfg1 and EnDevCfg2 bits must be set to 1 for normal operation. WARNING: All “Reserved” registers must maintain their default state to ensure proper functional operation.

6.1 SPI Control

device only supports write operations. the data which will be placed into the register designated by the MAP. ment after each byte is read or written, allowing block writes of successive registers.

6.2 I²C Control

In I²C Mode, SDA is a bidirectional dat a line. Data is clocked into and ou t of the device by the clock, SCL. Figure 16. Control Port Timing in SPI Mode

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6.3 Memory Address Pointer

The Memory Address Pointer (MAP) byte comes after the address byte and selects the register to be read or written. Refer to the pseudocode above for implementation details.

6.3.1 Map Auto Increment

The device has MAP auto increment capability enabled by the INCR bit (the MSB) of the MAP. If INCR is set to 0, MAP will stay constant for successive I²C writes or reads and SPI writes. If INCR is set to 1, MAP will auto increment after each byte is read or written, allowing block reads or writes of successive regis- ters. 7. REGISTER QU ICK REFERENCE This table shows the register and bit names with their associated default values. EnDevCfg1 and EnDevCfg2 bits must be set to 1 for normal operation. WARNING: All “Reserved” registers must maintain their default state to ensure proper functional operation. Adr Name 7 6 5 4 3 2 1 0 01h Device ID Device4 Device3 Device2 Devic e1 Device0 Revision2 Revision1 Revision0 p2 5 00000 x xx 02h Device Ctrl Unlock FsDet1 FsDet0 Reserved AutoRMod Reserved AuxOutDis ClkOutDis p2 5 xxx00000 03h Device Cfg 1 RModSel2 RModSel1 RModSel0 Reser ved Reserved AuxOutSrc1 AuxOutSrc0 EnDevCfg1 p2 6 00000 0 00 05h Global Cfg Reserved Reserved Reserved Res erved Freeze Reserved Reserved EnDevCfg2 p2 7 00000 0 00 06h 09h 32-Bit Ratio 16h Funct Cfg 1 ClkSkipEn AuxLockCfg Reserved Ref ClkDiv1 RefClkDiv0 Reserved Reserved Reserved p2 8 00000 0 00 17h Funct Cfg 2 Reserved Reserved Reserved ClkOutUnl LFRatioCfg Reserved Reserved Reserved p2 9 00000 0 00 1Eh Funct Cfg 3 Reserved ClkIn_BW2 ClkIn_BW1 Clk In_BW0 Reserved Reserved Reserved Reserved p2 9 00000 0 00

1. REGISTER DESCRIPTIONS In I²C Mode all registers are read/write unless otherwise stated. In SPI mode all registers are write only. All “Re- served” registers must maintain their default state to ensure proper functional operation. The default state of each bit after a power-up sequence or reset is indicated by the shaded row in the bit decode table and in the “Register Quick Reference” on page 24. Control port mode is entered when the device recognizes a valid chip address input on its I²C/SPI serial control pins and the EnDevCfg1 and EnDevCfg2 bits are set to 1. 8.1 Device I.D. and R evision (Address 01h)

8.1.1 Device Identification (Device[4:0]) - Read Only

I.D. code for the CS2100.

8.1.2 Device Revision (Revision[2:0]) - Read Only

CS2100 revision level.

8.2 Device Control (Address 02h)

8.2.1 Unlock Indicator (Unlock) - Read Only

Indicates the lock state of the PLL.

8.2.2 PLL Input Sample Rate Indi cator (FsDet[1:0]) - Read Only

Indicates the range of the frequency of CLK_IN relative to the frequency of SysClk. For audio applications, this can be used to distinguish single-, double-, and quad-speed modes. 76543210 Device4 Device3 Device2 Device1 Device0 Revision2 Revision1 Revision0 Device[4:0] Device 00000 CS2100. REVID[2:0] Revision Level 100 B2. 76543210 Unlock FsDet1 FsDet0 Reserved AutoRMod Reserved AuxOutDis ClkOutDis Unlock PLL Lock State 0 PLL is Locked. 1 PLL is Unlocked. FsDet[1:0] fSysClk / fCLK_IN 00 > 224. 01 96 to 224. 10 < 96. 11 Reserved. Application: “CLK_IN Frequency Detector” on page 13

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8.2.3 Auto R-Modifier Enable (AutoRMod)

Controls the automatic ratio modifier function.

8.2.4 Auxiliary Output Disable (AuxOutDis)

This bit controls the output driver for the AUX_OUT pin.

8.2.5 PLL Clock Output Disable (ClkOutDis)

This bit controls the output driver for the CLK_OUT pin.

8.3 Device Configuration 1 (Address 03h)

8.3.1 R-Mod Selection (RModSel[2:0])

Selects the R-Mod value, which is used as a factor in determining the PLL’s Fractional N. AutoRMod Automatic R-Mod State 0 Disabled. 1 Enabled. Application: “Automatic Ratio Modifier (Auto R-Mod)” on page 17 AuxOutDis Output Driver State 0 AUX_OUT output driver enabled. 1 AUX_OUT output driver set to high-impedance. Application: “Auxiliary Output” on page 20 ClkOutDis Output Driver State 0 CLK_OUT output driver enabled. 1 CLK_OUT output driver set to high-impedance. Application: “PLL Clock Output” on page 20 76543210 RModSel2 RModSel1 RModSel0 Reserved Rese rved AuxOutSrc1 AuxO utSrc0 EnDevCfg1 RModSel[2:0] R-Mod Selection 000 Left-shift R-value by 0 (x 1). 001 Left-shift R-value by 1 (x 2). 010 Left-shift R-value by 2 (x 4). 011 Left-shift R-value by 3 (x 8). 100 Right-shift R-value by 1 (÷ 2). 101 Right-shift R-value by 2 (÷ 4). 110 Right-shift R-value by 3 (÷ 8). 111 Right-shift R-value by 4 (÷ 16). Application: “Manual Ratio Modifier (R-Mod)” on page 17

8.3.2 Auxiliary Output Sour ce Selection (AuxOutSrc[1:0])

Selects the source of the AUX_OUT signal. Note: When set to 11, AuxLckCfg sets the polarity and driver type (“AUX PLL Lock Output Configura- tion (AuxLockCfg)” on page 28).

8.3.3 Enable Device Configurat ion Registers 1 (EnDevCfg1)

This bit, in conjunction with EnDevCfg2, enables control port mode. Both bits must be set to 1 during ini- tialization. Note: EnDevCfg2 must also be set to enable control port mode (“SPI / I²C Control Port” on page 22).

8.4 Global Configur ation (Address 05h)

8.4.1 Device Configuration Freeze (Freeze)

Setting this bit allows writes to the Device Control and Device Configuration registers (address 02h - 04h) but keeps them from taking effect until this bit is cleared.

8.4.2 Enable Device Configurat ion Registers 2 (EnDevCfg2)

This bit, in conjunction with EnDevCfg1, enables control port mode. Both bits must be set to 1 during ini- tialization. Note: EnDevCfg1 must also be set to enable control port mode (“SPI / I²C Control Port” on page 22). AuxOutSrc[1:0] Auxiliary Output Source 00 RefClk. 01 CLK_IN. 10 CLK_OUT. 11 PLL Lock Status Indicator. Application: “Auxiliary Output” on page 20 EnDevCfg1 Register State 0 Disabled. 1 Enabled. Application: “SPI / I²C Control Port” on page 22 76543210 Reserved Reserved Reserved Reserved Freeze Reserved Reserved EnDevCfg2 FREEZE Device Control and Configuration Registers 0 Register changes take effect immediately. 1 Modifications may be made to Device Control and Device Configuration registers (registers 02h-04h) without the changes taking effect until after the FREEZE bit is cleared. EnDevCfg2 Register State 0 Disabled. 1 Enabled. Application: “SPI / I²C Control Port” on page 22

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8.5 Ratio (Address 06h - 09h)

These registers contain the User Defined Ratio as shown in the “Register Quick Reference” section on page 24. These 4 registers form a single 32-bit ratio value as shown above. See “Output to Input Frequency Ratio Configuration” on page 16 and “Calculating the User Defined Ratio” on page 30 for more details.

8.6 Function Configuration 1 (Address 16h)

8.6.1 Clock Skip Enable (ClkSkipEn)

This bit enables clock skipping mode for the PLL and allows the PLL to mainta in lock even when the CLK_IN has missing pulses. Note: fCLK_IN must be < 80 kHz to use this feature.

8.6.2 AUX PLL Lock Output Configuration (AuxLockCfg)

When the AUX_OUT pin is configured as a lock indicator ( AuxOutSrc[1:0] = 11), this bit configures the AUX_OUT driver to either push-pull or open drain. It also determines the polarity of the lock signal. If AUX_OUT is configured as a clock output, the state of this bit is disregarded. Note: AUX_OUT is an unlock indicator, signalling an error condition when the PLL is unlocked. There- fore, the pin polarity is defined relative to the unlock condition.

8.6.3 Reference Clock Input Divider (RefClkDiv[1:0])

Selects the input divider for the timing reference clock. 76543210 76543210 ClkSkipEn AuxLockCfg Reserved RefClkDiv 1 RefClkDiv0 Reserved Reserved Reserved ClkSkipEn PLL Clock Skipping Mode 0 Disabled. 1 Enabled. Application: “CLK_IN Skipping Mode” on page 13 AuxLockCfg AUX_OUT Driver Configuration 0 Push-Pull, Active High (output ‘high’ for unlocked condition, ‘low’ for locked condition). 1 Open Drain, Active Low (output ‘low’ for unl ocked condition, high-Z for locked condition). Application: “Auxiliary Output” on page 20 RefClkDiv[1:0] Reference Clock Input Divider REF_CLK Frequency Range 00 ÷4 . 32 MHz to 75 MHz (50 MHz with XTI) 01 ÷ 2. 16 MHz to 37.5 MHz 10 ÷ 1. 8 MHz to 18.75 MHz 11 Reserved. Application: “Internal Timing Reference Clock Divider” on page 12

8.7 Function Configuration 2 (Address 17h)

8.7.1 Enable PLL Clock Out put on Unlock (ClkOutUnl)

Defines the state of the PLL output during the PLL unlock condition.

8.7.2 Low-Frequency Ratio Configuration (LFRatioCfg)

Determines how to interpret the 32-bit User Defined Ratio.

8.8 Function Configuration 3 (Address 1Eh)

8.8.1 Clock Input Bandwidth (ClkIn_BW[2:0])

Sets the minimum loop bandwidth when locked to CLK_IN. Note: In order to guarantee that a change in minimum bandwidth takes effect, these bits must be set prior to acquiring lock (removing and re-applying CLK_IN can provide the unlock condition necessary to initiate the setting change). In production systems these bits should be configured with the desired values prior to setting the EnDevCfg bits; this guarantees that the setting takes effect prior to acquiring lock. 76543210 Reserved Reserved Reserved ClkOutUnl LFRatioCfg Reserved Reserved Reserved ClkOutUnl Clock Output Enable Status 0 Clock outputs are driven ‘low’ when PLL is unlocked. 1 Clock outputs are always enabled (results in unpredictable output when PLL is unlocked). Application: “PLL Clock Output” on page 20 LFRatioCfg Ratio Bit Encoding Interpretation 0 20.12 - High Multiplier. 1 12.20 - High Accuracy. Application: “User Defined Ratio (RUD)” on page 16 76543210 Reserved ClkIn_BW2 ClkIn_BW1 ClkIn_BW0 Reserved Reserved Reserved Reserved ClkIn_BW[2:0] Minimum Loop Bandwidth 000 1 Hz 001 2 Hz 010 4 Hz 011 8 Hz 100 16 Hz 101 32 Hz 110 64 Hz 111 128 Hz Application: “Adjusting the Minimum Loop Bandwidth for CLK_IN” on page 15

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1. CALCULATING THE US ER DEFINED RATIO

systems without the aid of the evaluation kit. generate a binary or hex value which can be written to the Ratio register. write to the register. A few examples have been provided in Table 5. Table 5. Example 12.20 R-Values write to the register. A few examples have been provided in Table 6. Table 6. Example 20.12 R-Values

12.288 MHz/60 Hz=204,800 838860800 32 00 00 00

10.PACKAGE DIMENSIONS Notes: 1. Reference document: JEDEC MO-187 2. D does not include mold flash or prot rusions which is 0.15 mm max. per side. 3. E1 does not include inter-lead flash or protrusions which is 0.15 mm max per side. 4. Dimension b does not include a total allo wable dambar protrusion of 0.08 mm max. 5. Exceptions to JEDEC dimension. THERMAL CHARACTERISTICS INCHES MILLIMETERS NOTE DIM MIN NOM MAX MIN NOM MAX A1 0 -- 0.0059 0 -- 0.15 A2 0.0295 -- 0.0374 0.75 -- 0.95 b 0.0059 -- 0.0118 0.15 -- 0.30 4, 5 Parameter Symbol Min Typ Max Units Junction to Ambient Thermal Impedance JEDEC 2-Layer JEDEC 4-Layer θJA θJA 170 100 °C/W °C/W 10L MSOP (3 mm BODY) PACKAGE DRAWING (Note 1) E N 1 23 e b A1 A2 A D SEATING PLANE E11 L SIDE VIEW END VIEW TOP VIEW c

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11.ORDERING INFORMATION 12.REFERENCES 1. Audio Engineering Society AES-12id-2006: “AES Information Document for digital audio measurements - Jitter performance specifications,” May 2007. 2. Philips Semiconductor, “ The I²C-Bus Specification: Version 2,” Dec. 1998. http://www.semiconductors.philips.com 13.REVISION HISTORY Product Description Package Pb-Free Grade Temp Range Container Order# CS2100-CP Clocking Device 10L-MSOP Yes Commercial -10° to +70°C Rail CS2100-CP-CZZ CS2100-CP Clocking Device 10L-MSOP Yes -10° to +70°C Tape and Reel CS2100-CP-CZZR CDK2000 Evaluation Platform - Yes - - - CDK-2000-CLK Release Changes A1 Initial Release PP1 Updated “AC Electrical Characteristics” on page 7 Contacting Cirrus Logic Support For all product questions and inquiries, contact a Cirrus Logic Sales Representative. To find one nearest you, go to www.cirrus.com IMPORTANT NOTICE “Preliminary” product information describes products that are in production, but for which full characterization data is not yet available. Cirrus Logic, Inc. and its subsidiaries (“Cirrus”) believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives con- sent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROP- ERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRIT- ICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK AND CIR- RUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOM- ER’S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING AT- TORNEYS’ FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. I²C is a registered trademark of Philips Semiconductor. SPI is a trademark of Motorola, Inc.