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Preliminary Product Information This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice. Copyright Cirrus Logic, Inc. 2011 (All Rights Reserved) Cirrus Logic, Inc. http://www.cirrus.com CS1601 CS1601H Digital PFC Controller for Electronic Ballasts Features & Description Low PFC System Cost Best-in-class THD Digital EMI Noise Shaping Reduces Conducted EMI Adaptive Switching Frequency Control Minimizes Boost Inductor Size High Efficiency Due to Zero-current Switching Integrated Feedback Compensation Simplifies System Design Comprehensive Safety Features
- Undervoltage Lockout (UVLO)
- Output Overvoltage Protection
- Cycle-by-cycle Current Limiting
- Input Voltage Brownout Protection
- Open/Short Loop Protection for IAC & IFB Pins
- Thermal Shutdown Pin placement similar to traditional boundary mode (CRM) Controllers Applications & Description LED Power Supply/Driver Fluorescent Ballasts HID Ballasts Overview The CS1601 and CS1601H are digital power factor correction (PFC) controllers designed to deliver the lowest PFC system cost in electronic ballast appl ications. The controller operates in a variable frequency discontinuous conduction mode (VF- DCM) with zero-current switching (ZCS) optimized to deliver best-in-class THD and minimize the size and cost of magnetic components. The CS1601 operates at switching frequencies up to 70kHz while the CS1601H operates at frequencies extending to 100kHz. The VF-DCM control algorithm varies both duty cycle and frequency. This spreads the EMI frequency spectrum, thus reducing conducted EMI filtering requirements. In addition, the maximum switching frequency is reached at the peak of the AC input, which allows for use of a smaller, more cost-effective boost inductor. The feedback loop is closed through an integrated compensation network within the controller, eliminating the need for additional external com ponents. Protection features such as overvoltage, overcurrent, open and short-circuit protection, overtemperature, and brownout protect the system during abnormal transient conditions.
Ordering Information
See page 15. R2 R3 R4 R7 8 1 C1 C2 Regulated DC Output AC Mains BR 1 BR1 BR 1 BR1 CS1601 CS1601H GDZCD IFB GND CSIAC VDD LB VDD STBY Vrect Vlink JUN ’11 DS931PP6
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Figure 1. CS1601 Block Diagram overcurrent, and overtemperature). Figure 1 illustrates a high-level block diagram of the CS1601. implement the digital PFC control algorithm. ON time on a cycle-by-cycle basis. inductor to provide zero-current detection (ZCD) information. and switches when the auxiliary voltage is below zero. switching losses and reduces EMI noise. resumes once the fault clears.
5 ZCD+
6 GND
Figure 2. CS1601 Pin Assignments input into this pin. The current is measured with an ADC. STBY 2I N Standby — A voltage below 0.8V puts the IC into a non-operating, low-power state. The input has an internal 600k pull-up resistor to the VDD pin. into this pin. The current is measured with an ADC. computational logic to limit the maximum current through the power FET. auxiliary winding through an external resistor divider. peak current of 0.5A source and 1.0A sink. pin is clamped to a maximum voltage (Vz) by an internal zener function.
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- CHARACTERISTICS AND SPECIFICATIONS
3.1 Electrical Characteristics
Typical characteristics conditions: TA =2 5 ° C , VDD = 13V, GND = 0V All voltages are measured with respect to GND. Unless otherwise specified, all current are positive when flowing into the IC. Minimum/Maximum characteristics conditions: TJ = -40° to +125 °C, VDD = 10V to 15V, GND = 0V Parameter Condition Symbol Min Typ Max Unit VDD Supply Voltage Operating Range After Turn-on V DD 7.9 - 17.0 V Turn-on Threshold Voltage V DD Increasing V DD(on) 9.8 10.2 10.5 V Turn-off Threshold Voltage (UVLO) V DD Decreasing V DD(off) 7.9 8.1 8.3 V UVLO Hysteresis V Hys -2 . 1 - V Zener Voltage I DD =2 0 m A V Z 17.0 17.9 18.7 V VDD Supply Current Startup Supply Current V DD =V DD(on) IST -6 8 8 0 A Operating Supply Current3 CS1601 CS1601H CL = 1nF, fsw = 70kHz CL =1 n F , f s w=1 0 0 k H z IDD - 1.5 1.75 1.7 1.95 mA mA Standby Supply Current STBY < 0.8V I SB -8 0 1 1 2 A Reference Reference Current I ref - 129 - A PFC Gate Drive Output Source Resistance I GD = 100mA, VDD =1 3 V R OH -9 - Output Sink Resistance I GD = -200mA, VDD =1 3 V R OL -6 - Rise Time3 CL =1 n F ,VDD =1 3 V t r -3 2 4 5 n s Fall Time3 CL =1 n F ,VDD =1 3 V t f -1 5 2 5 n s Output Voltage Low State I GD = -200mA, VDD =1 3 V V o l - 0 . 9 1 . 3 V Output Voltage High State I GD = 100mA, VDD =1 3 V V o h 1 1 . 3 1 1 . 8 - V Zero-current Detection (ZCD) ZCD Threshold V ZCD(th) -5 0 - m V ZCD Blanking t ZCB - 200 - ns ZCD Sink/Source Current V ZCD =5 0 m V I ZCD -2 -1 2 mA Upper Voltage Clamp I ZCD =1 m A V CLP -V DD -V Overvoltage Protection (OVP) IFB Current at Startup Mode I IFB(startup) -1 1 6 - A IFB Current at Normal Mode I IFB(norm) - 129 - A OVP Threshold I ref =1 2 9AI OVP - 139 - A OVP Hysteresis I ref =1 2 9AI OVP(Hy) -2 - A
Notes: 1. Specifications guaranteed by design and are characterized and correlated using statistical process methods. 2. STBY is designed to be driven by an open collector. The input is internally pulled up with a 600 k resistor. 3. For test purposes, load capacitance (C L) is 1nF and is connected as shown in the following diagram. Overcurrent Protection (OCP) Current Sense Reference Clamp V CS(clamp) -1 . 0 - V Threshold on Current Sense V CS(th) -0 . 5 - V Leading Edge Blanking t LEB - 300 - ns Delay to Output t CS - 60 350 ns Brownout Protection (BP) Input Brownout Protection Threshold gate drive turns off I BP(lower) -3 1 . 6 - A Input Brownout Recovery Threshold gate drive turns on I BP(upper) -3 9 . 6 - A Thermal Protection1 Thermal Shutdown Threshold T SD 134 147 159 °C Thermal Shutdown Hysteresis T SD(Hy) -9 - ° C STBY Input 2 Logic Threshold Low - - 0.8 V Logic Threshold High V DD-0.8 - - V Parameter Condition Symbol Min Typ Max Unit GD OUT GD GND CS VDD Buffer TP CL 1nF +15V -15V VDD
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3.2 Absolute Maximum Ratings
Notes: 4. The CS1601 has an internal shunt regulator that limits the voltage on the VDD pin. VZ, the shunt regulation voltage, is defined in the VDD Supply Voltage section of the Characteristics and Specifications section on the previous page. 5. Long term operation at the maximum junction temperature will result in reduced product life. Derate internal power dissipation at the rate of 50mW/ °C for variation over temperature. WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. Pin Symbol Parameter Value Unit 8V DD IC Supply Voltage V Z V 1,3,4,5 - Analog Input Maximum Voltage -0.5 to V Z V 1,3,4,5 - Analog Input Maximum Current 50 mA 7V GD Gate Drive Output Voltage -0.3 to V Z V 7I GD Gate Drive Output Current -1.0 / +0.5 A -P D Total Power Dissipation @ TA =5 0° C 6 0 0 m W - JA Junction-to-Ambient Thermal Impedance 107 °C/W -T A Operating Ambient Temperature Range1 -40 to +125 °C -T J Junction Temperature Operating Range -40 to +125 °C -T Stg Storage Temperature Range -65 to +150 °C All Pins ESD Electrostatic Discharge Capability Human Body Model Machine Model Charged Device Model 2000 200 500 V
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Figure 8. Gate Resistance (ROH, ROL) vs. Temp Figure 9. OVP vs. Temp Figure 10. VDD Zener Voltage vs. Temp
legacy analog PFC controllers with minimal design effort.
5.1 PFC Operation
square-wave current envelop within every half-line cycle. Figure 11. Switching Frequency vs. Phase Angle power and the peak of the line voltage. Figure 12. CS1601 Max Switching Freq vs. Output Power changes with output power and the peak of the line voltage. Figure 13. CS1601H Max Switching Freq vs.Output Power O falls below 5%, the CS1601 changes to Burst Mode. The CS1601 is designed to function as a DCM controller. Figure 14. DCM and quasi-CRM Operation with CS1601
405 Bu rst M ode
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reaches 100% of nominal va lue, as shown in Figure 15. Figure 15. Startup and Normal Modes
5.3 Burst Mode
Figure 16. Burst Modes
5.4 Output Power and PFC Boost Inductor
estimated by the following equation. against boost inductor tolerances. Changing the value for the Vlink voltage is not recommended. voltage Vlink will drop below 460V and fall out of regulation. Figure 17. Relative Effects of Varying Boost Inductance
5.5 PFC Output Capacitor
0.25F/watt to 0.5 F/watt with a V link voltage of 460V.
5.6 Output IFB Sense & Input IAC Sense
compared to an internal reference current of (Iref) 129A. Figure 18. IFB Input Pin Model signal does not require an external compensation network. IC on pin IAC and is used by the PFC control algorithm. Figure 19. IAC Input Pin Model tolerance or better resistors for best Vlink voltage accuracy.
5.7 Valley Switching
Figure 20. ZCD Input Pin Model inductor to implement zero-voltage switching. Figure 21. Zero-voltage Switch
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range of boost-to-auxiliary inductor turns ratio, N. Table 1. Aux Inductor Turns Ratio vs. R3 and R4 by the RC circuit at the ZCD pin.
5.8 Brownout Protection
brownout, it re-enters normal operating mode. Vrect =R IACxIACand RIAC = R1+R2 in Figure 19 on page 11. brownout detection threshold, the CS1601 triggers a timer. equivalent of 7 rectified line cycles at 60Hz. protection, depending on the load. Figure 22. Brownout Sequence
5.9 Overvoltage Protection
5.10 Overcurrent Protection
5.11 Overpower Protection
power is a function of the boost inductor (Section 5.4). overload is still present, this cycle will repeat. for 2.5 seconds, then attempts to restart.
5.12 Open/Short Loop Protection
about 2 V/s, which is determined by the ADC sampling rate. time of open/short loop protection for RIFB is about 150s.
5.13 Internal Overtemperature Protection
sensor resets, allowing power to the logic.
5.14 Standby (STBY ) Function
Figure 23. STBY be tied to VDD (pulled high).
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5.15 Summary of Equations
Eq. # Equation Variables/Recommended Values Output Power (page 10) Po Rated output power of the system. Efficiency of the boost converter (estimated as 100% by the PFC algorithm). Vin(min) Minimum RMS line voltage is 90Vrms, measured after the rectifier and EMI filter. Vlink Nominal PFC output voltage must be 400V. fmax Maximum switching frequency is 70kHz. LB Boost inductor specified by rated power requirement. Margin factor to guarantee rated output power (Po) against boost inductor tolerances. RIAC Value of the IAC pin sense resistor(s). RIFB Value of the IFB pin sense resistor(s). Iref Value of the fixed, internal reference current. fc The cut-off frequency, f c, needs to be 10x the ringing frequency or fc = 10MHz. Cp Capacitance at the ZCD pin. Cp<10pF. VBP(th) Brownout threshold voltage. VBP(th) = 94.8V. Cout Value of the output capacitor in microfarads. fline(min) Minimum line frequency. VDD IC Supply Voltage. VOVP OVP threshold. IOVP Current into the IFB pin. Output Power w/ recommended values (page 10) Boost Inductor (page 10) Output IFB Sense Resistor (page 11) Input IAC Sense Resistor (page 11) Auxiliary Winding Cut-off Frequency (page 12) Maximum Response Time for Brownout: (page 12) Overvoltage Protection (page 12) Boost Inductor Peak Current Boost Inductor RMS Current Vlink Voltage Ripple RIFB Vlink VDD– Iref RIAC RIFB= TBrownout 8ms 8ms VOVP RIFB IOVP VDD+= ILB pk 4P O ILB rms PO Vlink rip PO
- PACKAGE DRAWING 7. ORDERING INFORMATION 8. ENVIRONMENTAL, MANUFACTURI NG, & HANDLING INFORMATION 8L SOIC (150 MIL BODY) PACKAGE DRAWING D HE e b A c L SEATING PLANE INCHES MILLIMETERS DIM MIN MAX MIN MAX A 0.053 0.069 1.35 1.75 A1 0.004 0.010 0.10 0.25 B 0.013 0.020 0.33 0.51 C 0.007 0.010 0.19 0.25 D 0.189 0.197 4.80 5.00 E 0.150 0.157 3.80 4.00 e 0.040 0.060 1.02 1.52 H 0.228 0.244 5.80 6.20 L 0.016 0.050 0.40 1.27 0° 8° 0° 8° JEDEC # MS-012 Part # Temperature Range Package Description CS1601-FSZ -40 °C to +125 °C 8-lead SOIC, Lead (Pb) Free Model Number Peak Reflow Temp MSL Rating a a. MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020. Max Floor Lifeb b. Stored at 30°C, 60% relative humidity. CS1601-FSZ 260 °C 2 365 Days
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- REVISION HISTORY Revision Date Changes PP1 NOV 2010 Preliminary Release - Updated block diagram and General Description sec- tion. PP2 DEC 2010 Updated Brownout Protection section, Overcurrent Protection section. Added Current Sense Reference Clamp specification. PP3 JAN 2011 Updated STBY pin and description. PP4 APR 2011 Updated Characteristics and Specifications section. PP5 May 2011 Updated Typical Electrical Performance section. PP6 JUN 2011 Updated Characteristics and Specifications section. Contacting Cirrus Logic Support For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find one nearest you go to http://www.cirrus.com IMPORTANT NOTICE "Preliminary" product information describes products that are in production, but for which full characterization data is not yet available. Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives con- sent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROP- ERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRIT- ICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUD- ING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners.