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Advance Product Information This document contains information for a product under development. Cirrus Logic reserves the right to modify this product without notice. Copyright Cirrus Logic, Inc. 2010 (All Rights Reserved) Cirrus Logic, Inc. http://www.cirrus.com CS1600 Low-cost PFC Controller for Electronic Ballasts Features & Description Lowest PFC System Cost for Electronic Ballasts Variable Frequency Discontinuous Conduction Mode Improved Efficiency Due to Variable Switching Frequency EMI Signature Reduction from Digital Noise Shaping Integrated Feedback Compensation Overvoltage Protection with Hysteresis Overpower Protection with Shutdown UVLO with Wide Hysteresis Thermal Shutdown with Hysteresis
Description
CS1600 is a high-performance Variable Frequency Discontinu- ous Conduction Mode (VF - DCM), active Power Factor Correction (PFC) controller, optimized to deliver the lowest PFC system cost for electronic ballast applications. A variable ON time / variable frequency algorithm is used to achieve near unity power factor. This algorithm spreads the EMI frequency spectrum, which reduces the conducted EMI filtering requirements. The feedback loop is closed through an integrated compensation network within the IC, eliminating the need for additional external components. Protection features such as overvoltage, overcurrent, overpower, open- and short-circuit pro- tection, overtemperature, and brownout help protect the device during abnormal transient conditions. Pin Assignments 8-lead SOIC NC STBY IAC FB NC VDD GD GND BR1 BR1 BR1 BR1 AC Mains +12V Q1R3 CS1600 IAC NC FB STBY VDD GNDNC GD R1a R1b R2b R2a C3a C3b R2cR1c RAC RFB Clink MAY ‘10 DS904A5
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Table 1. Pin Descriptions arise from leaving them unterminated. device. Leave this pin unterminated when not in use. Power Factor Correction (PFC) algorithm. GND 5– Ground — GND is a common reference for a ll the functional blocks in this device. current sink capacity of 1 A. for reliable operation of this device.
- CHARACTERISTICS AND SPECIFICATIONS
2.1 Absolute Maximum Ratings
Notes: 1. The CS1600 has an internal shunt regulator that c ontrols the nominal operating voltage on the VDD pin. 2. Long term operation at the maximum junction temperature will result in reduced product life. Derate internal power dissipation at the rate of 50 mW / ºC for variation over temperature.
2.2 Electrical Characteristics
Recommended operating conditions (unless otherwise specified): TA = TJ = -40º to +125º C, VDD = 10 to 15 V, GND = 0 V. Typical values are at TA = 25º C. Pin Symbol Parameter Value Unit
7 VDD IC Supply Voltage1 Vz V
2,3,4 V IN Input Voltage -0.5 to V DD V 3,4 I IN Input Current 50 mA 6V GD Gate Drive Voltage -0.3 to V DD V 6I GD Gate Drive Current -1.0 / +0.5 A 1,2,3,4,5,6,8 ESD Hum an Body Model 2000 V 1,2,3,4,5,6,8 ESD Ma chine Model 200 V 1,2,3,4,5,6,8 ESD Charg ed Device Model 500 V -P D Total Power Dissipation at 50° C2 600 mW -T J Junction Temperature Operating Range -40 to +125 ºC -T Stg Storage Temperature Range -65 to +150 ºC Parameter Condition Symbol Min Typ Max Unit VDD Supply Voltage VDD Turn-on Threshold Voltage VDD increasing V th(St) 8.4 8.8 9.3 V VDD Turn-off Threshold Voltage VDD decreasing V th(Stp) 7.1 7.4 7.9 V UVLO Hysteresis V Hys -1 . 3 - V Zener Voltage IDD =2 0m A V Z 17.0 17.9 18.5 V Supply Current Section Start-up Supply Current V DD < Vth(St) IST -6 8 8 0 μA Standby Supply Current STBY < 0.8V I SB -8 0 1 1 2 μA Operating Supply Current C L = 1nF, fsw = 70 kHz I DD -1 . 7 1 . 9 m A PFC Gate Drive Section Maximum Operating Frequency3,4 Normal mode, VDD =1 3V f SW(max) 62 66 70 kHz Minimum Operating Frequency3,4 Normal mode, VDD =1 3V f SW(min) 20 22 23 kHz Minimum Duty Cycle V DD = 13 V, STBY < 0.8 V t DC_min -- 0 % Maximum Duty Cycle3,4 VDD =1 3V D max 64 66 68 % Minimum On Time V DD =1 3V t on_min 0.45 0.5 0.55 μs Output Source Resistance I GD =1 0 0m A , VDD =1 3V R OH -9 - Ω Output Sink Resistance I GD =- 2 0 0m A , VDD =1 3V R OL -6 - Ω Rise Time C L =1n F , VDD =1 3V t r -3 2 4 5 n s
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2.3 Thermal Characteristics
- Specifications guaranteed by design & characterization. 4. Specifications measured as an instantaneo us quantity NOT as a time-averaged quantity. 5. STBY is designed to be driven by an open-collector device. The input is internally pulled up with a 600 kΩ resistor. 6. The package thermal impedance is calculated in accordance with JESD 51. 7. For an output voltage, V out, other than 460V, the threshold scales by a factor of Vout/460 Fall Time C L =1n F , VDD =1 3V t f -1 5 2 5 n s Output Voltage Low I GD =- 2 0 0m A , VDD =1 3V V OL -0 . 9 1 . 3 v Output Voltage High I GD =1 0 0m A , VDD =1 3V V OH 11.3 11.8 - v Feedback and Protection Reference Current I ref 127 130 133 μA Overvoltage Protection Threshold I OVP/Iref 105 107 110 % Overvoltage Protection Current Hysteresis I OVP(Hy) -4 - % Undervoltage Protection Threshold IUVP/Iref 83 85 87 % Undervoltage Protection Current Hysteresis I UVP(Hy) -1 0 - % Overpower Protection Threshold 3,4 % of full load as defined by Eq. 3 123 125 127 % Overpower Protection Recovery 3,4 35 49 60 % Input Brownout Protection Threshold7 Vout = 460V, GDRV turns off V BP(th) 82 86 90 Vrms Input Brownout Recovery Threshold7 Vout = 460V, GDRV turns on V BR 94 97 100 Vrms Thermal Protection Thermal Shutdown Threshold 3 TSD 130 143 155 ºC Thermal Shutdown Hysteresis T SD(Hy) -9 - º C STBY Input Logic Threshold 5 Low High VDD – 0.8 0.8 - V Symbol Parameter Value Unit RθJA Thermal Resistance (Junction to Ambient)6. TBD ºC / W RθJC Thermal Resistance (Junction to Case)6. TBD ºC / W Parameter Condition Symbol Min Typ Max Unit
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Figure 5. Supply Current (ISB, IST, IDD) vs. Temperature Figure 6. Gate Resistance (R OH, ROL) vs. Temperature
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4.1 PFC Implementation
illustrated in Figure 8 and Figure 9 below. Figure 8. Switching Frequency vs. Output Power Figure 9. Switching Frequency vs. Output Power maximum power delivery, as illustrated in Figure 10 below. Figure 10. DCM and quasi-CRM Operation with CS1600 changing the switching frequency to provide maximum power. these two modes is shown below in Figure 11. Figure 11. Start-up and Normal Modes
4.1.2 Burst Mode
estimated output power (P O) is < 5% of its nominal value. Figure 12. Burst Mode of Operation
4.2 Input Feedforward and Output
and the FB pins to monitor the voltages, scaled as currents. Figure 13. Output Feedback Figure 14. Input Feedforward
4.3 Protection Features
4.3.1 Overvoltage Protection
4.3.2 Overcurrent Protection
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4.3.3 Overpower Protection
of operation continues until the fault is removed.
4.3.4 Open/short circuit protection
FB pin is open or shorted to ground. undervoltage algorithm as described in Section 4.3.1. condition discussed in Section 4.3.5 below.
4.3.5 Brownout Protection
for the output voltage, drops to 49% of its nominal value. nominal value for a period of 56 ms. Figure 15. Brownout
4.3.6 Over-temperature Protection
4.4 Standby (STBY ) Function
about 1000 pF is recommended while this pin is being used. Figure 16. STBY
2 Vlink
- FLUORESCENT BALLAST APPLICATION EXAMPLE
follow may be used as guidelines for any other requirements using the CS1600.
5.1 Component Selection Guidelines
5.1.1 I AC and IFB Sense Resistors
breakdown and/or regulatory compliance is of concern.
5.1.2 PFC Input Filter Capacitor
108 W fluorescent ballast, an input filter capacitance of
Figure 17. CS1600 Basic Application Circuit
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5.1.3 PFC Boost Inductor
Equation 3 can be rewritten to calculate the PFC boost Inductor, LB, as follows: The RMS current rating for the inductor is estimated using an scaling factor used to account for variations in the input current shape across the AC line cycle, over and above the nominally calculated value. The nominal value before using the scaling factor is as follows: where β = inductor scaling factor The peak inductor current, I LB(pk), may be estimated using the following equation: Inductor tolerances should be considered when estimating the peak currents present in the application. The internal control algorithm of the controller dictates that the peak inductor current seen in the application could be as high as a pre-defined threshold of 0.001984 times the inverse of the inductor, which in this example amounts to 4.72 A. Care needs to be taken to ensure that the saturation current rating of the PFC boost inductor factors in this threshold used for the protection schemes.
5.1.4 PFC MOSFET
The peak voltage stress on the PFC MOSFET is a diode drop above the output voltage. Accoun ting for leakage spikes, for the 460 V output application, a 600 V FET is recommended. The FET should be able to handle the same peak current as that seen through the inductor. This would amount to 3.96 A. The scaling factor to determine the RMS current through the MOSFET for a 108 V input is about 1.15, and the minimum RMS current rating, I FET(rms), required for the FET is calculated as follows: where γ = FET scaling factor
5.1.5 PFC Diode
The PFC diode peak current is equal to the inductor peak current: The PFC diode average current is calculated as follows:
5.1.6 PFC Output Capacitor
The output capacitor needs to be designed to meet the voltage ripple and hold-up time requirements. In the case of a cost- sensitive ballast application, the hold-up requirement is not a key requirement. To address the output ripple requirements, the following equation may be used as a guide: where Cout = Output Capacitance value Po = Output Power fline(min) = Minimum Line Frequency Vlink = PFC Output Voltage ΔVlink = Peak-Peak Voltage Ripple on the PFC Output For a 40 V ripple and minimum line frequency of 45 Hz, the α Vlink Vin min() – Vlink Vin min() 2×– α Vlink Vin min() – Vlink Vin min() 2×– LB αη Vin min()() 2×× Vlink Vin min() 2×()– LB 0.937 0.95 108× 2× 460 108 2×–() 27 01 0 3× 115 460××× ILB rms() PO Vin min() 2×η × ILB rms() 1.07A= ILB rms() 115 108 2× 0.95× [Eq.7] ILB pk()
4 PO×
η V× in min() 2× ILB pk() 3.17 A= ILB pk() 4 115× 0.95 108× 2× [Eq.8] IFET rms() PO Vin min() 2×η × ILB rms() 0.91A= ILB rms() 115 108 2× 0.95× [Eq.9] IDp k() ILB pk()= IDp k() 3.17 A= [Eq.10] IDa v g() PO Vlink IDa v g() 0.25 A= IDa v g() 115 [Eq.11] [Eq.12]Cout PO
output capacitance needed is calculated as: The volt age rating on the capacitor needs to account for the operation of the device before it hits the overvoltage protection threshold. This is typically 105% of nominal value, which is 483 V. With the ripple voltage factored in, 22 μF of capacitance rated at 500 V would suffice for this application. Cout 115
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5.2 Bill of Materials (for Appli cation Example shown in Figure 17)
Designator Value Description/Part Number R1a 1.5 M Ω R1b 1.5 M Ω R1c 1.5 M Ω R2a 1.5 M Ω R2b 1.5 M Ω R2c 1.5 M Ω R3 24.9 Ω C1 0.47 μF C2 4.7 μF C3a 23.5μF2 4 7 μF, 250V caps in seriesC3b BR1 4A, 600V Bridge diode - GBU4J-BP D5 1 A, 600 1N4005 D6 3A, 600V MURS360 L1 360 μH (max) TBD (Premier Magnetics) Q1 9A, 600V FCP9N60N CS1600 - CS1600-FSZ
5.3 Summary of Equations
Eq. # Equation 1, 4 2, 5 3, 6 RFB Vlink VDD– Iref RAC RFB= PO αη Vin min()()× 2× Vlink Vin min() 2×()– ILB rms() PO Vin min() 2×η × ILB pk() 4P O× η V× in min() 2× IFET rms() PO Vin min() 2×η × IDp k() ILB pk()= IDa v g() PO Vlink Cout PO
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- PACKAGE DRAWING INCHES MILLIMETERS DIM MIN MAX MIN MAX A 0.053 0.069 1.35 1.75 A1 0.004 0.010 0.10 0.25 B 0.013 0.020 0.33 0.51 C 0.007 0.010 0.19 0.25 D 0.189 0.197 4.80 5.00 E 0.150 0.157 3.80 4.00 e 0.040 0.060 1.02 1.52 H 0.228 0.244 5.80 6.20 L 0.016 0.050 0.40 1.27 ∝ 0° 8° 0° 8° JEDEC # : MS-012 8L SOIC (150 MIL BODY) PACKAGE DRAWING D HE e b A c L ∝SEATING PLANE
- ORDERING INFORMATION 8. ENVIRONMENTAL, MANUFACTURI NG, & HANDLING INFORMATION Part # Temperature Range Package Description CS1600-FSZ -40 °C to +125 °C 8-lead SOIC, Lead (Pb) Free Model Number Peak Reflow Temp MSL Rating a a. MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020. Max Floor Lifeb b. Stored at 30 °C, 60% relative humidity. CS1600-FSZ 260 °C 2 365 Days
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- REVISION HISTORY Revision Date Changes A1 OCT 2009 Initial Advance Information release. A2 MAR 2010 Revised feature list, product description and parametric table to reflect the C0 version of silicon. A3 MAR 2010 Revised to reflect the update in switching frequency and variation of frequency over line. A4 APR 2010 Revised parametric table and equations to reflect the C1 version of silicon. A5 MAY 2010 Updated with additional test bench data for EP level. Contacting Cirrus Logic Support For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find one nearest you go to http://www.cirrus.com IMPORTANT NOTICE “Advance” product information describes products that are in development and subject to development changes. Cirrus Logic, Inc. and its subsidiaries (“Cirrus”) believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives con- sent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROP- ERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRIT- ICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIR- RUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOM- ER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING AT- TORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners.