CS1500

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Advance Product Information This document contains information for a product under development. Cirrus Logic reserves the right to modify this product without notice. Copyright  Cirrus Logic, Inc. 2010 (All Rights Reserved) Cirrus Logic, Inc. http://www.cirrus.com CS1500 Digital Power Factor Correction IC Features & Description  Digital EMI Noise Shaping  Excellent Efficiency Under All Load Conditions  Minimal External Devices Required  Optimized Digital Loop Compensation  Comprehensive Safety Features

• Undervoltage Lockout (UVLO)
• Output Overvoltage Protection
• Input Current Limiting
• Output Overpower Protection
• Input Brownout Protection
• Open/short Loop Protection for IAC & FB Pins
• Thermal Shutdown

Description

The CS1500 is a high-performance power factor correction (PFC) controller for universal AC input, which uses a proprie- tary digital algorithm for discontinuous conduction mode (DCM) with variable on-time and variable frequency control, ensuring unity power factor, shaping EMI noise, achieving ex- cellent efficiency especially at light load conditions. The CS1500 incorporates all the safety features necessary for robust and compact PFC stages. In addition, it has burst mode control to lower the light load/standby losses to a minimum. The digital controller optimizes the system stability and tran- sient performance, simplifies the PFC design, reduces the external component count and BOM costs. The simple design and minimum cost makes CS1500 the ideal choice for PFC up to 300 watts. Pin Assignments NC STBY IAC FB NC VDD GD GND 8-lead SOIC CS1500 LB Q16 R1a R1b R2a R2b FB GD NC STBY GND VDD IAC NC RAC RFB BR1 AC Mains Regulated DC Output MAY ‘10 DS849A5 May ?$shortyear> CONFIDENTIAL

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Table 1. Pin Descriptions pull-up resistor to the VDD pin and should be driven with an open-collector device. fed into this pin. The current is measured with an A/D converter. PFC is fed into this pin. The current is measured with an A/D converter. GND 5- Ground — Current return for both the input signal portion of the IC and the gate driver. clamped at VZ to avoid excessive gate voltages.

May ?$shortyear> CONFIDENTIAL 1. CHARACTERISTICS AND SPECIFICATIONS

1.1 Absolute Maximum Ratings

1.2 Electrical Characteristics

(TA = 25º C, VDD = 13V, -40º < TJ < +125º C, CL=1nF between pin GD and GND, all voltages are measured with respect to GND; all current are positive when flowing into the IC; unless otherwise specified) Pin Symbol Parameter Value Unit 7V DD IC Supply Voltage VZ V 1,2,3,4,8 - Analog Input Ma ximum Voltage -0.5 to V Z V 3,4 - Analog Input Maximum Current 50 mA 6V GD Gate Drive Output Voltage -0.3 to VZ V 6I GD Gate Drive Output Current -1.0 / +0.5 A -P D Total Power Dissipation @ TA=50° C 600 mW - θJA Junction-to-Ambient Thermal Impedance 107 ºC / W TA Operating Ambient Temperature Range1 -40 to +125 ºC -T J Junction Temperature Operating Range -40 to +125 ºC -T Stg Storage Temperature Range -65 to +150 ºC Parameter Condition Symbol Min Typ Max Unit VDD Supply Voltage Turn-on Threshold Voltage VDD Increasing V DD(on) 8.4 8.8 9.3 V Turn-off Threshold Voltage (UVLO) V DD Decreasing V DD(off) 7.1 7.4 7.9 V UVLO Hysteresis V Hys -1 . 3 - V Zener Voltage I DD =2 0m A VZ 17.0 17.9 18.5 V VDD Supply Current Start-up Supply Current V DD =V DD(on) IST -6 8 8 0 μA Standby Supply Current STBY <0 . 8V ISB -8 0 9 5 μA Operating Supply Current C L=1nF, fsw=70kHz I DD -1 . 7 1 . 9 m A PFC Gate Drive Maximum Operating Frequency6 VDD = 13V fSW(max) 62 66 70 kHz Minimum Operating Frequency6 VDD = 13V fSW(min) 20 22 23 kHz Maximum Duty Cycle6 VDD = 13V Dmax 64 66 68 % Output Source Resistance I GD =1 0 0 m A , VDD = 13V R OH -9 - Ω Output Sink Resistance I GD = -200mA,VDD = 13V R OL -6 - Ω Rising Time C L=1nF,VDD = 13V tr -3 2 4 5 n s Falling Time C L=1nF,VDD = 13V tf -1 5 2 5 n s Output Voltage Low State I GD = -200mA,VDD = 13V Vol - 0.9 1.3 V Output Voltage High State I GD =1 0 0 m A , VDD = 13V Voh 11.3 11.8 - V

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May ?$shortyear> CONFIDENTIAL NOTES: 1. Specifications guaranteed by design & characterization and correlation with statistical process controls. 2. Specification are based upon a PF C system configured for AC input of 90-265 VAC (Sine), 45/65 Hz, Vlink=4 0 0V , RAC =3x1 . 0 MΩ, RFB =3x1 . 0 MΩ, C3 = 180 μF, LB = 360 μH, 90 W. For other Vlink voltages, refer to Section 4 Application Example. 3. Detailed Calculation See Section 4 Application Example. 4. Overpower protection is scaled to rated power. 5. STBY is designed to be driven by an open collector. The input is internally pulled up with a 600 kΩ resistor. 6. Normal operation mode, see Section 3.2. Feedback & Protection2,3 Reference Current IREF -1 2 9 - μA Output Voltage at Startup Mode 25º C, 115 VAC V O(startup) -3 6 0 - V Output Voltage at Normal Mode V O(nom) -4 0 0 - V Overvoltage Protection Threshold 25º C, 115 VAC V OVP 415 418 421 V Overvoltage Protection Hysteresis V OVP(Hy) -4 - V Overpower Protection Threshold 2,4 25º C, 115 VAC - 125 - % Overpower Protection Recovery 2,4 25º C, 115 VAC - 100 - % Input Brownout Protection Threshold 25º C, GDRV turns off V BP(th) 62 65 68 Vrms Input Brownout Recovery Threshold 25º C, GDRV turns on V BR 77 80 83 Vrms Thermal Protection 1 Thermal Shutdown Threshold TSD -1 4 3 - º C Thermal Shutdown Hysteresis T SD(Hy) -9 - º C STBY Input 5 Logic Threshold Low - - 0.8 V Logic Threshold High Vdd-0.8 - - V Parameter Condition Symbol Min Typ Max Unit

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Figure 5. Supply Current (ISB, IST, IDD) vs. Temp Figure 6. Min/Max Operating Frequency vs. Temp Figure 7. Gate Resistance (ROH, ROL) vs. Temp Figure 8. OVP vs. Temp

Figure 9. CS1500 Block Diagram maximize the efficiency and reduce the conductive EMI.

• DCM with Variable On-Time, Variable Switching Fre- quency The CS1500 PFC switching frequency varies with the V rect on a cycle-by-cycle basis, and its digital algorithm calculates the on-time accordingly for unity power factor. Unlike traditional Critical Conduction Mode (CRM) PFC controller, CS1500 operates at its low switching frequen- cy near the zero-crossing point of the AC input voltage, even no switching at all, and it operates at its high switch- ing frequency at the peak of its AC input voltage (this is the opposite of the switching frequency profile for a CRM PFC controller), thus CS1500 reduces switching losses especially under light-load conditions, spreads conducted EMI energy peaks over a wide frequency band and in- creases overall system efficiency.
• Optimized Digital Loop Compensation The proprietary digital control engine optimizes the feed- back error signal using an adaptive control algorithm, im- proves system stability an d transient response. No external feedback error signal compensation components are required.
• Overcurrent Mitigation The CS1500s digital controller algorithm limits the ON time of the Power MOSFET by the following equation: Where T on is the max time that the power MOSFET is turned on and V rect is the rectified line voltage. In the event of a sudden line surge or sporadic, high dv/dt line voltages, this equation may not limit the ON time appro- priately. For this type of line disturbance, additional pro- tection mechanisms such as fusible resistors, fast-blow fuses, or other current-limiting devices are recommend- ed.
• Over Voltage Protection Under steady-state conditio ns, the voltage loop keeps PFC output voltage close to its nominal value. Under light load startup or feedback loop open conditions, the output voltage may pass the overvoltage protection threshold. The digital control engine initiates a fast response loop to shut down gate driving signal to reduce the energy deliv- ered to the output for PFC capacitor protection. When the link voltage drop below V OVP-VOVP(Hy), PFC resumes normal operation. IAC FB STBY CS1500 GD6 VDD 7 NC 8 GND5 Processor Logic NC 1 PWM Driver Oscillator ProtectionADC Ton 0.001126 Vrect

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3.1 PFC Operating Frequency

varied in about a 2-to-1 ratio from the peak to the trough. Figure 10. Switching Frequency vs. Phase Angle Figure 11. Switching Frequency vs. Output Power below 5%) will be discussed in a later section. Figure 12. DCM and quasi-CRM Operation with CS1500 Figure 13. Start-up and Normal Modes

3.3 Burst Mode

405 Burst Mode

Figure 14. Burst Modes

3.4 Output Power and PFC Boost Inductor

3.5 PFC Output Capacitor

is within the range of 0.5 μF / watt to 2.0 μF/w a t t .

3.6 Output Feedback & Regulation

Figure 15. Feedback Input Pin Model compared to an internal reference current, Iref. signal does not require an external compensation network.

3.7 IAC Signal

Figure 16. IAC Input Pin Model IC on pin IAC and is used by the PFC control algorithm.

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3.8 Brownout Protection

fault trigger, a digital filter is added for line voltage detection. upper threshold for at least 56 ms. Figure 17. Brownout Sequence

3.9 Overpower Protection

condition and initiates the overpower protection. Figure 18. Overpower Protection Mechanism Figure 19. Maximal Output Power vs. Line Voltage

3.10 Overvoltage Protection

3.11 Open/short Loop Protection

of about 2V / μs, which is determined by ADC sampling rate.

is about 150 μs in the CS1500. mechanism described in Section 3.8.

3.12 Overcurrent Limiting

margin to prevent saturation in normal operation mode.

3.13 Standby (STBY) Function

Figure 20. STBY be tied to VDD (pulled high).

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calculate the values for the components shown in the diagram.

4.1 PFC for Power Supply Application

Figure 21. CS1500 Basic Application Circuit

May ?$shortyear> CONFIDENTIAL

4.1.2 PFC Input Filter Capacitor

To achieve unity power factor, a DCM PFC circuit needs an input filtering circuit to bypass the high-frequency current so that the input current consists of the low-frequency portion only. There are two main factors on PFC input filter capacitor selection: its voltage ripple and phase lag, which both will worsen power factor. The filtering capacitance is proportional to Po and it is suggested as follows: Use 0.47 μF for tolerance. If a PI filter used for suppression of conducted EMI is located on the DC side of the input rectifier, the Vrect sense point has to be moved to the second capacitor.

4.1.3 PFC Boost Inductor

The value of the inductor in normal mode can be calculated by the following equation, with α = 0.9 as a derating factor to ensure the inductor is sized to guarantee DCM operation and provide a slightly higher power than required by the load: Choose a 360 μH inductor. η is the efficiency. The inductor should be designed so that its saturation current meets the following requirement, where 0.001126 is a pre- defined threshold for the current protection algorithm: where L is the inductance in Henrys.

4.1.4 PFC MOSFET

In normal mode, the PFC MOSFET peak current is equal to the peak current in the PFC boost inductor:

4.1.5 PFC Diode

The PFC diode peak current in normal mode is the equal to the inductor peak current: The PFC Diode average current is calculated as follows:

4.1.6 PFC Output Capacitor

The value of the output capacitor is determined by several requirements. It must meet the voltage ripple and hold-up time requirements and the RMS current in the capacitor should not exceed its RMS current rating. The following equation defines the size of the output capacitor to meet the output voltage ripple requirements: fline(min) is the minimum line frequency the design is required to support, Vlink is the output voltage from the PFC, ΔVlink(rip), is the output voltage ripple requirement in volts peak-to-peak. The equation will provide the va lue of the output capacitor needed to meet the ripple requirement. For 10 V of ripple and minimum line frequency of 45 Hz, the equation becomes: A second requirement that the output capacitor may be required to meet is hold-up ti me. The value of the capacitor C1 3.3nF C1 3.3 120× ≥ C1 390nF≥ 0.39μF= [Eq.10] LB αη Vin min()()× 2× Vlink Vin min() 2×()– LB 374μH= [Eq.11] ILB pk() 4P o× αη× V× in min() 2× ILB pk() 3.3A= ILB pk() 49 0× 0.9 0.95× 90× 2× [Eq.12] Isat 0.001126 IFET pk() ILB pk()= IFET pk() 3.3A= [Eq.14] IDp k() ILB pk()= IDp k() 3.3A= [Eq.15] IDa v g() Po Vlink IDa v g() 0.225A= IDa v g() [Eq.16] [Eq.17]Cout rip() PO Cout rip()

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May ?$shortyear> CONFIDENTIAL needed to meet the hold-up time required is defined by the following equation: tHOLD is the magnitude of the hold-up time in seconds. For 10 ms of hold-up time and V link(min) of 300 V, the equation becomes: Choose a 100 μF capacitor.

4.1.7 Overvoltage Protection

Overvoltage protection is activated when Vlink exceeds 105% of the nominal value: While in overvoltage protecti on mode, gate drive output is disabled. GD output is re-enabled when V link falls below its nominal value. Cout hold() 2P O× t× hold Vlink ΔVout rip() Vlink min()() 2– Cout hold() 29 0× 0.010× 400 10  2 300() 2– Vovp Vlink 1.05×= Vovp 400 1.05×= Vovp 420V= [Eq.19]

May ?$shortyear> CONFIDENTIAL

4.1.8 Summary of Component Values

Designator Value Description R1a 1.5 MΩ SFR25 axial film res - 0.4W-1% R1b 1.5 MΩ SFR25 axial film res - 0.4W-1% R2a 1.5 MΩ SFR25 axial film res - 0.4W-1% R2b 1.5 MΩ SFR25 axial film res - 0.4W-1% R3 4.7 Ω SFR25 axial film res - 0.4W-1% C1 0.47 μF ECQ2W474KH C2 0.47 μF 50V Ceramic cap - X7R C3 100 μF, 450V LLS2W101MELA BR1 4A, 600V GBU4J-BP D1 1 A, 600 V 1N4005 D2 1 A, 600 V STTH1R06 LB 360 μH Premier Magnetics Q1 12 A, 500 V STP12NM50FP CS1500 PFC Controller CS1500

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Figure 22. Efficiency vs. Load, Typical Figure 23. Distortion vs. Load, Typical

Figure 24. Power Factor vs. Load, Typical

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Figure 25. Load Transient — 20% to 80% (60 mA to 240 mA), 0.8 A/ μsec Slew, 90 VAC Figure 26. Load Transient — 20% to 80% (60 mA to 240 mA), 0.8 A/ μsec Slew, 260 VAC

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May ?$shortyear> CONFIDENTIAL 6. DEFINITIONS Variable Definition η The efficiency factor. α A margin factor to guarantee rated power against tolerances and transients. fline(min) The minimum AC line frequency. IAC The current generated by Vrect that flows into the IAC pin. IFB The current generated by Vlink that flows into the FB pin. IFET(pk) The PFC MOSFET peak current, which is equal to the peak current in the PFC boost inductor. Irms The magnitude of the RMS current. Isat The boost inductor LB saturation current. Ist The sum of the current into the IAC and FB pins. IST The startup current of the chip. LB The PFC boost inductor. Po The nominal output power from the CS1500 PFC circuit. Po(max) The maximum value of the output power from the CS1500 PFC circuit. RAC The sense resistor used to measure current into the IAC pin. RFB The sense resistor used to measure current into the FB pin. Vin(min) The minimum specified line voltage for proper operation (volts RMS). Vlink The magnitude of the output voltage from the PFC. Vlink(min) The magnitude of the output voltage from the PFC. ΔVlink(rip) ΔVlink(rip), is the output voltage ripple requirement in volts peak-to-peak Vrect The instantaneous value of the rectified line voltage (volts).

May ?$shortyear> CONFIDENTIAL 7. PACKAGE DRAWING 8. ORDERING INFORMATION 9. ENVIRONMENTAL, MANUFACTURI NG, & HANDLING INFORMATION INCHES MILLIMETERS DIM MIN MAX MIN MAX A 0.053 0.069 1.35 1.75 A1 0.004 0.010 0.10 0.25 B 0.013 0.020 0.33 0.51 C 0.007 0.010 0.19 0.25 D 0.189 0.197 4.80 5.00 E 0.150 0.157 3.80 4.00 e 0.040 0.060 1.02 1.52 H 0.228 0.244 5.80 6.20 L 0.016 0.050 0.40 1.27 ∝ 0° 8° 0° 8° JEDEC # MS-012 8L SOIC (150 MIL BODY) PACKAGE DRAWING D HE e b A c L ∝SEATING PLANE Part # Temperature Range Package Description CS1500-FSZ -40 °C to +125 °C 8-lead SOIC, Lead (Pb) Free Model Number Peak Reflow Temp MSL Ratinga a. MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020. Max Floor Lifeb b. Stored at 30 °C, 60% relative humidity. CS1500-FSZ 260 °C 2 365 Days

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May ?$shortyear> CONFIDENTIAL 10.REVISION HISTORY Revision Date Changes A1 APR 2009 Initial Advance Information release. A2 JUN 2009 No substantive changes. Document number incremented to avoid confusion among previous, pre-released versions. A3 DEC 2009 Revised feature list & product de scription. Revised electrical charac- teristics to include brownout & open-loop protection. Modified defini- tion table. Modified data sheet format. A4 MAR 2010 Updated to corr espond to C1 silicon. A5 MAY 2010 Updated performance data. Contacting Cirrus Logic Support For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find one nearest you go to http://www.cirrus.com IMPORTANT NOTICE "Advance" product information describes products that are in development and subject to development changes. Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives con- sent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROP- ERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRIT- ICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUD- ING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners.