CMX018 CMLMICRO | Alldatasheet
Document overview
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- PDF pages: 15
Technical content
Datasheet sections
- 1.0 Features and Applications
- 1.1 Brief Description
- 1.2 Internal Block Diagram
- 1.3 Signal List
- 1.4 External Components
- 1.5 General Description
- 1.5.1 Low Noise Amplifier
- 1.5.2 First Down-Converter
- 1.5.3 Second Down-Converter
- 1.5.4 Limiting Amplifier and RSSI
- 1.5.5 FM/FSK Demodulator
- 1.5.6 Zero-Power Mode
- 1.6 Application Notes
- 1.6.1 General
- 1.6.2 Example Schematic and Layout
- 1.7 Performance Specification
- 1.7.1 Electrical Performance
- 1.7.2 Packaging
- 1.7.3 Handling Precautions
D/018/3 April 1999 Advance Information Features Applications
- • Double Conversion Super-Heterodyne Receiver and FM/FSK Demodulator
- • High Performance Analogue/Digital Radio Links (860-965MHz)
- • LNA with Switched Gain •• General ISM 915MHz Band
- • High Performance UHF Down-Converter Stage with Integrated VCO
- • Analogue/Digital Cordless Phones
- • 2.7V Operation •• Spread Spectrum Receivers
- • Zero-Power Mode (<10µµA) •• Analogue FM Receivers
- • 28-Pin SSOP Package •• Handheld Data Terminals
- • Temperature Compensated RSSI •• So-Ho Wireless Data Links DETOUT LIMOUT QUADIN 430ΩΩ 2nd DOWN CONVERTER 1st DOWN CONVERTER IF LIMITING AMPLIFIER LNA MIX2IN MIX2OUT LIMIN LIMDEC1 LIMDEC2 LNAIN 50ΩΩ 50ΩΩ 50ΩΩ 100ΩΩ 100ΩΩ 430ΩΩ VCO FM/FSK DISCRIMINATOR LNADEC LNAOUT MIX1IN MIX1OUT ENABLEGAINSEL TANK OSCOUT RSSIOSCBA OSCEM BANDGAP & BIAS CONTROL BUFFERED OSCILLATOR OUTPUT
1.1 Brief Description
The CMX018 is a single chip UHF FM/FSK double-conversion super-heterodyne receiver. It combines a dual gain mode Low Noise Amplifier (LNA), two down-converters (including integrated oscillators), limiting amplifier, RSSI, FM/FSK demodulator and zero-power mode control. The CMX018 can be used in conjunction with the CMX017 , an integrated FM/FSK modulator and transmitter, to implement a complete UHF radio link.
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1.2 Internal Block Diagram
Figure 1 Internal Block Diagram SECOND DOWN CONVERTER FIRST DOWN CONVERTER 430 Ω ENABLE GAINSEL LNADEC Vcc1 GND TANK Vcc2 OSCOUT OSCBA OSCEM DETOUT Vcc3 LIMOUT QUADIN LNAIN GND LNAOUT GND MIX1IN MIX1OUT GND MIX2IN MIX2OUT GND LIMIN LIMDEC1 LIMDEC2 RSSI LNA FM/FSK DEMODULATOR BUFFERED VCO OUTPUT IF LIMITING AMPLIFIER
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1.3 Signal List
Pin No. Name Type
1 LNAIN I/P LNA RF Input
2 GND GROUND LNA Ground connection
3 LNAOUT O/P LNA RF Output
4 GND GROUND LNA Ground connection
5 MIX1IN I/P RF Input to the First Down-Converter
6 MIX1OUT O/P IF Output from the First Down-Converter
7 GND GROUND First Down-Converter Ground connection
8 MIX2IN I/P RF Input to the Second Down-Converter
9 MIX2OUT O/P IF Output from the Second Down-Converter
10 GND GROUND Second Down-Converter, Limiting Amplifier,
RSSI and Demodulator stages - Ground connection
11 LIMIN I/P Input to the Limiting Amplifier
12 LIMDEC1 I/P External Decoupling capacitors - one required at
13 LIMDEC2 I/P each Limiting Amplifier Input
14 RSSI O/P Receive Signal Strength Indicator output
15 QUADIN I/P Quadrature input to the FM Demodulator
16 LIMOUT O/P Output from the Limiting Amplifier
17 Vcc3 POWER Power supply to the Second Down-Converter,
Limiting Amplifier, RSSI and Demodulator stages - nominally 3.0V
18 DETOUT O/P Output of the FM/FSK Quadrature Demodulator
19 OSCEM Emitter connection to the Second Down-
Converter Local Oscillator transistor
20 OSCBA Base connection to the Second Down-Converter
Local Oscillator transistor
21 OSCOUT O/P Buffered Local Oscillator (Open-Collector) output
from the First Down-Converter
22 VCC 2 POWER First Down-Converter Power supply
- nominally 3.0V
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23 TANK I/P First Down-Converter Local Oscillator (VCO)
24 GND GROUND First Down-Converter VCO Ground connection
25 VCC 1 POWER LNA Power supply - nominally 3.0V
26 LNADEC External LNA bias decoupling capacitor
27 GAINSEL CMOS I/P LNA Gain control logic input. A logic '0' provides a typical power gain of 16dB and a logic '1' provides an attenuation of 6dB 28 ENABLE CMOS I/P Zero-Power logic control. A logic '0' powers down the device. Notes: I/P = Input O/P = Output
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1.4 External Components
Component Values: X1 60.175MHz 50ppm Xtal L1 22nH L2 680nH L3 680nH L4 1µH D1 Varactor Varactor Diode, type SMV1233-011 ~ Resonator Co-Axial Resonator, type RG402, length = 11mm, shorted end. C1 100nF C2 100nF C3 100nF C4 200pF C5 8 - 50pF Trimmer C6 5pF C7 220pF C8 6.8pF C9 15pF C10 33pF C11 4.7pF C12 6.2pF C13 10nF C14 100pF C15 100pF R1 10kΩ R2 10kΩ R3 2.0kΩ NOTE: Components are surface mount, type SMD0603, unless otherwise marked. Figure 2 Example of CMX018 with External Components
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1.5 General Description
The CMX018 is a single chip UHF FM/FSK double-conversion super-heterodyne receiver. It combines a dual gain mode Low Noise Amplifier (LNA), two down-converters (including integrated oscillators), limiting amplifier, RSSI, FM/FSK demodulator and zero-power mode control. The receiver frequency is selected using an external PLL or synthesizer which is driven by the buffered RF oscillator signal from the first down-converter. The CMX018 can be used in conjunction with the CMX017 , an integrated FM/FSK modulator and transmitter, to implement a complete UHF radio link.
1.5.1 Low Noise Amplifier
The LNA includes a switched gain function which is used to increase the dynamic range of the receiver. The gain is selected using the GAINSEL logic input at pin 2. With a logic '0' at the GAINSEL input a high gain is selected and the amplifier achieves the lowest noise figure. This mode is used where maximum sensitivity is required for low level input signals. Where high level signals are present at the receiver input, which cause difficulties due to inter-modulation, the gain of the LNA can be reduced by typically 22dB from about +16dB to about -6dB. The attenuation is selected by applying a logic '1' at the GAINSEL input, this minimises the amount of non-linear distortion in the overall receiver at the expense of small signal sensitivity. The input and output impedances of the LNA are typically Ω .
1.5.2 First Down-Converter
The first down-converter includes a double balanced mixer with a low noise pre-amplifier and on-chip oscillator components. The oscillator is configured as a “high-sided” voltage controlled local oscillator, using an external varicap diode and tank resonator circuit, such that the first IF is typically centred at 70MHz. A buffered oscillator signal (OSCOUT at pin 21) is provided to drive the frequency synthesizer which controls the frequency tuning. The input impedance is typically 50Ω and the output impedance is typically 100Ω .
1.5.3 Second Down-Converter
The second down-converter also includes a double balanced mixer with a low noise pre-amplifier and on-chip oscillator components. The oscillator is configured as a “low-sided” local oscillator, using an external crystal at typically 60MHz, such that the second IF is centred at 10.7MHz. The input impedance is typically 100Ω and the output impedance is typically 430Ω .
1.5.4 Limiting Amplifier and RSSI
The limiting amplifier provides the IF amplification and limiting prior to the FM/FSK demodulator. An RSSI circuit is included which has temperature compensation. An RF signal level of -100dBm at the LNA input will produce an RSSI voltage of typically TBD mV. The RSSI voltage will increase with increasing RF input level at a rate of 20mV/dB up to a typical voltage of TBD V at a -60dBm RF input. In practice the absolute RSSI voltage will depend upon the insertion losses associated with each of the IF filters. The input impedance is typically 430 Ω .
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1.5.5 FM/FSK Demodulator
A quadrature detector is employed together with an external discriminator and phase shift network to demodulate the FM or FSK signal.
1.5.6 Zero-Power Mode
The device is powered down by applying a logic '0' level at the ENABLE input (pin 28). In this mode the device current is reduced to less than 10µA. This feature is useful when the device is operating within a transceiver where the receiver needs to be enabled and disabled. A delay should be allowed for the receiver to settle after power-up. This is likely to be less than the xtal oscillator stabilisation time, which may be altered by adjusting the value of R2, shown in Figure 2.
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1.6 Application Notes
1.6.1 General
1.6.2 Example Schematic and Layout
The following schematic (Figure 3) and printed circuit layout (Figure 4) show a typical application interface for the CMX018. To aid legibility, the schematic and layout are available electronically from the CML website http://www.cmlmicro.co.uk or on floppy disk by request from CML's office. Alternative components and component values are shown on the schematic. These should be selected according to the intended application. The schematic uses the following ICs: U2 Motorola MC34072D-SO8 U3 IC Works WB1315X U4 Analog DevicesAD8532-SO8
1999 Consumer Microcircuits Limited 10 D/018/3 C71 6p8 6 5 4 8 - + - + MC34072D R4 100k R5 100k C6 2.2uF C7 47nF R2 10k C5 1nF C11 1nF C32 2.2uF 100k 1 3 5 7 2 4 6 8 9 11 13 15 17 19 10 12 14 16 18 20 TFMCON20M C80 10nF C79 100nF C78 100uF C87 100nF 100pF C470 100R100 100pF C10 C58 100pF C59 100pF C48 100pF R47 2k2 R10 N/C C77 100nF 100pF C13 L11 820nH C81 1uF C460100pF C61 100pF C25 1nF C22100pF 100pF C67 CLOCK DATA LE GND FIN2B FIN2 GND DO2 VP2 VCC2 VCC1 VP1 DO1 GND FIN1 FIN1B GND OSC_IN GND FO_LD WB1315X C70 1nF C50 180pF L5 8nH 12.5nH 12.5nHC54 180pF C41 33pF C26100pF C39 360pF C40 33pF C52 330pF C30 N/C C42360pF C31 N/C C49 120+33pF C53 120+33pF C51 120+47pF C21 N/C C2 33pF C4 N/C C93 N/C 100pF C38100pF C34 100pF SAW FILTER SAW FILTER RFIN C27 N/CN/C OUT IN 1GND 4GND 6GND 3GND F5CH-915M-L2 FLT2 OUT IN GND GND GND GND F5CH-915M-L2 FLT1 C17 100pF C35 100pF N/C C28 C12 N/C C60 1nF L10 1uH R22 C65 100nF C66 100nF 1nF C55 1 IN GND OUT KMFC545S 1 IN OUT 2 GND KMFC545P LNAIN GND1 LNAOUT GND2 MIX1IN MIX1OUT MIX2IN MIX2OUT GND3 GND4 LIMIN LIMDEC1 LIMDEC2 RSSI QUADIN LIMOUT VCC3 DETOUT OSCEM OSCBA OSCOUT VCC2 TANK OSCGND VCC1 LNADEC GAINSEL ENABLE CMX018D6 C69 10nF C45 1nF 33pF C56 680nH C57 15pF C64 6.8pF C62 220pF C72 200pF C73 CV1206 C685pF C37 1nF L16 100nF C320 1uF 10k-N/C R14 100nF L15 100nF L14 100pF C24 C36 1nF C33 1nF 2IN1 GND RXRESNR C43 4.7pF C44 10pF XT1 HC49U-S C63 N/C R15 10k 0R-N/C R16 100R C47 10nF C46 3pF SYNT_STB 100kR19 100kR20 100kR21 C23 100pF SYNT_DATASYNT_CLK C29 100pF 15uH C14 100nF C15 100pF C16 2.2uF 680nHL8 10k-N/C R18 47K - N/C L3 22nH N/C L9 3V C18 470nF C20 100pF C1 1nF L1 15uH R6 0R R3 N/C C19 100nF R8 1k AD8532-SO8 ( -NC)C3 2.2uF Figure 3 Application Schematic
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1.7 Performance Specification
1.7.1 Electrical Performance
Exceeding these maximum ratings can result in damage to the device. Pins Min. Max. Units Supply Voltage (VCC ) 17, 22, 25 -0.3 7.0 V Input Voltage 27, 28 -0.3 VCC + 0.3 V LNA Input Power 1 0 dBm Total Allowable Power Dissipation at Tamb = 25°C 1100 mW ... Derating 11 mW/°C Storage Temperature -55 +125 °C Operating Limits Correct operation of the device outside these limits is not implied. Notes Min. Max. Units Supply Voltage (VCC ) 2.7 3.3 V RF Input Range 860 965 MHz Operating Temperature -10 +60 °C
1999 Consumer Microcircuits Limited 13 D/018/3 Operating Characteristics For the following conditions unless otherwise specified: VCC = 2.7V to 3.3V, Tamb = - 10°C to +60°C, RF = 915MHz, 50Ω source and load impedance. Pin Min. Typ. Max. Units DC Parameters Icc (ENABLE = VCC and GAINSEL = 0V) 17, 22, 25 50 mA Icc (ENABLE = VCC and GAINSEL = VCC ) 17, 22, 25 42 mA Icc (ENABLE = 0V) 17, 22, 25 10 µA A C Parameters LNA (RF = 915MHz) Power Gain (GAINSEL = 0V) 1, 3 16 dB Power Gain (GAINSEL = VCC ) 1, 3 -6.0 dB Noise Figure 1, 3 3.0 dB Input 1dB Gain Compression Point (GAINSEL = 0V) 1 -20 dBm Input 1dB Gain Compression Point (GAINSEL = VCC ) 1 16 dBm Input Third Order Intercept Point (GAINSEL = 0V) 1 -10 dBm Input Third Order Intercept Point (GAINSEL = VCC ) 1 25 dBm Reverse Isolation (GAINSEL = 0V) 3, 1 -35 dB Reverse Isolation (GAINSEL = VCC ) 3, 1 -6.0 dB Input Impedance 1 50 Ω Output Impedance 3 50 Ω Input Return Loss (50Ω source) 1 10 dB Output Return Loss (50Ω load) 3 15 dB VCO to LNA Leakage 1 -45 dBm First Down Converter (RF = 915MHz and IF = 70MHz) Conversion Gain 5, 6 15 dB Noise Figure 5, 6 15 dB Input 1dB Gain Compression Point 5 -12 dBm Input Third Order Intercept Point 5 -4.0 dBm Input Impedance 5 50 Ω Output Impedance 6 100 Ω Input Return Loss (50Ω source) 5 TBD dB Output Return Loss (50Ω load) 6 TBD dB Buffered oscillator output power 21 -10 dBm RF to IF Leakage 5, 6 TBD dB LO to IF Leakage 6 TBD dBm LO to RF Leakage 5 TBD dBm
1999 Consumer Microcircuits Limited 14 D/018/3 Operating Characteristics (Continued) Pin Min. Typ. Max. Units Second Down Converter (RF = 70MHz and IF = 10.7MHz) Conversion Gain 8, 9 24 dB Noise Figure 8, 9 13 dB Output 1dB Gain Compression Point 9 -11 dBm Output Third Order Intercept Point 9 -2 dBm Input Impedance 8 100 Ω Output Impedance 9 430 Ω Limiting Amplifier and RSSI (IF = 10.7MHz) Bandwidth 11, 16 40 MHz Internal Voltage Gain 11 74 dBV Input Impedance 11 430 Ω RSSI Dynamic Range 14 TBD dB RSSI Slope 14 TBD V/dB RSSI Voltage Range 1 14 TBD V Demodulator (IF = 10.7MHz) Output Swing 2 18 TBD mVp-p Output Impedance 18 1 kΩ Notes: 1. Input power = TBD to TBD 2. 125kHz Deviation, 1kΩ Load
UHF FM/FSK Receiver CMX018 CML does not assume any responsibility for the use of any circuitry described. No IPR or circuit patent licences are implied. CML reserves the right at any time without notice to change the said circuitry and this product specification. CML has a policy of testing every product shipped using calibrated test equipment to ensure compliance with this product specification. Specific testing of all circuit parameters is not necessarily performed.
1 WHEATON ROAD
Telephone: +44 1376 513833 Telefax: +44 1376 518247 e-mail: sales@cmlmicro.co.uk http://www.cmlmicro.co.uk
1.7.2 Packaging
Figure 5 28-Pin Plastic SSOP Mechanical Outline: Order as part no. CMX018D6
1.7.3 Handling Precautions
This device is a high performance RF integrated circuit and is ESD sensitive. Adequate precautions must be taken during handling and assembly of this device.