Sensor

CMV20000

ams AG

20 Megapixel global shutter CMOS image sensor

Manufacturer: ams AG

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20 Megapixel global shutter CMOS image sensor

Reference:CMV20000-datasheet-v2.3 CMV20000 Datasheet Page 2 of 47 © 2015 CMOSIS bvba Change record Issue Date Modification 1 24/11/211 Origination 1.1 24/5/2013 Changed VDD20 from 2.0V to 2.1V 2 19/06/2013 Removed draft, confidential and preliminary annotations 2.1 12/08/2013 Updated: - FOT, Read out time and exposure time calculations - SPI read out delay (left - right) - VDD20 maximum range to 2.2V - CLK_IN is optional Added: - Angular response - Digital test signals - Detailed frame timing - LVDS output skew 2.2 05/06/2014 Updated: - QE and spectral response for mono devices - Remarks in register overview Added: - QE and spectral response for color devices 2.3 20/05/2015 Updated: - Supply currents - SPI_OUT not tri-state - PGA gain made relative - Reg103 = 72  64 Added: - ADC_gain vs. actual gain - Excessive light precaution - Test Pattern image example Disclaimer CMOSIS reserves the right to change the product, specification and other information contained in this document without notice. Although CMOSIS does its best efforts to provide correct information, this is not warranted. Since the CMV20000 started its design life as a custom imager for traffic applications, the sale of the imager for these applications is excluded.

1 INTRODUCTION

1.1 OVERVIEW

The CMV20000 is a global shutter CMOS image sensor with 5120 by 3840 pixels. The image array consists of 6.4μm x 6.4μm pipelined global shutter pixels which allow ex posure during read out, while performing CDS operation. The image sensor has sixteen 12 -bit digital LVDS outputs (serial). The image sensor also integrates a programmable gain amplifier and offset regulation. Each channel runs at 480 Mbps maximum which res ults in 30 fps frame rate at full resolution. Higher frame rates can be achieved in row -windowing mode or row-subsampling mode. These modes are all programmable using the SPI interface. All internal exposure and read out timings are generated by a programmable on-board sequencer. External triggering and exposure programming is also possible. Extended optical dynamic range can be achieved by multiple integrated high dynamic range modes. Features

1.2 FEATURES

 5120 * 3840 active pixels on a 6.4um pitch  frame rate 30 Frames/sec  row windowing capability  Window, X-Y mirroring function  Master clock 40MHz  16 LVDS-outputs @ 480MHz, or 8 LVDS-outputs at 15FPS  LVDS control line with frame and line information  LVDS DDR output clock to sample data on the receiving end  12 bit ADC output  High Dynamic Range mode supported  Power dissipation control  On chip temperature sensor  On chip timing generation  SPI-control  Ceramic PGA package (143 pins)

1.3 SPECIFICATIONS

 Full well charge: 15Ke-  Sensitivity: 8.3 V/lux.s (with microlenses @ 550nm)  Dark noise: 8e- RMS  Conversion factor: 110µV/e (@ pixel); 0.25DN/e  Dynamic range: 66 dB  Extended dynamic range: Piecewise linear response  Parasitic light sensitivity: 1/50 000  Dark current: 125 e/s (@ 25C die temp)  Fixed pattern noise: <0.2% of full swing, standard deviation on full image  Power consumption: 1100mW

2 SENSOR ARCHITECTURE

Figure 1 shows the image sensor architecture. The internal sequencer generates the necessary signals for image acquisition. The image is stored in the pixel (global shutter) and they are read out sequ entially, row-by-row into the which ADC conversion is performed. The digital signals are then read out over multiple LVDS channels. Each LVDS channel reads out 640 adjacent columns of the array. The AFE and LVDs drivers are doubled on opposite sides of the sensor, resultin g in 2 rows being read out at the same when all 16 outputs are used. In the Y -direction, rows of interest are selected through a row-decoder which allows a flexible windowing. Control registers are foreseen for the programming of the sensor. These register parameters are uploaded via a four -wire SPI interface. A temperature sensor which can be read out over the SPI interface is also included. Active pixel area 5120 rows 3840 columns Analog front end (AFE) (gain, offset, ADCs) LVDS block (drivers, multiplexers) 8 outputs sequencer SPI Temp sensor Input clock SPI signals External driving signals Pixel (0,0) Pixel (4095,3071) Analog front end (AFE) (gain, offset, ADCs) LVDS block (drivers, multiplexers) 8 outputs FIGURE 1: BASIC SENSOR ARCHITE CTURE The most important blocks are described more in detail in the following sections.

2.1 PIXEL ARRAY

The CMV20000 sensor has 5120*3840 active pixels with a 6.4um pitch surrounded by two dummy rows and columns. These dummy pixels at the side will ensure that the optical performance, of the active pixels at the edges, is the same as the one in the active array. These dummy pixels cannot be read out and will be set permanent into reset. The pixels are designed to achieve maximum sensitivity with low noise and low PLS specifications. Micro lenses are placed on top of the pixels for improved fill factor and quantum efficiency.

2.2 ANALOG FRONT -END ELECTRONICS (AFE)

The analog front end consists of 2 major parts, a column amplifier block and a column ADC block. The column amplifier prepares the pix el signal for the column ADC and applies analog gain if desired (programmable using the SPI interface). The column ADC converts the analog pixel value to a 12 bit value and can apply a gain. A digital offset can also be applied to the output of the column ADC’s. All gain and offset settings can be programmed using the SPI interface.

2.3 LVDS BLOCK

The LVDS block converts the digital data coming from the column ADC into standard serial LVDS data running at maximum 480Mbps. The sensor has 18 LVDS output pairs:  16 data channels  1 control channel  1 clock channel The 16 data channels are used to transfer 12 -bit data words from sensor to receiver. The output clock channel transports a DDR clock, synchronous to the data on the other LVDS channels. This clock can be use d at the receiving end to sample the data. The data on the control channel contains status information on the validity of the data on the data channels, among other useful sensor status information. Details on the LVDS timing and format can be found in section 4 of this document.

2.4 SEQUENCER

The on-chip sequencer will generate all required control signals to operate the sensor from only a few external control clocks. This sequencer can be activated and programmed through the SPI interface. A detailed description of the SPI registers and sensor (sequencer) programming can be found in section 5 of this document.

2.5 SPI

The SPI interface is used to load the sequencer registers with data. The data in these registers is used by the sequencer while driving and reading out the image sensor. Features like windowing, sub sampling, gain and offset are programmed using this interface. The data in the on -chip registers can also be read back for test and debug of the surrounding system. Section 5 contains more details on register programming and SPI timing.

2.6 TEMPERATURE SENSOR

A 16-bit digital temperature sensor is included in the image sensor and can be controlled by the SPI-interface. The on- chip temperature can be obtained by reading out a dedicated SPI register (address 101-102). A calibration of the temperat ure sensor is needed by the surrounding system (for absolute temperature measurements).

3 DRIVING THE CMV20000

3.1 SUPPLY SETTINGS

The CMV20000 image sensor has the following supply settings: Supply name Recommended Value Absolute Min - Max Range Current typical Current peak VDD20 2.1V 1.6 - 2.2V 800mA 1A VDD33 3.3V 3V - 3.6V 170mA 0.6A VDDpix 3.0V 2.3V - 3.6V 20mA 8A Vres_h 3.3V 3.0V - 3.6V 5mA 0.1A See pin list for exact pin numbers for every supply. The peak current of VDD20 is drawn during read out, while the other supplies draw it during FOT. All supplies should have enough decoupling, especially VDDPIX. Application note AN03 has more details about these peaks waveforms.

3.2 BIASING

For optimal performance, some pins need to be decoupled to ground or to VDD. Please refer to the pin list for a detailed description for every pin and the appropriate decoupling if applicable.

3.3 DIGITAL INPUT PINS

The table below gives an overview of the external pins used to drive the sensor Pin name Description CLK_IN Master input clock, frequency range is (LVDS_CLK / 12). This clock is optional. LVDS_CLK_N/P High speed LVDS input clock, frequency range between 120 and 480 MHz SYS_RES_N System reset pin, active low signal. Resets the on - board sequencer and must be kept low during start- up FRAME_REQ Frame request pin. When a rising edge is detected on this pin the programmed number of frames is captured and sent by the sensor SPI_IN Data input pin for the SPI interface. The data to program the image sensor is sent over this pin. SPI_EN SPI enable pin. When this pin is high the data should be written/read on the SPI SPI_CLK SPI clock. This is the clock on which the SPI runs (max 20Mz) T_EXP1 Input pin which can be used to program the exposure time externally. Optional

3.4 ELECTRICAL IO SPECIFICATIONS

3.4.1 DIGITAL IO CMOS/TTL DC SPECIFICATIONS

Parameter Description Conditions min typ max Units VIH High level input voltage

2.0 VDD33 V

GND 0.8 V VOH High level output voltage VDD=3.3V IOH=-2mA 2.4 V VOL Low level output voltage VDD=3.3V IOL=2mA 0.4 V

3.4.2 LVDS RECEIVER SPECIFICATI ONS

Parameter Description Conditions min typ max Units VID Differential input voltage Steady state 100 350 600 mV VIC Receiver input range Steady state 0.0 2.4 V IID Receiver input current VINP|INN=1.2V±50mV, 0≤ VINP|INN≤2.4V 20 µA ∆IID Receiver input current difference |IINP – IINN| 6 µA

3.4.3 LVDS DRIVER SPECIFICATION S

Parameter Description Conditions min typ max Units VOD Differential output voltage Steady State, RL = 100Ω 247 350 454 mV ∆VOD Difference in VOD between complementary output states Steady State, RL = 100Ω 50 mV VOC Common mode voltage Steady State, RL = 100Ω 1.125 1.25 1.375 V ∆VOC Difference in VOC between complementary output states Steady State, RL = 100Ω 50 mV IOS,GND Output short circuit current to ground VOUTP=VOUTN=GND 24 mA IOS,PN Output short circuit current VOUTP=VOUTN 12 mA

3.5 INPUT CLOCK

The high speed LVDS input clock (LVDS_CLK_N/P) defines the output data rate of the CMV20000. The master clock (CLK_IN) must be 12 times slower and this clock but is optional. The maximum data rate of the output is 480Mbps which results in a LVDS_CLK_N/P of 480MHz (and a CLK_IN of 4 0MHz). The minimum frequencies are 10MHz for CLK_IN and 120MHz for LVDS_CLK_N/P. Any frequency between the minimum and maximum can be applied by the user and will result in a corresponding output data rate.

3.6 FRAME RATE CALCULATIO N

The frame rate of the CMV20000 is defined by 2 main factors. 1. Exposure time 2. Read out time For ease of use we will assume that the exposure time is shorter than the read out time. By assuming this , the frame rate is completely defined by the read out time (because the exposure time happens in parallel with the read -out time). The read-out time (and thus the frame rate) is defined by: 1. Output clock speed: max 480Mbps 2. Number of lines read-out 3. Number of outputs used: max 16 LVDS outputs (8 on the top and 8 on the bottom) This means that if any of the parameters above is changed, it will have an impact on the frame rate of the CMV20000. In normal operation (16 outputs @ 480Mbps, 12 bit and full resolution) this will result in 30 fps. Total readout time is composed of two parts: FOT (frame overhead time) + image readout time. 𝐹𝑂𝑇 = ((80 ∗ 𝑟𝑒𝑔82 + 𝑟𝑒𝑔82 So for reg82 = 80 and running at 480MHz this becomes: 𝐹𝑂𝑇 = (6410 + 1282) ∗ 25𝑛𝑠 = 192.3µ𝑠 The image read out time equals to 𝑅𝑒𝑎𝑑 𝑂𝑢𝑡 𝑇𝑖𝑚𝑒 = 641 ∗ 𝑐𝑙𝑘_per ∗ 𝑛𝑟_lines # 𝑠𝑖𝑑𝑒𝑠 𝑢𝑠𝑒𝑑 So for full resolution and running at 480MHz with both output sides used this becomes: 𝑅𝑒𝑎𝑑 𝑂𝑢𝑡 𝑇𝑖𝑚𝑒 = 641 ∗ 25𝑛𝑠 ∗ 3840 2 = 30.768𝑚𝑠 This results in a total frame time of: 𝐹𝑟𝑎𝑚𝑒 𝑡𝑖𝑚𝑒 = 𝐹𝑂𝑇 + 𝑅𝑒𝑎𝑑 𝑂𝑢𝑡 𝑡𝑖𝑚𝑒 So for the default settings this becomes: 𝐹𝑟𝑎𝑚𝑒 𝑡𝑖𝑚𝑒 = 192.3µ𝑠 + 30768 µ𝑠 = 30.96𝑚𝑠 And the frame rate becomes: 𝐹𝑟𝑎𝑚𝑒 𝑟𝑎𝑡𝑒 = 1 𝐹𝑟𝑎𝑚𝑒 𝑡𝑖𝑚𝑒 = 1 0.03096𝑠 = 32.3𝑓𝑝𝑠 See chapter 5.1.1 for detailed frame timing. Clk_per is the period of the pixel clock. This pixel clock frequency is equal to 1/12th (40MHz) of the LVDS input clock frequency (480MHz).

3.7 START-UP SEQUENCE

The following sequence should be followed when the CMV20000 is started up in default output mode ( 480Mbps, 12bit resolution).

Reference:CMV20000-datasheet-v2.3 CMV20000 Datasheet Page 12 of 47 © 2015 CMOSIS bvba 1μs 1μs Stable time Supply CLK_IN SYS_RES_N FRAME_REQ FIGURE 2: START-UP SEQUENCE FOR 480M BPS @ 12-BIT The CLK_IN and LVDS_CLK_N/P should only start after the rise time of the supplies (VDD33, VDD20, Vddpix and Vres_h go high together). The external reset pin should be released at least 1μs after the supplies have become stable. The first frame can be requested 1μs after the reset pin has been released. A n optional SPI upload (to program the sequencer) is possible 1μs after the reset pin has been released. In this case the F RAME_REQ pulse must be postponed until after the SPI upload has been completed.

3.8 RESET SEQUENCE

If a sensor reset is necessary while the sensor is running the following sequence should be followed. 1μs CLK_IN SYS_RES_N FRAME_REQ FIGURE 3: RESET SEQUENCE The on-board sequencer will be reset and all programming registers will return to their default start-up values when a falling edge is detected on the SYS_RES _N pin. After the reset there is a minimum time of 1μs needed before a FRAME_REQ pulse can be sent. All recommended register settings must be reloaded after a reset sequence.

3.9 SPI PROGRAMMING

Programming the sensor is done by writing the appropriate va lues to the on -board registers. These registers can be written over a simple serial interface (SPI). The details of the timing and data format are described below. The data written to the programming registers can also be read out over this same SPI interface. The SPI out doesn’t have a tri-state, so multiple SPI outputs cannot be on the same bus without a buffer.

3.9.1 SPI WRITE

The timing to write data over the SPI interface can be found below. SPI_EN SPI_IN SPI_CLK C=’1' A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 ½ CLK 1 CLK FIGURE 4: SPI WRITE TIMING

Reference:CMV20000-datasheet-v2.3 CMV20000 Datasheet Page 13 of 47 © 2015 CMOSIS bvba The data is sampled by the CMV20000 on the rising edge of the SPI_CLK. The SPI_CLK has a maximum frequency of 20MHz. The SPI_EN signal has to be high for half a clock period before the first databit is sampled. SPI_EN has to remain high for 1 clock period after the last databit is sampled. One write action contains 16 databits:  One control bit: First bit to be sent, indicates whether a read (‘0’) or write (‘1’) will occur on the SPI interface.  7 addr ess bits: These bits form the address of the programming register that needs to be written. The address is sent MSB first.  8 data bits: These bits form the actual data that will be written in the register selected with the address bits. The data is written MSB first. When several sensor registers need to be written , the timing above can be repeated with SPI_EN remaining high all the time. See the figure below for an example of 2 registers being written in burst. SPI_EN SPI_IN SPI_CLK C=’1' A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 C=’1' A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 ½ CLK 1 CLK FIGURE 5: SPI WRITE TIMING FOR 2 REGISTERS IN BURST The sample and hold time is 1/4th of the SPI clock period.

3.9.2 SPI READ

The timing to read data from the registers over the SPI interface can be found below. SPI_EN SPI_IN SPI_CLK C=’0' A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0SPI_OUT ½ CLK 1 CLK FIGURE 6: SPI READ TIMING To i ndicate a read action over the S PI interface, the control bit on the SPI_IN pin is made ‘0’. The address of the register being read out is sent immediately after this control bit (MSB first). After the LSB of the address bits, the data is launched on the SPI_OUT pin on the falling edge of the SPI_CLK. This means that the data should be sampled by the receiving system on the rising edge of the SPI_CLK. The data comes over the SPI_OUT with MSB first. The CMV20000 has to SPI read out pins: SPI_OUT_LEFT (pin T1) and SPI_OUT_RIGHT (pin R18). SPI_OUT_LEFT will read out every register, while SPI_OUT_RIGHT will only read out registers 103 to 126. Because of the large sensor there is some SPI read out delay. This delay is fixed and independent of the sensor or SPI clock.

Reference:CMV20000-datasheet-v2.3 CMV20000 Datasheet Page 14 of 47 © 2015 CMOSIS bvba A1 A0 D7 D6 SPI_CLK 40MHz SPI_IN SPI_OUT_LEFT registers 0 - 102 10ns 12.5ns 2.5ns D7 D6SPI_OUT_LEFT registers 103 - 126 26ns D7 D6SPI_OUT_RIGHT registers 103 - 126 20ns FIGURE 7: SPI DELAY So when sampling on the rising SPI_CLK edge it is advised to have a SPI_CLK of 10MHz maximum.

3.10 REQUESTING A FRAME

After starting up the sensor (see section 3. 7), a number of frames can be requested by sending a FRAME_REQ pulse. The number of frames can be set by programming the appropriate register (addresses 22 and 23). The default number of frames to be grabbed is 1. In internal-exposure-time mode, the exposure time will start after this FRAME_RE Q pulse. In the external -exposure- time mode, the read-out will start after the FRAME_REQ pulse. Both modes are explained into detail in the sections below.

3.10.1 INTERNAL EXPOSURE CONTROL

In this mode, the exposure time is set by programming the appropriate registers (address 32-33) of the CMV20000. After the high state of the FRAME_REQ pulse is detected, the exposure time will start immediately. When the exposure time ends (as programmed in the registers), the pixels are being sampled and prepared for read -out. This sequence is called the frame overhead time (FOT). Immediately after the FOT, the frame is read -out automatically. If more than one frame is requested, the exposure of the next frame starts already during the read -out of the previous one. See the diagram below for more details. FRAME_REQ Exposure timeFrame1_cycle FOT Read-out time Exposure timeFrame2_cycle FOT Read-out time FIGURE 8: REQUEST FOR 2 FRAMES IN INTERNAL- EXPOSURE-TIME MODE When the exposure time is shorter than the read -out time, the FOT and read -out of the next frame will start immediately after the read-out of the previous frame. FRAME_REQ Frame1_cycle FOT Read-out time Exposure timeFrame2_cycle FOT Read-out time Exposure time FIGURE 9: REQUEST FOR 2 FRAMES IN INTERNAL -EXPOSURE-TIME MODE WITH EXPOSURE TIME < READ-OUT TIME

3.10.2 EXTERNAL EXPOSURE CONTROL

The exposure time can also be programmed externally by using the T_EXP1 input pin. This mode needs to be enabled by setting the appropriate register (address 81). In this case, the exposure starts when a high state is detected on the T_EXP1 pin. When a high state is detected on the FRAME_REQ input, the exposure time stops and the read -out will start automatically. A new exposure can start by sending a pulse to the T_EXP1 pin during or after the read-out of the previous frame. FRAME_REQ Exposure timeFrame1_cycle FOT Read-out time Exposure timeFrame2_cycle FOT Read-out time T_EXP1 FIGURE 10: REQUEST FOR 2 FRAMES USING EXTERNAL-EXPOSURE-TIME MODE

4 READING OUT THE SENSO R

The CMV20000 has LVDS (low voltage differe ntial signaling) outputs to transport the image data to the surrounding system. Next to 16 data channels, the sensor also has two other LVDS channels for control and s ynchronization of the image data. In total, the sensor has 18 LVDS output pairs (2 pins for each LVDS channel):  16 Data channels  1 Control channel  1 Clock channel This means that a total of 36 pins of the CMV20000 are used for the LVDS outputs ( 32 for data + 2 for LVDS clock + 2 for control channel). See the pin list for the exact pin numbers of the LVDS outputs. The 16 data channels are used to transfer the 12-bit pixel data from the sensor to the receiver in the surrounding system . The output clock channel transports a clock, synchronous to the data on the other LVDS channels. This clock can be used at the receiving end to sample the data. This clock is a DDR clock which means that the frequency will be half of the output data rate. When 480Mbps output data rate is used, the LVDS output clock will be 240MHz. The data on the control channel contains status information on the validity of the data on the data channels. Information on the control channel is grouped in 12-bit words that are transferred synchronous to the 16 data channels.

4.1 LVDS LOW-LEVEL PIXEL TIMING

The figure below shows the timing for transfer of 12-bit pixel data over one LVDS output. To make the timing more clear, the figure shows only the p-channel of each LVDS pair. The data is transferred LSB first, with the transfer of bit D[0] during the high phase of the DDR output clock. LVDS_CLOCK_OUT DATA_OUT D(10) D(11) D(0) D(1) D2) D(3) FIGURE 11: 10: 12-BIT PIXEL DATA ON AN LVDS CHANNEL The time ‘T1’ in the diagram above is 1/12th of the period of the input clock (CLK_IN) of the CMV20000. If a frequency of 40MHz is used for CLK_IN (max), this results in a 240MHz LVDS_CLOCK_OUT.

4.2 LVDS READOUT TIMING

The readout of image data is grouped in bursts of 640 pixels per channel (2 rows at the same time) . Each pixel is 1 2 bits of data (see section 4.1.1). One complete pixel period equals one period of the master clock input. For details on pixel remapping and pixel vs channel location please see section 4. 1.3 of this document. An overhead time exists between two bursts of 640 pixels. This overhead time has the length of one pixel read-out (i.e. the length of 12 bits at the selected data rate) or one master clock cycle. 4.2.1 16 OUTPUT CHANNELS By default, all 16 data output channels are used to transmit the image data. This means that two entire rows of image data are transferred in one slot of 640 pixel periods (16/2 x 640 = 5120). Next figure shows the timing for the top and bottom LVDS channels.

640 OH 640

DATA_OUT_BOTTOM FIGURE 12: OUTPUT TIMING IN DEFAULT 16 CHANNEL MODE Only when 16 data outputs, running at 480Mbps, are used, the frame rate of 30fps can be achieved (default). 4.2.2 8 OUTPUT CHANNELS The CMV20000 has the possibility to use only 8 LVDS output channels. This setting can be programmed in the register with address 80 (see section 5.7). In such multiplexed output mode, only the 8 bottom LVDS channels are used . The readout of one row takes 1*640 periods. . This means that ne entire rows of image data are transferred in one slot of 640 pixel periods (8 x 640 = 5120). Next figure shows the timing for the bottom LVDS channels. IDLE OH 640 OH 640 OH 640 Row 0 Row 1 Row 2 DATA_OUT_BOTTOM FIGURE 13: OUTPUT TIMING IN 8 CHANNEL MODE In this 2 channel mode, the frame rate is reduced with a factor of 2 compared to 4 channel mode.

4.3 PIXEL REMAPPING

Depending on the number of output channels, the pixels are read out by different channels and come out at a different moment in time. With the details from the next sections, the end user is able to remap the pixel values at the output to their correct image array location. 4.3.1 16 OUTPUTS The figure below shows the location of the image pixels versus the output channel of the image sensor. IDLE Pixel 0 to 639Channel 1 bot IDLE Pixel 0 to 639 Channel 2 bot Pixel 640 to 1279 Pixel 640 to 1279 Row 0 IDLEChannel 8 bot Pixel 4480 to 5119 Pixel 4480 to 5119 Row 2 IDLE Pixel 0 to 639Channel 1 top IDLE Pixel 0 to 639 Channel 2 top Pixel 640 to 1279 Pixel 640 to 1279 Row 1 IDLEChannel 8 top Pixel 4480 to 5119 Pixel 4480 to 5119 Row 3 … …… … …… FIGURE 14: PIXEL REMAPPING FOR 16 OUTPUT CHANNELS

Reference:CMV20000-datasheet-v2.3 CMV20000 Datasheet Page 18 of 47 © 2015 CMOSIS bvba 16 bursts (8 x 2) of 640 pixels happen in parallel on the data outputs. This means that two complete rows are read out in one burst. The amount of rows that will be read out depends on the value in the corresponding register. By default there are 3840 rows being read out. 4.3.2 8 OUTPUTS When only 8 outputs are used, the pixel data is placed on the outputs as detailed in the figure below. 8 bursts of 640 pixels happen in parallel on the data outputs. This means that one complete row is read out in one burst. The time needed to read out two rows is doubled compared to when 16 outputs are used. The top LVDS channels are not being used in this mode, so they can be turned off by setting the correct bits in the register with address 95-97. Turning off these channels will reduce the power consumption of the chip. The amount of rows that will be read out depends on the value in the corresponding register. By default there are 3840 rows being read out. IDLE Pixel 0 to 639Channel 1 bot IDLE Pixel 0 to 639 Channel 2 bot Pixel 640 to 1279 Pixel 640 to 1279 Row 0 IDLEChannel 8 bot Pixel 4480 to 5119 Pixel 4480 to 5119 Row 1 … …… FIGURE 15: PIXEL REMAPPING FOR 8 OUTPUT CHANNELS

4.4 CONTROL CHANNEL

The CMV20000 has one LVDS output channel dedicated for the valid data synchronization and timing of the output channels. The end user must use this channel to know when valid image dat a or training data is available on the data output channels. The control channel transfers status information in 12-bit word format. Every bit of the word ha s a specific function. Next table describes the function of the individual bits. Bit Function Description [0] DVAL Indicates valid pixel data on the outputs [1] LVAL Indicates validity of the readout of a row [2] FVAL Indicates the validity of the readout of a frame [3] ‘0’ Constant zero [4] ‘0’ Constant zero [5] FOT Indicates when the sensor is in FOT (sampling of image data in pixels) (*) [6] INTE1 Indicates when pixels of integration block 1 are integrating (*) [7] INTE2 Indicates when pixels of integration block 2 are integrating (*) [8] ‘0’ Constant zero [9] ‘1’ Constant one [10] ‘0’ Constant zero [11] ‘0’ Constant zero (*)Note: The status bits are purely informational. These bits are not required to know when the data is valid. The DVAL, LVAL and FVAL signals are sufficient to know when to sample the image data.

4.4.1 DVAL, LVAL, FVAL

The first three bits of the control word must be used to identify valid data and the readout status. Next figure shows the timing of the DVAL, LVAL and FVAL bits of the control channel with an example of the readout of a frame of 6 rows (default is 3840 rows). This example uses the default mode of 16 outputs (8 outputs on each side).

4.4.2 DIGITAL TEST PINS

Pins D1 (Tdig2) and D3 (Tdig1) can be used as digital outputs to monitor the state of the sensor. Register 92 can be used to select a signal on these pins. Reg92[6:4] Tdig2 Reg92[3:0] Tdig1

0 LVAL 0 FVAL

3 INTE_1 2 FOT

7 CLK_OUT (=LVDS_CLK/12) 3 INTE_2

4.5 TRAINING DATA

To synchronize the receiving side with the LVDS outputs of the CMV20000, a known data pattern can be put on the output channels. This pattern can be used to “train” the LVDS receiver of the surrounding system to achieve correct word alignment of the image data. Such a training pattern is put on all 16 data channel outputs when there is no valid image data to be sent (so, also in between bursts of 640 pixels). The training pattern is a 1 2-bit data word that replaces the pixel data. The sensor has a 12-bit sequencer register (address 90-90) that can be loaded through the SPI to change the contents of the 12-bit training pattern. The control channel does not send a training pattern, because it is used to send control information at all time. Word alignment can be done on this channel when the sensor is idle (not exposing or sending image data). In this case all bits of the control word are zero, except for bit [9]. The figure below shows the location of the training pattern (TP) on the data channels and control channels when the sensor is in idle mode and when a frame of 6 rows is read-out. The default mode of 16 outputs is selected. Training pattern TP 640 TP 640 TP 640Data channels DVAL LVAL FVAL Control channel Training pattern Control information Sensor in idle mode FIGURE 17: TRAINING PATTERN LOCATION IN THE DATA CHANNEL AND CONTROL CH ANNEL. The LVDS outputs are not aligned with the LVDS output clock. Every channel (per odd/even side) has a skew of +600ps compared to the previous channel. The control channel and both odd and even channels 1 are aligned with the clock. This skew will become larger than a LVDS clock period and therefor bit and word alignm ent is needed in the receiving side.

Reference:CMV20000-datasheet-v2.3 CMV20000 Datasheet Page 20 of 47 © 2015 CMOSIS bvba LVDS CLOCK_OUT CTR OUT1E OUT1O OUT2E OUT2O D(0) D(1) D2) D(0) D(1) D2) D(0) D(1) D2) D(0) D(1) D2) D(0) D(1) D2) 600ps 600ps OUT3E OUT3O D(0) D(1) D2) D(0) D(1) D2) 1200ps 1200ps OUT8E OUT8O D(0) D(0) 4200ps ... 4200ps FIGURE 18: LVDS OUTPUT SKEW

4.6 TEST PATTERN

Instead of sending image data, the sensor can generate a fixed two-dimensional test image (after sending a frame request), if the test pattern mode is enabled. This setting can be programmed in the register by setting register 83[0] to 1. The test pattern is the sum of the row number, the pixel number and the data output channel number. Next figure shows an example of the test pattern data.

5 IMAGE SENSOR PROGRAMM ING

This section explains how the CMV20000 can be programmed using the on-board sequencer registers.

5.1 EXPOSURE MODES

The exposure time can be programmed in two ways, externally or internally. Externally, the exposure time is defined as the time between the rising edge of T_EXP1 and the rising edge of FRAME_REQ (see section 3.10 for more details). Internally, the exposure time is set by uploading the desired value to the corresponding sequencer register. The table below gives an overview of the registers involved in the exposure mode. Exposure time settings Register name Register address Default value Description of the value Exp_ext 81[0] 0 0: Exposure time is defined by the value uploaded in the sequencer register (32-33) 1: Exposure time is defined by the pulses applied to the T_EXP1 and FRAME_REQ pins. Exp_time 32-33 3840 When the Exp_ext register is set to ‘0’ , the value in this register defines the exposure time according to the formula below. Minimum = 1. 𝐴𝑐𝑡𝑢𝑎𝑙 𝐸𝑥𝑝𝑜𝑠𝑢𝑟𝑒 𝑡𝑖𝑚𝑒 = (((𝐸𝑥𝑝_time − 1) ∗ 641) + 1 + (47 ∗ 𝑟𝑒𝑔82)) ∗ 𝑐𝑙𝑘_𝑝𝑒𝑟 Here clk_per is the period of the input LVDS_CLK multiplied by 12 (so for 480MHz this is 25ns). The minimum exposure time then becomes 94µs.

5.1.1 FRAME TIMING

A detailed view of the frame timing can be seen below. Frame_REQ INTE_1 (Exp_time - 1) * 641 + 1) * clk_per 47*80*clk_per Actual exposure time 6410 * clk_per 1282 * clk_per 641 * (#lines / #sides) * clk_per Actual FOT FOT FVAL

5.2 HIGH DYNAMIC RANGE MO DE

5.2.1 PIECEWISE LINEAR RESP ONSE

The CMV20000 has the possibility to achieve a high optical dynamic range by using a piecewise linear response. This feature will clip illuminated pixels which reach a programmable voltage, while leaving the darker pixels untouched .

5.2.1.1 PIECEWISE LINEAR RESP ONSE WITH INTERNAL EXPOSU RE MODE

The following registers need to be pr ogrammed when a piecewise linear response in internal exposure mode is desired. HDR settings – PLR Register name Register address Default value Description of the value Exp_time 32-33 3840 The value in this register defines the total exposure time according following formula: ((Exp_time - 1) x 641 + 1 + 47 x FOT_mult) x clk_per, where clk_per is the period of the master input clock. Nr_slopes 37[1:0] 1 The value in this register defines the number of slopes (min=1, max=3). Exp_s2 39-40 0 The value in this register defines the exposure time from the start of the second slope to the end of the total exposure time . Formula: ((Exp_s2 - 1) x 641 + 1 + 47 x FOT_mult) x clk_per , where clk_per is the period of the master input clock. Exp_s3 42-43 0 The value in this register defines the exposure time from the start of the third slope to the end of the total exposure time. Formula: ((Exp_s3 - 1) x 641 + 1 + 47 x FOT_mult) x clk_per, where clk_per is the period of the master input clock. Vlevel_s2 114[6:0] 64 Bit[6] = enable Bit[5:0] dac value Low level voltage during dual slope operation. The value in this register defines the Vlevel_s2 voltage (DAC setting). The DAC range goes from 0 to 2.1V. Vlevel_s3 115[6:0] 64 Bit[6] = enable Bit[5:0] dac value Low level voltage during triple slope operation. The value in this register defines the Vlevel_s3 voltage (DAC setting). The DAC range goes from 0 to 2.1V.

5.2.1.2 PIECEWISE LINEAR RES PONSE WITH EXTERNAL EXPOSU RE MODE

When external exposure time is used and a piecewise linear response is desired, the following registers should be programmed. HDR settings – PLR Register name Register address Default value Description of the value Nr_slopes_ex 15[1:0] 1 The value in this register defines the number of slopes (min=1, max=3). Vlevel_s2_ex 112[6:0] 64 Bit[6] = enable Bit[5:0] dac value Low level voltage during dual slope operation. The value in this register defines the Vlevel_s2 voltage (DAC setting). The DAC range goes from 0 to 2.1V. Vlevel_s3_ex 113[6:0] 64 Bit[6] = enable Bit[5:0] dac value Low level voltage during triple slope operation. The value in this register defines the Vlevel_s3 voltage (DAC setting). The DAC range goes from 0 to 2.1V.

Reference:CMV20000-datasheet-v2.3 CMV20000 Datasheet Page 25 of 47 © 2015 CMOSIS bvba The timing that needs to be applied in this external exposure mode looks like the one below. FRAME_RE Q T_EXP1 Total exposure time Exposure s2 Exposure s3 FIGURE 23: PIECEWISE LINEAR RESPONSE WITH EXTERNAL EXPOSURE MODE

5.3 WINDOWING

To limit the amount of data or to increase the frame rate of the sensor, windowing in Y direction is possible. The number of lines and start address can be set by programming the appropriate registers. The CMV20000 has the possibility to read out multiple (max=8) predefined subwindows in one read-out cycle. The default mode is to read-out one window with the full frame size (5120 x 3840).

5.3.1 SINGLE WINDOW

When a single window is read out, the start address and size can be uploaded in the corresponding registers. The default start address is 0 and the default size is 3840 (full frame). Windowing – single window Register name Register address Default value Description of the value Start_single 24-25 0 The value in this register defines the start address of the window in Y (min=0, max=3839) Number_lines_single 26-27 3840 The value in this register defines the number of lines read out by the sensor (min=1, max=3840) 5120 3840 Number_lines_single Start_single FIGURE 24: SINGLE WINDOW SETTINGS

5.3.2 MULTIPLE WINDOWS

The CMV20000 can read out a maximum of 8 different subwindows in one read -out cycle. The location and length of these subwindows must be programmed in the correct registers. The total number of lines to be read -out (sum of all windows) needs to be specified in the Number_lines register. The registers which need to be programmed for the multiple windows can be found in the table below. Windowing – multiple windows Register name Register address Default value Description of the value Multwin_en 44 0 0: multiple windows mode disabled 1: multiple windows mode enabled Number_lines 45-46 0 The value in this register defines the total number of lines read-out by the sensor (min=1, max=3840) Start1 47-48 0 The value in this register defines the start address of the first window in Y (min=0, max=3839) Number_lines1 63-64 0 The value in this register defines the number of lines of the first window (min=1, max=3840) Start2 49-50 0 The value in this register defines the start address of the second window in Y (min=0, max=3839) Number_lines2 65-66 0 The value in this register defines the number of lines of the second window (min=1, max=3840) Start3 51-52 0 The value in this registe r defines the start address of the third window in Y (min=0, max=3839) Number_lines3 67-68 0 The value in this register defines the number of lines of the third window (min=1, max=3840) Start4 53-54 0 The value in this register defines the start address of the fourth window in Y (min=0, max=3839) Number_lines4 69-70 0 The value in this register defines the number of lines of the fourth window (min=1, max=3840) Start5 55-56 0 The value in this registe r defines the start address of the fifth window in Y (min=0, max=3839) Number_lines5 71-72 0 The value in this register defines the number of lines of the fifth window (min=1, max=3840) Start6 57-58 0 The value in this register defines the start address of the sixth window in Y (min=0, max=3839) Number_lines6 73-74 0 The value in this register defines the number of lines of the sixth window (min=1, max=3840) Start7 59-60 0 The value in this register defines the start address of the seventh window in Y (min=0, max=3839) Number_lines7 75-76 0 The value in this register defines the number of lines of the seventh window (min=1, max=3840) Start8 61-62 0 The value in this register defines the start addre ss of the eighth window in Y (min=0, max=3839) Number_lines8 77-78 0 The value in this register defines the number of lines of the eighth window (min=1, max=3840)

Reference:CMV20000-datasheet-v2.3 CMV20000 Datasheet Page 27 of 47 © 2015 CMOSIS bvba 5120 3840 Number_lines4 start4 Number_lines3 start3 Number_lines2 start2 Number_lines1 start1 Number_lines = Number_lines1 + Number_lines2 + Number_lines3 + Number_lines4 FIGURE 25: EXAMPLE OF 4 SUBWIND OWS READ-OUT

5.4 IMAGE FLIPPING

The image coming out of the image sensor, can be flipped in X and/or Y direction. This means that if flipping is enabled in both directions the upper right pixel is read out first (instead of lower left). The following registers are involved in image flipping Image flipping Register name Register address Default value Description of the value Image_flipping 85[1:0] 0 0: No image flipping 1: Image flipping in X 2: Image flipping in Y 3: Image flipping in X and Y

5.5 IMAGE SUBSAMPLING

To maintain the same field of view but reduce the amount of data coming out of the sensor, a subsampling mode is implemented on the chip. Different subsampling schemes can be programmed by setting the appropriate registers. These subsampling schemes can take into account whether a color or monochrome sensor is used to preserve the Bayer pattern information. The registers involved in subsampling are detailed below. A distinction is made between a simple and advanced mode (can be used for color devices). Subsampling can be enabled in every windowing mode.

5.5.1 SIMPLE SUBSAMPLING

Image subsampling - simple Register name Register address Default value Description of the value Number_lines_single 26-27 3840 The value in this register defines the total number of lines read out by the sensor (min=1, max=3840) Sub_s 28-29 0 Number of rows to skip (min=0, max=3839) Sub_a 30-31 0 Identical to Sub_s

Reference:CMV20000-datasheet-v2.3 CMV20000 Datasheet Page 28 of 47 © 2015 CMOSIS bvba The figures below give two subsampling examples (skip 4x and skip 1x). Sub_s = 4 Sub_a = 4 Number_lines = sum of red lines Sub_s = 1 Sub_a = 1 Number_lines = sum of red lines FIGURE 26: SUBSAMPLING EXAMPLES (SKIP 4X AND SKIP 1X)

5.5.2 ADVANCED SUBSAMPLING

When a color sensor is used, the subsampling scheme should take into account that a Bayer color filter is applied on the sensor. This Bayer pattern should be preserved when subsampling is used. This means that the number of rows to be skipped should always be a mu ltiple of two. An advanced subsampling scheme can be programmed to achieve these requirements. Of course, this advanced subsampling scheme can also be programmed in a monochrome sensor. See the table of registers below for more details. Image subsampling - advanced Register name Register address Default value Description of the value Number_lines_single 26-27 3840 The value in this register defines the total number of lines read out by the sensor (min=1, max=3840) Sub_s 28-29 0 Should be ‘0’ at all times Sub_a 30-31 0 Number of rows to skip, it should be an even number between (0 and 3838). The figures below give two subsampling examples (skip 4x and skip 2x) in advanced mode.

Reference:CMV20000-datasheet-v2.3 CMV20000 Datasheet Page 29 of 47 © 2015 CMOSIS bvba Sub_s = 0 Sub_a = 4 Number_lines = sum of red lines Sub_s = 0 Sub_a = 2 Number_lines = sum of red lines FIGURE 27: SUBSAMPLING EXAMPLES IN ADVANCED MODE (SK IP 4X AND SKIP2X)

5.6 NUMBER OF FRAMES

When internal exposure mode is selected, the number of frames sen t by the sensor after a frame request can be programmed in the corresponding sequencer register. Number of frames Register name Register address Default value Description of the value Number_frames 22-23 1 The value in this register defines the number of frames grabbed and sent by the image sensor in internal exposure mode (min =1, max = 65535)

5.7 OUTPUT MODE

When LVDS output mode is selected, t he number of LVDS channels can be selected by programming the appropriate sequencer register. The pixel remapping scheme and the read-out timing for each mode can be found in section 4 of this document. Output mode Register name Register address Default value Description of the value Output_mode 80 0 0: 16 outputs 1: 8 outputs

5.8 FOT MULTIPLIER

The length of the FOT can be programmed using the register below. It is not recommended to set it below 80 as loss in swing and increase in FPN can occur. FOT multiplier Register name Register address Recommended value Description of the value FOT_mult 82 80 The value in this register defines the length of the FOT according to the following formula: (80 x FOT_mult + FOT_mult/8) x clk_per, where clk_per is the period of the master input clock (min=8, max=248, multiple of 8)

5.9 TRAINING PATTERN

As detailed in section 4.5, a training pattern is sent over the LVDS data channels whenever no valid image data is sent. This training pattern can be programmed using the sequencer register. Training pattern Register name Register address Default value Description of the value Training_pattern 90-91 85 The 12 LSBs of this 16 bit word are sent

5.10 TEST PATTERN

As detailed in section 4.6, a test pattern can be generated whenever no training data is sent. This test pattern can be enabled using the register below. Test pattern Register name Register address Default value Description of the value Testpattern_en 83 0 0: test pattern disabled 1: test pattern enabled

5.11 DATA RATE

During start-up or after a sequencer reset, the data rate can be changed if a lower speed than 480Mbps is desired. This can be done by applying a lower master input clock (CLK_IN) and lowe LVDS_CLK_N/P to the sensor. See section 3.5 for more details on the input clock. See section 3. 7 and 3.8 for details on how and when the data rate can be changed.

5.12 POWER C ONTROL

The power consumption of the CMV20000 can be regulated by disabling the LVDS data channels when they are not used (in 8 channel mode). Power control Register name Register address Default value Description of the value Channel_en 95-96 262143 Bits 0-7 enable/disable the bottom data output channels Bits 8-15 enable/disable the top data output channels Bit 16 enables/disables the clock channel Bit 17 enables/disables the control channel Bit 18 enables/disables the clock receiver 0: disabled 1: enabled

5.13 OFFSET AND GAIN

5.13.1 OFFSET

A digital offset can be applied to the output signal. The dark level offset can be programmed by setting the desired value in the sequencer register s. The offset register is a 12 bit 2’s complement representation of the actual desired offset to be added or subtracted from a fixed value of 1296. Default offset register value of 2840 is the 2’s complement representation of -1256  default dark level is 1296 + (-1256) = 40. Offset Register name Register address Default value Description of the value Offset 88-89 2840 The value in this register defines the dark level offset applied to the output signal

5.13.2 GAIN

An analog gain and ADC gain can be applied to the output signal. The analog gain is applied by a PGA in every column. The digital gain is applied by the ADC. The ADC gain has to be changed when changing the clock speed from 480MHz. Gain Register name Register address Default value Description of the value PGA_gain 93 bits[3:2] 0 0: x0.8 1: x1 (recommended) 2: x1.2 3: x1.4 ADC_gain 126 bits[5:0] 32 32 Below is the ADC_gain setting vs. the actual gain. When for example you run the sensor at 240MHz, you have to use an actual gain of 480/240 = x2 or value 48 to compensate (the ADC conversion is dependent on the clock speed). FIGURE 28: ADC_GAIN VS ACTUAL GAIN

5.14 TEMPERATURE

The register below contains the temperature data. Temperature Register name Register address Default value Description of the value Temperature 101-102 0 This register contains the temperature data

6 REGISTER OVERVIEW

The table below gives an overvi ew of all the sensor registers. The registers with the remark “Do not change” should not be changed. Register overview Address Default Value Remark Bit[7] Bit[6] Bit[5] Bit[4] Bit[3] Bit[2] Bit[1] Bit[0] 0 1 Do not change 1 0 Do not change 2 0 Do not change 3 0 Do not change 4 0 Do not change 5 15 Do not change 6 0 Do not change 7 0 Do not change 8 0 Do not change 9 0 Do not change 10 32 Do not change 11 0 Do not change 12 32 Do not change 13 0 Do not change 14 0 Do not change 15 1 Nr_slopes_ex[1:0] 16 0 Do not change 17 0 Do not change 18 0 Do not change 19 0 Do not change 20 0 Do not change 21 0 Do not change 22 1 Number_frames[7:0] 23 0 Number_frames[15:8] 24 0 Start_single[7:0] 25 0 Start_single[15:8] 26 0 Number_lines_single[7:0] 27 15 Number_lines_single[15:8] 28 0 Sub_s[7:0] 29 0 Sub_s[15:8] 30 0 Sub_a[7:0] 31 0 Sub_a[15:8] 32 0 Exp_time[7:0] 33 15 Exp_time[15:8] 34 0 Do not change 35 15 Do not change 36 0 Do not change 37 1 Nr_slopes[1:0] 38 0 Do not change 39 0 Exp_s2[7:0] 40 0 Exp_s2[15:8] 41 0 Do not change 42 0 Exp_s3[7:0] 43 0 Exp_s3[15:8] 44 0 Multwin_en 45 0 Number_lines[7:0]

Reference:CMV20000-datasheet-v2.3 CMV20000 Datasheet Page 33 of 47 © 2015 CMOSIS bvba Register overview Address Default Value Remark Bit[7] Bit[6] Bit[5] Bit[4] Bit[3] Bit[2] Bit[1] Bit[0] 46 0 Number_lines[15:8] 47 0 Start1[7:0] 48 0 Start1[15:8] 49 0 Start2[7:0] 50 0 Start2[15:8] 51 0 Start3[7:0] 52 0 Start3[15:8] 53 0 Start4[7:0] 54 0 Start4[15:8] 55 0 Start5[7:0] 56 0 Start5[15:8] 57 0 Start6[7:0] 58 0 Start6[15:8] 59 0 Start7[7:0] 60 0 Start7[15:8] 61 0 Start8[7:0] 62 0 Start8[15:8] 63 0 Number_lines1[7:0] 64 0 Number_lines1[15:8] 65 0 Number_lines2[7:0] 66 0 Number_lines2[15:8] 67 0 Number_lines3[7:0] 68 0 Number_lines3[15:8] 69 0 Number_lines4[7:0] 70 0 Number_lines4[15:8] 71 0 Number_lines5[7:0] 72 0 Number_lines5[15:8] 73 0 Number_lines6[7:0] 74 0 Number_lines6[15:8] 75 0 Number_lines7[7:0] 76 0 Number_lines7[15:8] 77 0 Number_lines8[7:0] 78 0 Number_lines8[15:8] 79 0 Do not change 80 0 Output_mode 81 0 Exp_ext 82 80 FOT_mult[7:0] 83 0 Testpattern_en 84 129 Set to 131 85 0 Image_flipping[1:0] 86 0 Set to 3 87 254 Set to 0 88 24 Offset[7:0] 89 11 Offset[11:8] 90 85 Training_pattern[7:0] 91 0 Training_pattern[15:8] 92 0 Do not change 93 0 PGA_Gain[3:2) 94 136 Set to 72 95 255 Channel_en[7:0] 96 255 Channel_en[15:8] 97 3 Channel_en[18:16] Set to 7

Reference:CMV20000-datasheet-v2.3 CMV20000 Datasheet Page 34 of 47 © 2015 CMOSIS bvba Register overview Address Default Value Remark Bit[7] Bit[6] Bit[5] Bit[4] Bit[3] Bit[2] Bit[1] Bit[0] 98 0 Do not change 99 0 Do not change 100 0 Do not change 101 0 Temp[7:0] Do not change 102 0 Temp[15:8] Do not change 103 136 Set to 64 104 136 Set to 102 105 136 Set to 68 106 96 Do not change 107 96 Do not change 108 96 Set to 228 109 96 Set to 210 110 64 Do not change 111 64 Do not change 112 64 Vlevel_s2_ex[6:0] 113 64 Vlevel_s3_ex[6:0] 114 64 Vlevel_s2[6:0] 115 64 Vlevel_s3[6:0] 116 96 Set to 91 117 96 Set to 91 118 96 Do not change 119 96 Do not change 120 96 Do not change 121 255 Set to 47 122 255 Do not change 123 64 Set to 102 124 0 Do not change 125 0 Do not change 126 32 ADC_gain[5:0] 127 32 Do not change Note: The default value of the “do not change” registers should not be overwritten.

7 MECHANICAL SPECIFICAT IONS

7.1 PACKAGE DRAWING

FIGURE 29: PACKAGE DRAWING OF T HE CMV20000. ALL DISTANCES IN MM. Package tolerances and alignment are:  Tilt image sensor : +/- 0.05 degree  Rotation image sensor : +/- 0.3 degree  Placement image sensor : +/- 150 um  Alignment image sensor to the top of the package : 1 mm +/- 0.13 mm Pin alignment tolerances are specified as 1% however tolerances measured are 0.18% max.

7.2 ASSEMBLY DRAWING

FIGURE 30: ASSEMBLY DRAWING O F CMV20000

7.3 COVER GLASS

The cover glass of the CMV20000 has following specifications:  Reflection(abs) <= 1.5% @ 400 – 900 nm (per surface), Angle Off Interest = 15O  2 sides AR-coated When a color sensor is used an IR-cutoff filter should be placed in the optical path of the sensor.

7.4 COLOR FILTERS

When a color version of the CMV20000 is used, the color filters are applied in a Bayer pattern. The color version of the CMV20000 always has micro lenses. The use of an IR cut-off filter in the optical path of the CMV20000 image sensor is necessary to obtain good color separation when using light with an IR component. A RGB Bayer pattern is used on the CMV 20000 image sensor. The order of the RGB filter can be found in the drawing below. FIGURE 31: RGB BAYER PATTERN ORDER

7.5 QE AND SPECTRAL RESPONSE

The typical QE and spectral response of the CMV20000 color/monochrome with micro lenses and cover glass can be found below. FIGURE 32: TYPICAL QE OF THE CMV20000 FIGURE 33: TYPICAL SPECTRAL RESPONSE OF THE CMV20000 350 450 550 650 750 850 950 1050 Quantum Efficiency [%] Wavelength [nm] Quantum Efficiency BLUE GREEN1 GREEN2 RED Mono 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 350 450 550 650 750 850 950 1050 Spectral Response [A\\W] Wavelength [nm] Spectral Response BLUE GREEN1 GREEN2 RED Mono

7.6 ANGULAR RESPONSE

FIGURE 34: ANGULAR RESPONSE 100 -45 -35 -25 -15 -5 5 15 25 35 45 Relative response [%] Angle of incoming light [°] Horizontal Vertical

8 PIN LIST

A2 OUTE1_P LVDS positive output data even rows channel1 bottom LVDS output A3 VDD20 2.1V supply Supply A4 OUTE2_P LVDS positive output data even rows channel2 bottom LVDS output A5 VDD20 2.1V supply Supply A6 OUTE3_P LVDS positive output data even rows channel3 bottom LVDS output A7 VDDPIX 2.3V -> 3.3V DEFAULT 2.8V supply Supply A8 OUTE4_P LVDS positive output data even rows channel4 bottom LVDS output A9 GND Ground pin Ground A10 OUTE5_N LVDS negative output data even rows channel5 bottom LVDS output A11 VDD20 2.1V supply Supply A12 OUTE6_N LVDS negative output data even rows channel6 bottom LVDS output A13 VDDPIX 2.3V -> 3.3V DEFAULT 2.8V supply Supply A14 OUTE7_N LVDS negative output data even rows channel7 bottom LVDS output A15 GND Ground pin Ground A16 OUTE8_N LVDS negative output data even rows channel8 bottom LVDS output A17 VDD20 2.1V supply Supply A18 CMD_LVDS decouple with 470nF to ground Bias B1 DIO2 Diode 2 for test (connect to GND) Test B2 OUTE1_N LVDS negative output data even rows channel1 bottom LVDS output B3 GND Ground pin Ground B4 OUTE2_N LVDS negative output data even rows channel2 bottom LVDS output B5 GND Ground pin Ground B6 OUTE3_N LVDS negative output data even rows channel3 bottom LVDS output B7 GND Ground pin Ground B8 OUTE4_N LVDS negative output data even rows channel4 bottom LVDS output B9 VDD33 3.3V supply Supply B10 OUTE5_P LVDS positive output data even rows channel5 bottom LVDS output B11 GND Ground pin Ground B12 OUTE6_P LVDS positive output data even rows channel6 bottom LVDS output B13 GND Ground pin Ground B14 OUTE7_P LVDS positive output data even rows channel7 bottom LVDS output B15 VDD33 3.3V supply Supply B16 OUTE8_P LVDS positive output data even rows channel8 bottom LVDS output B17 GND Ground pin Ground B18 CMD_COL_AMPL decouple with 470nF to ground Bias C1 TANA Test pin for analog signals ( can be left floating ) Analog output C2 OUTCTR_N LVDS negative control output channel LVDS output C3 DIO1 Diode 1 for test (connect to GND) Test C16 GND Ground pin Ground C17 CMDN decouple with 470nF to ground Bias C18 CMD_COL_PC decouple with 470nF to ground Bias D1 TDIG2 Test pin Test pin for digital signals ( can be left floating or route to an input pin of the FPGA )for digital signals Digital output D2 OUTCTR_P LVDS positive control output channel LVDS output D3 TDIG1 Test pin for digital signals ( can be left floating or route to an input pin of the FPGA ) Digital output D16 CMDP decouple with 470nF to VDD33 Bias D17 CMDP_INV decouple with 470nF to VDD33 Bias D18 CMD_ADC decouple with 470nF to VDD33 Bias E1 Extra1 Leave floating

Reference:CMV20000-datasheet-v2.3 CMV20000 Datasheet Page 41 of 47 © 2015 CMOSIS bvba Pin number Pin name Description Type E2 Extra2 Connect to GND E3 FRAME_REQ Frame request Digital input E16 VBGAP decouple with 470nF to VBGAP_LOW Bias E17 VBGAP_LOW decouple to VBGAP see pin E16 Bias E18 CMD_COL_LOAD decouple with 470nF to ground Bias F1 STRB_EXP1 Output strobe pin for the exposure time Digital output F2 VDD20 2.1V supply Supply F3 GND Ground pin Ground F16 GND Ground pin Ground F17 VDD20 2.1V supply Supply F18 REF_ADC Ref for ADC testing (decouple with 470nF to ground) Bias G1 VDDPIX 2.3V -> 3.3V DEFAULT 2.8V supply Supply G2 GND Ground pin Ground G3 VDD33 3.3V supply Supply G16 VDD33 3.3V supply Supply G17 GND Ground pin Ground G18 VDDPIX 2.3V -> 3.3V DEFAULT 2.8V supply Supply H1 Extra6 Connect to GND H2 T_EXP1 Input pin for external exposure mode Digital input H3 GND Ground pin Ground H16 GND Ground pin Ground H17 VREF Ref for column amps (decouple with 470nF to ground) Bias H18 CMD_RAMP decouple with 470nF to VDD33 Bias J1 PLL_REF decouple with 470nF to PLL_REF_LOW Bias J2 PLL_REF_LOW decouple to PLL_REF see pin J1 Bias J3 GND Ground pin Ground J16 GND Ground pin Ground J17 VRAMP2 Start voltage second ramp (decouple with 470nF to ground) Bias J18 VRAMP1 Start voltage first ramp (decouple with 470nF to ground) Bias K1 VDDPIX 2.3V -> 3.3V DEFAULT 2.8V supply Supply K2 GND Ground pin Ground K3 VDD33 3.3V supply Supply K16 VDD33 3.3V supply Supply K17 GND Ground pin Ground K18 VDDPIX 2.3V -> 3.3V DEFAULT 2.8V supply Supply L1 LVDS_CLK_P LVDS input clock P LVDS input L2 VDD20 2.1V supply Supply L3 GND Ground pin Ground L16 GND Ground pin Ground L17 VDD20 2.1V supply Supply L18 SIG_ADC Sig for ADC testing (decouple with 470nF to ground) Bias M1 LVDS_CLK_N LVDS input clock N LVDS input M2 CLK_IN Master input clock Digital input M3 SYS_RES_N Input pin for sequencer reset Digital input M16 VTF_LOW3 Transfer low voltage 3 (decouple with 470nF to ground) Bias M17 VTF_LOW2 Transfer low voltage 2 (decouple with 470nF to ground) Bias M18 VTF_LOW1 Transfer low voltage 1 (decouple with 470nF to ground) Bias N1 Extra3 Connect to GND N2 OUTCLK_P LVDS positive clock output channel LVDS output N3 Extra4 connect to GND N16 VRES_L Res low voltage (decouple with 470nF to ground) Bias N17 VRES_H 3.3V supply or highest supply voltage Supply

Reference:CMV20000-datasheet-v2.3 CMV20000 Datasheet Page 42 of 47 © 2015 CMOSIS bvba Pin number Pin name Description Type N18 VPCH_L Precharge low voltage (decouple with 470nF to ground) Bias P1 SPI_EN SPI enable Digital input P2 OUTCLK_N LVDS negative clock output channel LVDS output P3 SPI_IN SPI data input pin Digital input P16 GND Ground pin Ground P17 GND Ground pin Ground P18 VPCH_H Precharge high voltage (decouple with 470nF to ground) Bias R1 SPI_CLK SPI clock input pin Digital input R2 OUTO1_N LVDS negative output data odd rows channel1 top LVDS output R3 GND Ground pin Ground R4 OUTO2_N LVDS negative output data odd rows channel2 top LVDS output R5 GND Ground pin Ground R6 OUTO3_N LVDS negative output data odd rows channel3 top LVDS output R7 GND Ground pin Ground R8 OUTO4_N LVDS negative output data odd rows channel4 top LVDS output R9 VDD33 3.3V supply Supply R10 OUTO5_P LVDS positive output data odd rows channel5 top LVDS output R11 GND Ground pin Ground R12 OUTO6_P LVDS positive output data odd rows channel6 top LVDS output R13 GND Ground pin Ground R14 OUTO7_P LVDS positive output data odd rows channel7 top LVDS output R15 VDD33 3.3V supply Supply R16 OUTO8_P LVDS positive output data odd rows channel8 top LVDS output R17 GND Ground pin Ground R18 SPI_OUT_RIGHT SPI data output pin at the right, this is a backup SPI data output pin. Only the spi output data of register >= address 103 are available at this pin. Should be routed to the FPGA as well Digital output T1 SPI_OUT_LEFT SPI data output pin at the left, this is the main SPI data output pin containing the SPI output data of all registers. Digital output T2 OUTO1_P LVDS positive output data odd rows channel1 top LVDS output T3 VDD20 2.1V supply Supply T4 OUTO2_P LVDS positive output data odd rows channel2 top LVDS output T5 VDD20 2.1V supply Supply T6 OUTO3_P LVDS positive output data odd rows channel3 top LVDS output T7 VDDPIX 2.3V -> 3.3V DEFAULT 2.8V supply Supply T8 OUTO4_P LVDS positive output data odd rows channel4 top LVDS output T9 GND Ground pin Ground T10 OUTO5_N LVDS negative output data odd rows channel5 top LVDS output T11 VDD20 2.1V supply Supply T12 OUTO6_N LVDS negative output data odd rows channel6 top LVDS output T13 VDDPIX 2.3V -> 3.3V DEFAULT 2.8V supply Supply T14 OUTO7_N LVDS negative output data odd rows channel7 top LVDS output T15 GND Ground pin Ground T16 OUTO8_N LVDS negative output data odd rows channel8 top LVDS output T17 VDD20 2.1V supply Supply T18 Extra5 connect to GND

9 SPECIFICATION OVERVIE W

Specification Value Comment Effective pixels 5120 x 3840 Pixel pitch 6.4 x 6.4 µm2 Imager size 32.77x24.58m m2 Full well charge 15 Ke- Pinned photodiode pixel. Conversion gain 0.25 DN/e- At recommended settings Temporal noise (analog domain) 8 e- Pipelined global shutter (GS) with correlated double sampling ( CDS ) Dynamic range 66 dB Pixel type Global shutter pixel Allows fixed pattern noise correction and reset (kTC) noise canceling through correlated double sampling. Shutter type Pipelined global shutter Exposure of next image during readout of the previous image. Parasitic light sensitivity - Shutter efficiency 1/50 000 Color filters Optional RGB Bayer Micro lenses Yes QE * FF 60.00% @ 550 nm with micro lenses. Dark current signal 125e/s @ RT DSNU 10e/s Fixed pattern noise (RMS) <0.2% full swing PRNU (RMS) 1% LVDS Output channel Each data output running @ 480 Mbit/s. 8 outputs selectable at half frame rate Frame rate 30 frames/s Using a 12bit/pixel and 480 Mbit/s LVDS. Higher frame rate possible in row windowing mode. Timing generation On-chip Possibility to control exposure time through external pin. PGA Yes 4 analog gain settings Programmable Registers Sensor parameters Window coordinates, Timing parameters, Gain & offset, Exposure time, flipped readout in x and y direction … Supported HDR modes Multi-slope Multiple slopes with partial reset of the pixel. ADC 12bit Column ADC Interface LVDS Serial output data + synchronization signals I/O logic levels LVDS = 2.1V Logic levels = 3.3V Supply voltages 2.1 & 3.3 V 3.3V for the pixel array and analog circuits 2.1V for digital circuits and the LVDS drivers Clock inputs 40MHz CLK_IN 480MHz LVDS_CLK_N/P Power 1100 mW Package Ceramic package Custom ceramic PGA ( 143 pins ) Operating range -20C to +70C Dark current and noise performance will degrade at higher temperature Cover glass 2 sides ARC

10 ORDERING INFO

Part Number Chroma Microlens Package Glass CMV20000-1E5M1PA Mono yes Ceramic PGA AR coated CMV20000-1E5C1PA RGB Bayer yes Ceramic PGA AR coated On request the package and cover glass can be customized. For options, pricing and delivery time please contact info@cmosis.com.

11 HANDLING AND SOLDERING P ROCEDURE

11.1 SOLDERING

11.1.1 WAVE SOLDERING

Wave soldering is possible but not recommended. Solder dipping can cause damage to the glass and harm the imaging capability of the device. See the figure below for the wave soldering profile. Temperature (C) Time (s) 260 Max 10 s

11.1.2 REFLOW SOLDERING

The figure below shows the maximum recommended thermal profile for a reflow soldering system. If the temperature/time profile exceeds these recommendations, damage to the image sensor can occur. Temperature (C) Time (s) 150 200 220 250 Maximum 6 min 60 to 180 seconds 60 to 80 seconds 10 to 20 sec

11.1.3 SOLDERING RECOMMENDAT IONS

Image sensors with color filter arrays (CFA) and micro-lenses are especially sensitive to high temperatures. Prolonged heating at elevated temperatures may result in deterioration of the performance of the sensor. Best solution will be

Reference:CMV20000-datasheet-v2.3 CMV20000 Datasheet Page 46 of 47 © 2015 CMOSIS bvba flow soldering or manual soldering of a socket (through hole or BGA) and plug in the sensor at latest stag e of the assembly/test process.

11.2 HANDLING IMAGE SENSOR S

General application note AN03 contains more details and procedures.

11.2.1 ESD

The following are the recommended minimum ESD requirements when handling image sensors. 1. Ground workspace (tables, floors…) 2. Ground handling personnel (wrist straps, special footwear…) 3. Minimize static charging (control humidity, use ionized air, wear gloves…)

11.2.2 GLASS CLEANING

When cleaning of the cover glass is needed we recommend the following two methods. 1. Blowing off the particles with ionized nitrogen 2. Wipe clean using IPA (isopropyl alcohol) and ESD protective wipes.

11.2.3 IMAGE SENSOR STORING

Image sensors should be stored under the following conditions 1. Dust free 2. Temperature 20°C to 40°C 3. Humidity between 30% and 60%. 4. Avoid radiation, electromagnetic fields, ESD, mechanical stress

11.2.4 EXCESSIVE LIGHT

Excessive light falling on the sensor can cause heating up the micro lenses and color filters. This heat can cause deforming of the lenses and/or deterioration of the lenses and color filters by making them more opaque, increasing the heat up even more. Av oid shining high intensity light upon the sensors for extended periods of time. In case of lasers, they can cause heat up but can also damage the silicon die itself.

12 ADDITIONAL I NFORMATION

For any additional question s related to the operation an d specification of the CMV 20000 imagers or feedback with respect to the present data sheet please contact techsupport@cmosis.com.

Product Information

CMV20000 specifications and overview.

Summary

20 Megapixel global shutter CMOS image sensor

Description

20 Megapixel global shutter CMOS image sensor

Source title CMV20000 Datasheet(PDF) - ams AG

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