CMP1617BAX-E

CMP1617BAX-E FIDELIX | Alldatasheet

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Technical content

Revision 0.5 Jul. 2006 Document Title 1M x 16 bit Super Low Power and Low Voltage Full CMOS RAM

Revision History

FinalNov. 1st, 2005Added G(Pb-Free) and H(Pb-Free & Halogen Free) descriptions0.4 FinalNov. 8th, 2004Modified functional description & MRS update timing Minor Changes0.3 FinalJul. 25th, 2006Add AC Parameter (tCP)0.5 FinalSep. 21th, 2004Change speed from 60nsec to 55nsec Modify ISB1, PASR Current0.2 PreliminaryMar. 15th, 2004 Add Direct DPD Modify MRS Entry Modify PASR Current 0.1 PreliminaryDec. 22nd, 2003Initial Draft0.0 RemarkDraft dateHistoryRevision No.

Revision 0.5 Jul. 2006 1M x 16 bit Super Low Power and Low Voltage Full CMOS RAM PIN DESCRIPTION 1 2 3 4 5 6 A B C D E F G H /LB /OE A0 A1 A2 I/O9 /UB A3 A4 /CS I/O10 I/O11 A5 A6 I/O2 VSS I/O12 A17 A7 I/O4 VCCQ I/O13 DNU A16 I/O5 I/O15 I/O14 A14 A15 I/O6 I/O16 A19 A12 A13 WE A 1 8A 8A 9A 1 0 A 1 1 /ZZ I/O1 I/O3 VCC VSS I/O7 I/O8 NC 48-FBGA : Top View(Ball Down) Do Not Use DNUData Inputs/OutputsI/O1~I/O16 Core PowerVCCLow Power Modes/ZZ No ConnectionNC Lower Byte(I/O 1~8)/LBAddress InputsA0~A19 Upper Byte(I/O9~16)/UBWrite Enable Input/WE GroundVSSOutput Enable Input/OE I/O PowerVCCQChip Select Input/CS FunctionNameFunctionName FUNCTIONAL BLOCK DIAGRAM Precharge circuit.Clk gen. VCC VSS Memory arrayRow Addresses I/O Circuit Column select Data cont Data cont Column Addresses Data cont Control Logic /CS /OE /WE /UB /LB /ZZ I/O9~I/O16 I/O1~I/O8 Row select

FEATURES

• Process Technology : Full CMOS
• Organization : 1M x 16
• Power Supply Voltage : 2.7~3.3V
• Low Power & Page Modes CMP1617BX1 : support the PASR/MRS DPD function CMP1617BX2 : support the Direct DPD function CMP1617BX4 : support the PASR/MRS DPD/PAGE function CMP1617BX5 : support the Direct DPD/PAGE function
• Three state output and TTL Compatible
• Package Type : 48-FBGA-6.00x8.00 mm2
• Separated I/O power(VCCQ) & Core Power(VCC)
• Page read/write operation by 16 words (CMP1617BA4, CMP1617BA5)
• DPD mode by using MRS only (CMP1617BA1, CMP1617BA4)
• Direct DPD mode when /ZZ goes low (CMP1617BA2, CMP1617BA5) PRODUCT FAMILY ISB1 (CMOS Standby Current) ICC2 ICC1 Max.Typ. 25mA Max.Typ. Max.Typ.Min. 100uA3.0 Typ.Max. 50uA15mA 12mA3mA1.5mA60ns 70ns3.32.7Extended (-25~85’C) CMP1617BAx-F60E CMP1617BAx-F70E Operating Voltage (V) f = fmaxf = 1MHz Power Dissipation SpeedOperating TemperatureProduct Family 1. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at Vcc = Vcc ( typ) and TA = 25C. 2. F=FBGA, G=FBGA(Pb-Free), H=FBGA(Pb-Free & Halogen Free), W=WAFER

Revision 0.5 Jul. 2006 PRODUCT LIST 48-FBGA, 60ns, VCC=3.0V, VCCQ=3.0V(2.5V,1.8V) 48-FBGA, 70ns, VCC=3.0V, VCCQ=3.0V(2.5V,1.8V) CMP1617BAx-F60E CMP1617BAx-F70E FunctionPart Name Extended Temperature Products(-25~85’C) ABSOLUTE MAXIMUM RATINGS1) ’C-25 to 85TAOperating Temperature ’C-65 to 150TSTGStorage temperature W1.0PDPower Dissipation V-0.2 to 3.6VccVoltage on Vcc supply relative to Vss V-0.2 to Vcc+0.3VVIN, VOUTVoltage on any pin relative to Vss UnitRatingsSymbolItem 1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause perm anent damage to the device. Functional operation s hould be restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability. FUNCTIONAL DESCRIPTION Direct DPD2)DeselectedHigh-ZHigh-ZX1)X1)X1)X1)LX1) ActiveWord WriteDinDinL L ActiveUpper Byte WriteDinHigh-ZLH ActiveLower Byte WriteHigh-ZDinHL LX1) ActiveWord ReadDoutDoutLL ActiveUpper Byte ReadDoutHigh-ZLH ActiveLower Byte ReadHigh-ZDoutHL HL HL ActiveOutput DisabledHigh-ZHigh-ZLX1)HHH ActiveOutput DisabledHigh-ZHigh-ZX1)LHHH L StandbyDeselectedHigh-ZHigh-ZHHX1)X1)HX1) Low Power Modes3)DeselectedHigh-ZHigh-ZX1)X1)X1)X1)LH StandbyDeselectedHigh-ZHigh-ZX1)X1)X1)X1)HH PowerModeI/O9-16I/O1-8/UB/LB/WE/OE/ZZ/CS 1. X means don’t care.(Must be low or high state) 2. In case of CMP1617BA2 & CMP1617BA5 product 3. In case of CMP1617BA1 & CMP1617BA4 product RECOMMENDED DC OPERATING CONDITIONS1) -0.23) 0.8VCCQ 2.7 2.7 Min CMP1617BA 0.2VCCQ VCC+0.22) 3.3 3.3 Max -0.23) 0.8VCCQ 2.25 2.7 Min 0.2VCCQ VCC+0.22) 2.75 3.3 Max 1.95 V3.32.7VCCSupply voltage 0.2VCCQ VCC+0.22) Max V-0.23)VILInput low voltage V0.8VCCQVIHInput high voltage V0VSSGround V1.65VCCQI/O operating voltage (VCCQ ≤ VCC) Unit Min SymbolItem Note : 1.TA=-25 to 85’C, otherwise specified. 2. Overshoot : Vcc+1.0V in case of pulse width≤20ns. 3. Undershoot : -1.0V in case of pulse width≤20ns. 4. Overshoot and undershoot are sampled, not 100% tested. 1. F=FBGA, G=FBGA(Pb-Free), H=FBGA(Pb-Free & Halogen Free), W=WAFER

Revision 0.5 Jul. 2006 DC AND OPERATING CHARACTERISTICS 1. Capacitance is sampled, not 100% tested. CAPACITANCE1) (f=1MHz , TA=25’C) Max Min pFVIO=0VCIOInput/Output capacitance pFVIN=0VCINInput capacitance UnitTest ConditionSymbolItem uA10--/ZZ≤0.2V, Other inputs=0~VCC, No refresh(DPD)ISB0 Low Power Modes uA55--/ZZ≤0.2V, Other inputs=0~VCC, ¼ refresh area selectionISB0a uA70--/ZZ≤0.2V, Other inputs=0~VCC, ½ refresh area selectionISB0b uA100--/CS≥VCC-0.2V, /ZZ≥VCC-0.2V, Other inputs=0~VCCISB1Standby Current(CMOS) uA1--1/CS=VIH, /ZZ=VIH, /OE=VIH or /WE=VIL, VIO=VSS to VCCILOOutput leakage current uA1--1VIN=VSS to VCCILIInput leakage current mA3--Cycle time=1us, 100%duty, IIO=0mA, /CS≤0.2V, /ZZ=VIH, VIN≤0.2V or VIN≥VCC-0.2VICC1 Average operating current V0.2VCCQIOL=0.5mAVOLOutput low voltage mA25--Cycle time=Min, IIO=0mA, 100% duty, /CS=VIL, /ZZ=VIH, VIN=VIL or VIHICC2 V0.8VCCQIOH=-0.5mAVOHOutput high voltage 100 0.3 Max Typ Min uA/ZZ≤0.2V, Other inputs=0~VCC, All refresh area selectionISB0c mA/CS=VIH, /ZZ=VIH, Other inputs=VIH or VILISBStandby Current(TTL) UnitTest ConditionsSymbolItem

Revision 0.5 Jul. 2006 AC OPERATING CONDITIONS TEST CONDITIONS(Test Load and Input/Output Reference) Input pulse level : 0.2 to VCC-0.2V Input rising and falling time : 5ns Input and output reference voltage : 0.5*VCCQ Output load(see right) : CL=30pF+1TTL AC CHARACTERISTICS(VCC=2.7V~3.3V, Extended product : TA=-25 to 85’C) 30pf 1TTL ns40k-40k-tMRCMaximum Cycle Time Page ns-10-10tCP ns25-25-tPAAPage Mode Address Access Time ns-25-25tPCPage Mode Cycle Time /CS High Pulse Width ns-5-5tOWEnd Write to Output Low-Z ns-0-0tDHData Hold from Write Time ns-20-20tDWData to Write Time Overlap ns5050tWHZWrite to Output High-Z ns-0-0tWRWrite Recovery Time ns-50-50tWPWrite Pulse Width ns-60-50tBW/UB, /LB Valid to End of Write ns-60-50tAWAddress Valid to End of Write ns-0-0tASAddress Set-up Time ns-60-50tCWChip Select to End of Write ns40k7040k60tWCWrite Cycle Time Write ns-5-5tOHOutput Hold from Address Change ns5050tOHZOutput Disable to High- Z Output ns5050tBHZ/UB, /LB Disable to High- Z Output ns5050tHZChip Disable to High- Z Output ns-5-5tOLZOutput Enable to Low-Z Output 70ns ns-10-10tBLZ/UB, /LB Enable to Low-Z Output ns-10-10tLZChip Select to Low-Z Output ns70-60-tBA/UB, /LB Access Time ns25-25-tOEOutput Enable to Valid Output ns70-60-tCOChip Select to Output ns70-60-tAAAddress Access Time ns40k7040k60tRCRead Cycle Time Read MaxMinMaxMin 60ns Units Speed Bins SymbolParameter List 1. /CS High Pulse Width is defined by /CS or (/UB and /LB) because /UB & /LB can make standby mode when /UB=High and /LB=High.

Revision 0.5 Jul. 2006 Power Up Sequence 1. Apply Power 2. Maintain stable power for a minimum of 200us with /CS=V IH Standby Mode State machines Standby Mode Characteristics 055 (ISB0a)¼ valid 070 (ISB0b)½ valid 20010 (ISB0)Invalid Low Power Modes 0100 (ISB0c)valid 0100 (ISB1)ValidStandby Mode Memory Cell Data Wait Time(us)Standby Current(uA) Initial State Standby Mode Active Mode Low Power Modes 1 (16M/8M/4M bits) Power On /CS=VIL /ZZ=VIH /CS=VIH (or/and /UB=/LB=VIH) /ZZ=VIH /CS=VIH /CS=VIH, /ZZ=VIL /CS=VIL, /ZZ=VIH /UB or/and /LB=VIL Low Power Modes 2 (Data Invalid) Wait 200us /CS=VIH, /ZZ=VIL /CS=VIH, /ZZ=VIL /CS=VIH /ZZ=VIL /CS=VIlL /ZZ=VIH /CS=VIH, /ZZ=VIH

Revision 0.5 Jul. 2006 READ CYCLE (2) (/ZZ=/WE=VIH) 1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device interconnection. 3. Do not access device with cycle timing shorter than tRC(tWC) for continuous periods > 40us. Address tAA tCO tBA tOE tOH tOLZ tBLZ tLZ Data ValidHigh-Z tHZ tBHZ tOHZ /CS /UB, /LB /OE Data Out tRC READ CYCLE (1) (Address controlled,/CS=/OE=VIL, /ZZ=/WE=VIH, /UB or/and /LB=VIL) Address Data Out tRC Previous Data Valid Data Valid tAA tOH 1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device interconnection. 3. Do not access device with cycle timing shorter than tRC(tWC) for continuous periods > 40us. PAGE READ CYCLE (/ZZ=/WE=VIH, 16 words access) A0~A3 tAA tCO tBA tOE High-Z tHZ tBHZ tOHZ /CS /UB, /LB /OE Data Out tRC A4~A20 tOH tPC tPC tPC tPC tPC tPC tPC tPAA tPAA tPAA tPAA tPAA tPAA tPAA tLZ tBLZ tOLZ Data Valid Data Valid Data Valid Data Valid Data Valid Data Valid Data Valid Data Valid tMRC

Revision 0.5 Jul. 2006 WRITE CYCLE (2) (/CS controlled, /ZZ=/WE=VIH) Address /CS /UB, /LB /WE Data Out tWC tWR(4) tBW tWP(1) High-Z High-Z Data Valid tDW tDH Data in tCW(2)tAS(3) tAW WRITE CYCLE (3) (/UB, /LB controlled, /ZZ=VIH) 1. A write occurs during the overlap (tWP) of low /CS and /WE. A write begins when /CS goes low and /WE goes low with asserting /UB or /LB for single byte operation or simultaneously asserting /UB and /LB for double byte operation. A write ends at the earliest transition when /CS goes high and WE goes high. The tWP is measured from the beginning of write to the end of write. 2. tCW is measured from the /CS going low to end of write. 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end of write to the address change. tWR applied in case a write ends as /CS or /WE going high. 5. Do not access device with cycle timing shorter than tRC(tWC) for continuous periods > 40us. Address /CS /UB, /LB /WE Data Out tWC tWR(4) tBW tWP(1) High-Z High-Z Data Valid tDW tDH Data in tCW(2) tAW tAS(3) WRITE CYCLE (1) (/WE controlled, /ZZ=VIH) Address /CS /UB, /LB /WE Data Out tWC tCW(2) tWR(4) tAW tBW tWP(1) tAS(3) High-Z High-Z Data Undefined Data Valid tDW tDH tOWtWHZ Data in

Revision 0.5 Jul. 2006 1. A write occurs during the overlap (tWP) of low /CS and /WE. A write begins when /CS goes low and /WE goes low with asserting /UB or /LB for single byte operation or simultaneously asserting /UB and /LB for double byte operation. A write ends at the earliest transition when /CS goes high and /WE goes high. The tWP is measured from the beginning of write to the end of write. 2. tCW is measured from the /CS going low to end of write. 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end of write to the address change. tWR applied in case a write ends as /CS or /WE going high. 5. Do not access device with cycle timing shorter than tRC(tWC) for continuous periods > 40us. PAGE WRITE CYCLE (Address controlled, /ZZ=VIH) A4~A20 /CS /UB, /LB /WE Data Out tAS(3) High-Z Data Undefined Data Valid tDW tOW tWHZ Data in A0~A3 tWC tPC tPC tPC tPC tPC tPC tPC High-Z tDH Data Valid tDH tDW tDH tDW tDH tDW tDH tDW tDH tDW tDH tDW tDH tDW Data Valid Data Valid Data Valid Data Valid Data Valid Data Valid tMRC

Revision 0.5 Jul. 2006 LOW POWER MODES 1. Mode Register Set A0A1A2A3A4A19 ~ A5 Array Refresh AreaHalf SelectionArray On/Off on /ZZ ZZ Enable/Disable0 /ZZ Enable/Disable DPD Disable (Default)1 Deep Power Down Enable0 TypeA4 Array On/Off on /ZZ Reduced Memory Size Mode1 Partial Array Refresh Mode (Default)0 TypeA3 Note: If the register is written to enable the Deep Power Down, the part will go into Deep Power Down during the following time that /ZZ is driven low and there is no MRS update. When /ZZ is driven high, all of the register settings will return to default state for the part (i.e. full array refresh, Deep Power Down Disabled). Note: The RMS(Reduced Memory Size) mode is enabled after /ZZ goes high and remains enabled after /ZZ goes high. To change to a different mode, the mode register will have to be rewritten.Half Selection (Top / Bottom) Top1 Bottom (Default)0 TypeA2 Array Refresh Area RFU10 ½ Array01 ¼ Array1 Full Array (Default)0 TypeA0 2. MRS Update Address /CS /UB, /LB /WE tWC tWR(4) tBW tWP(1) tCW(2)tAS(3) tAW /ZZ tZZWE Register Write Start Register Write Complete Register Update Complete The register update take place on the rising edge of /ZZ. Once the register is updated, the next time /ZZ goes low, without an y updates to the register starting within the tZZWE max time of 1us, the part will refresh the array selected. The data bus is a don’t care When /ZZ is low during the register updates.

Revision 0.5 Jul. 2006 8Mb512Kbx1680000h-FFFFFh1/2101 4Mb256Kbx16C0000h-FFFFFh1/4111 16Mb1Mbx1600000h-FFFFFhFull00X 8Mb512Kbx1600000h-7FFFFh1/2100 4Mb256Kbx1600000h-3FFFFh1/4110 DensitySizeAddressRefresh SectionA1,A0A2 Partial Array Refresh Mode (A3=0, A4=1) Reduced Memory Size Mode (A3=1, A4=1) 3. Deep Power Down Mode Entry/Exit 4. Address Information tZZmin tR /CS /UB, /LB /WE tWC tWR(4 tBW tWP(1) tCW(2 tAS(3) tAW /ZZ tZZWE Register Write(DPD) Deep Power down start Deep Power down exit Next Cycle 8Mb512bx1680000h-FFFFFh 1/2101 4Mb256Kbx16C0000h-FFFFFh1/4111 8Mb512Kbx1600000h-7FFFFh 1/2100 4Mb256Kbx1600000h-3FFFFh 1/4110 DensitySizeAddressRefresh SectionA1,A0A2 us-10Low Power Mode TimetZZmin us-200Operation Recovery TimetR(Deep Power Down Mode only) us10ZZ low to Write Enable LowtZZWE UnitsMaxMinDescriptionParameter

Revision 0.5 Jul. 2006 PACKAGE DIMENSION 48 BALL FINE PITCH BGA(0.75mm ball pitch) Top View B C #A1 Bottom View Side View Detail A Unit : millimeters 0.08--Y 0.300.250.20E2 -0.85-E1 1.201.10-E 0.400.350.30D -5.25-C1 8.108.007.90C -3.75-B1 6.106.005.90B -0.75-A MaxTypMin- D C E 0.30 0.85/Typ. 0.25/Typ. Y NOTES. 1. Bump counts : 48(8row x 6column) 2. Bump pitch : (x,y)=(0.75 x 0.75)(typ.) 3. All tolerance are +/-0.050 unless otherwise specified. 4. Typ : Typical 5. Y is coplanarity : 0.08(Max) B C B/2 B1 0.05 0.05 A1 INDEX MARK 6 5 4 3 2 1 A B C D C1/2 E F G H A