CMP0817BA0-I FIDELIX | Alldatasheet

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Technical content

Revision 0.3 Sep. 2006 Document Title 512K x 16 bit Super Low Power and Low Voltage Full CMOS RAM

Revision History

FinalAug. 22nd, 2006Removed 60ns descriptions0.2 FinalSep. 6th, 2006Added Power Up Sequence0.3 FinalOct. 26th, 2005Added G(Pb-Free) and H(Pb-Free & Halogen Free) descriptions0.1 FinalMay. 2nd, 2004Initial Draft0.0 RemarkDraft dateHistoryRevision No.

Revision 0.3 Sep. 2006 512K x 16 bit Super Low Power and Low Voltage Full CMOS RAM PIN DESCRIPTION 1 2 3 4 5 6 A B C D E F G H /LB /OE A0 A1 A2 I/O9 /UB A3 A4 /CS I/O10 I/O11 A5 A6 I/O2 VSS I/O12 A17 A7 I/O4 VCCQ I/O13 DNU A16 I/O5 I/O15 I/O14 A14 A15 I/O6 I/O16 NC A12 A13 /WE A 1 8A 8A 9A 1 0 A 1 1 CS2 I/O1 I/O3 VCC VSS I/O7 I/O8 NC 48-FBGA : Top View(Ball Down) Do Not Use DNUData Inputs/OutputsI/O1~I/O16 Core PowerVCCChip Select InputCS2 No ConnectionNC Lower Byte(I/O 1~8)/LBAddress InputsA0~A18 Upper Byte(I/O9~16)/UBWrite Enable Input/WE GroundVSSOutput Enable Input/OE I/O PowerVCCQChip Select Input/CS1 FunctionNameFunctionName

FEATURES

  • Process Technology : Full CMOS
  • Organization : 512K x 16
  • Power Supply Voltage : 2.7~3.3V
  • Three state output and TTL Compatible
  • Package Type : 48-FBGA-6.00x8.00 mm2
  • Separated I/O power(VCCQ) & Core Power(VCC)
  • Easy memory expansion with /CS1, CS2, and /OE features
  • Automatic power-down when deselected PRODUCT FAMILY ISB1 (CMOS Standby Current) ICC2 ICC1 Max.Typ. 20mA Max.Typ. Max.Typ.Min. 70uA3.0 Typ.Max. 30uA12mA3mA1.5mA70ns3.32.7Industrial (-40~85’C)CMP0817BA0-F70I Operating Voltage (V) f = fmaxf = 1MHz Power Dissipation SpeedOperating TemperatureProduct Family FUNCTIONAL BLOCK DIAGRAM Precharge circuit.Clk gen. VCC VSS Memory arrayRow Addresses I/O Circuit Column select Data cont Data cont Column Addresses Data cont Control Logic /CS1 CS2 /OE /WE /UB /LB I/O9~I/O16 I/O1~I/O8 Row select 1. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at Vcc = Vcc ( typ) and TA = 25C. 2. F=FBGA, G=FBGA(Pb-Free), H=FBGA(Pb-Free & Halogen Free), W=WAFER

Revision 0.3 Sep. 2006 PRODUCT LIST 48-FBGA, 70ns, VCC=3.0V, VCCQ=3.0V(2.5V,1.8V)CMP0817BA0-F70I FunctionPart Name Industrial Temperature Products(-40~85’C) FUNCTIONAL DESCRIPTION ActiveWord WriteDinDinL L ActiveUpper Byte WriteDinHigh-ZLH ActiveLower Byte WriteHigh-ZDinHL LX1) ActiveWord ReadDoutDoutLL ActiveUpper Byte ReadDoutHigh-ZLH ActiveLower Byte ReadHigh-ZDoutHL HL HL ActiveOutput DisabledHigh-ZHigh-ZLX1)HHH ActiveOutput DisabledHigh-ZHigh-ZX1)LHHH L StandbyDeselect/Power-downHigh-ZHigh-ZHHX1)X1)HX1) StandbyDeselect/Power-downHigh-ZHigh-ZX1)X1)X1)X1)LX1) StandbyDeselect/Power-downHigh-ZHigh-ZX1)X1)X1)X1)HH PowerModeI/O9-16I/O1-8/UB/LB/WE/OECS2/CS1 1. X means don’t care.(Must be low or high state) ABSOLUTE MAXIMUM RATINGS1) ’C-40 to 85TAOperating Temperature ’C-65 to 150TSTGStorage temperature W1.0PDPower Dissipation V-0.2 to 3.6VccVoltage on Vcc supply relative to Vss V-0.2 to Vcc+0.3VVIN, VOUTVoltage on any pin relative to Vss UnitRatingsSymbolItem 1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause perm anent damage to the device. Functional operation should be restricted to recommended operating condition. Exposure to absolute maximum rating conditions for Industria l periods may affect reliability. RECOMMENDED DC OPERATING CONDITIONS1) -0.23) 0.8VCCQ 2.7 2.7 Min CMP0817BA0 0.2VCCQ VCC+0.22) 3.3 3.3 Max -0.23) 0.8VCCQ 2.25 2.7 Min 0.2VCCQ VCC+0.22) 2.75 3.3 Max 1.95 V3.32.7VCCSupply voltage 0.2VCCQ VCC+0.22) Max V-0.23)VILInput low voltage V0.8VCCQVIHInput high voltage V0VSSGround V1.65VCCQI/O operating voltage (VCCQ ≤ VCC) Unit Min SymbolItem Note : 1.TA=-40 to 85’C, otherwise specified. 2. Overshoot : Vcc+1.0V in case of pulse width≤20ns. 3. Undershoot : -1.0V in case of pulse width≤20ns. 4. Overshoot and undershoot are sampled, not 100% tested. 1. F=FBGA, G=FBGA(Pb-Free), H=FBGA(Pb-Free & Halogen Free), W=WAFER

Revision 0.3 Sep. 2006 DC AND OPERATING CHARACTERISTICS 1. Capacitance is sampled, not 100% tested. CAPACITANCE1) (f=1MHz , TA=25’C) Max Min pFVIO=0VCIOInput/Output capacitance pFVIN=0VCINInput capacitance UnitTest ConditionSymbolItem uA70--/CS≥VCC-0.2V, CS2≤0.2V, Other inputs=0~VCCISB1Standby Current(CMOS) uA1--1/CS=VIH, CS2=VIH, /OE=VIH or /WE=VIL, VIO=VSS to VCCILOOutput leakage current uA1--1VIN=VSS to VCCILIInput leakage current mA31.5-Cycle time=1us, 100%duty, IIO=0mA, /CS≤0.2V, CS2=VIH, VIN≤0.2V or VIN≥VCC-0.2VICC1 Average operating current V0.2VCCQIOL=0.5mAVOLOutput low voltage mA2515-Cycle time=Min, IIO=0mA, 100% duty, /CS=VIL, CS2=VIH, VIN=VIL or VIHICC2 V0.8VCCQIOH=-0.5mAVOHOutput high voltage 0.3 Max Typ Min mA/CS=VIH, CS2=VIH, Other inputs=VIH or VILISBStandby Current(TTL) UnitTest ConditionsSymbolItem

Revision 0.3 Sep. 2006 AC OPERATING CONDITIONS TEST CONDITIONS(Test Load and Input/Output Reference) Input pulse level : 0.2 to VCC-0.2V Input rising and falling time : 5ns Input and output reference voltage : 0.5*VCCQ Output load(see right) : CL=30pF+1TTL AC CHARACTERISTICS(VCC=2.7V~3.3V, Industrial product : TA=-40 to 85’C) 30pf 1TTL 1. /CS High Pulse Width is defined by /CS or (/UB and /LB) because /UB & /LB can make standby mode when /UB=High and /LB=High. ns-10tCP/CS High Pulse Width1) ns-5tOWEnd Write to Output Low-Z ns-0tDHData Hold from Write Time ns-20tDWData to Write Time Overlap ns50tWHZWrite to Output High-Z ns-0tWRWrite Recovery Time ns-50tWPWrite Pulse Width ns-60tBW/UB, /LB Valid to End of Write ns-60tAWAddress Valid to End of Write ns-0tASAddress Set-up Time ns-60tCWChip Select to End of Write ns80k70tWCWrite Cycle Time Write ns-5tOHOutput Hold from Address Change ns50tOHZOutput Disable to High- Z Output ns50tBHZ/UB, /LB Disable to High- Z Output ns50tHZChip Disable to High- Z Output ns-5tOLZOutput Enable to Low-Z Output 70ns ns-10tBLZ/UB, /LB Enable to Low-Z Output ns-10tLZChip Select to Low-Z Output ns70-tBA/UB, /LB Access Time ns25-tOEOutput Enable to Valid Output ns70-tCOChip Select to Output ns70-tAAAddress Access Time ns80k70tRCRead Cycle Time Read MaxMin UnitsSymbolParameter List

Revision 0.3 Sep. 2006 Power Up Sequence 1. Apply Power 2. Maintain stable power for a minimum of 200us with /CS=V IH Standby Mode State machines Standby Mode Characteristics Initial State Standby Mode Active Mode Power On /CS=VIlL /ZZ=VIH /CS=VIH (or/and /UB=/LB=VIH) /ZZ=VIH /CS=VIH /CS=VIL, /ZZ=VIH /UB or/and /LB=VIL Wait min.200us 070 (ISB1)ValidStandby Mode Memory Cell Data Wait Time(us)Standby Current(uA)

Revision 0.3 Sep. 2006 READ CYCLE (1) (Address controlled,/CS1=/OE=VIL, CS2=/WE=VIH, /UB or/and /LB=VIL) Address Data Out tRC Previous Data Valid Data Valid tAA tOH READ CYCLE (2) (CS2=/WE=VIH) Address tAA tCO tOH tHZ /CS1 tRC 1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device interconnection. 3. Do not access device with cycle timing shorter than tRC(tWC) for continuous periods > 80us. tBA tOE tOLZ tBLZ tLZ Data ValidHigh-Z tBHZ tOHZ /UB, /LB /OE Data Out CS2

Revision 0.3 Sep. 2006 WRITE CYCLE (1) (/WE controlled) Address /CS1 /UB, /LB /WE Data Out tWC tCW(2) tWR(4) tAW tBW tWP(1) tAS(3) High-Z High-Z Data Undefined Data Valid tDW tDH tOWtWHZ Data in CS2 WRITE CYCLE (2) (/CS1 controlled) Address /CS1 /UB, /LB /WE Data Out tWC tWR(4) tBW tWP(1) High-Z High-Z Data Valid tDW tDH Data in tCW(2)tAS(3) tAW CS2 WRITE CYCLE (3) (CS2 controlled) Address /CS1 /UB, /LB /WE Data Out tWC tWR(4) tBW tWP(1) High-Z High-Z Data Valid tDW tDH Data in tCW(2) tAW tAS(3) CS2

Revision 0.3 Sep. 2006 1. A write occurs during the overlap (tWP) of low /CS and /WE. A write begins when /CS goes low and /WE goes low with asserting /UB or /LB for single byte operation or simultaneously asserting /UB and /LB for double byte operation. A write ends at the earliest transition when /CS goes high and /WE goes high. The tWP is measured from the beginning of write to the end of write. 2. tCW is measured from the /CS going low to end of write. 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end of write to the address change. tWR applied in case a write ends as /CS or /WE going high. 5. Do not access device with cycle timing shorter than tRC(tWC) for continuous periods > 80us. WRITE CYCLE (4) (/UB, /LB controlled) Address /CS1 /UB, /LB /WE Data Out tWC tWR(4) tBW tWP(1) High-Z High-Z Data Valid tDW tDH Data in tCW(2) tAW tAS(3) CS2

Revision 0.3 Sep. 2006 PACKAGE DIMENSION 48 BALL FINE PITCH BGA(0.75mm ball pitch) Top View B C #A1 Bottom View Side View Detail A Unit : millimeters 0.08--Y 0.300.250.20E2 -0.75-E1 -1.00-E 0.400.350.30D -5.25-C1 8.108.007.90C -3.75-B1 6.106.005.90B -0.75-A MaxTypMin- D C E 0.30 0.85/Typ. 0.25/Typ. Y NOTES. 1. Bump counts : 48(8row x 6column) 2. Bump pitch : (x,y)=(0.75 x 0.75)(typ.) 3. All tolerance are +/-0.050 unless otherwise specified. 4. Typ : Typical 5. Y is coplanarity : 0.08(Max) B C B/2 B1 0.05 0.05 A1 INDEX MARK 6 5 4 3 2 1 A B C D C1/2 E F G H A