CH7307C

CH7307C CHRONTEL | Alldatasheet

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Technical content

201-0000-062 Rev. 2.0, 06/12/2018 1 Chrontel CH7307C DVI Transmitter FEATURES GENERAL DESCRIPTION

• Digital Visual Interface (DVI) Transmitter up to 165M pixels/second
• DVI low jitter PLL
• DVI hot plug detection
• Supporting graphics resolutions up to 1600x1200 pixels and 1920x1200 (reduced blanking)
• High-speed SDVO ◊ (1G~2Gbps) AC-coupled serial differential RGB inputs
• Programmable power management
• Fully programmable through serial port
• Configuration through Intel ® Opcodes ◊
• Complete Windows and DOS driver support
• Offered in a 48-pin LQFP package
• Boundary scan support The CH7307C is a Display Controller device, which accepts digital graphics input signal, encodes and transmits data through a DVI link (DFP can also be supported). The device accepts one channel of RGB data over three pairs of serial data ports. The DVI processor includes a low jitter PLL for generation of the high frequency serialized clock, and all circuitry required encoding, serializing and transmitting the data. The CH7307C is able to drive a DFP display at a pixel rate of up to 165MHz. ◊ Intel ® Proprietary. SDVO_Clk(+/-) Serial Port Control SDVO_R(+/-) Data Latch, Serial to Parallel 10bit-8bit decoder Clock Driver SPC SPD RESET* DVI PLL DVI Encode DVI Serialize DVI Driver TLC, TLC* TDC0, TDC0* TDC1, TDC1* TDC2, TDC2* SC_PROM SD_PROM &H,V,DE FIFO interrept generation SDVO_INT(+/-) SC_DDC SD_DDC AS Reset Control SDVO_G(+/-) SDVO_B(+/-) HPDET VSWING Test Block BSCAN Figure 1: Functional Block Diagram

2 201-0000-062 Rev. 2.0, 06/12/2018 Table of Contents

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1.0 PIN -O UT

1.1 Package Diagram

Figure 2: 48-Pin LQFP Pin Out CHRONTEL CH7307C SPD SPC RESET* AVDD_PLL AGND_PLL AS DVDD SC_DDC SD_DDC SC_PROM SD_PROM DGND TLC TLC* TDC0 TDC0* TDC1 TDC1* TDC2 TDC2* TVDD TVDD TGND TGND VSWING HPDET DGND DVDD Reserved BSCAN AVDD AGND SDVO_INT+ SDVO_INT- Reserved Reserved SDVO SDVO SDVO SDVO SDVO SDVO AGND SDVO SDVO AVDD AGND AVDD _B- _B+ _G- _G+ _R- _R+ _CLK+ _CLK-

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1.2 Pin Description

Table 1: Pin Description Pin # Type Symbol Description

2 In RESET* Reset* Input (Internal pull-up)

When this pin is low, the device is held in the power-on reset condition. When this pin is high, reset is controlled through the serial port register.

3 In AS Address Select (Internal pull-up)

This pin determines the serial port address of the device (0,1,1,1,0,0,AS*,0). When AS is low the address is 72h, when high the address is 70h.

4 In/Out SPC Serial Port Clock Input

This pin functions as the clock input/output of the serial port and operates with inputs from 0 to 2.5V. This pin requires an external 4k Ω - 9k Ω pull-up resistor to 2.5V.

5 In/Out SPD Serial Port Data Input / Output

This pin functions as the bi-directional data pin of the serial port and operates with inputs from 0 to 2.5V. Outputs are driven from 0 to 2.5V. This pin requires an external 4k Ω - 9 k Ω pull-up resistor to 2.5V.

8 In/Out SD_PROM Routed Serial Port Data to PROM

This pin functions as the bi-directional data pin of the serial port for PROM on ADD2 card. This pin will require a pull-up resistor to the desired high state voltage. Leave open if unused.

9 In/Out SC_PROM Routed Serial Port Clock Output to PROM

This pin functions as the clock bus of the serial port to PROM on ADD2 card. This pin will require a pull-up resistor to the desired high state voltage. Leave open if unused.

10 In/Out SD_DDC Routed Serial Port Data to DDC

This pin functions as the bi-directional data pin of the serial port to DDC receiver. This pin will require a pull-up resistor to the desired high state voltage. Leave open if unused.

11 In/Out SC_DDC Routed Serial Port Clock Output to DDC

This pin functions as the clock bus of the serial port to DDC receiver. This pin will require a pull-up resistor to the desired high state voltage. Leave open if unused. 13, 14 Out TLC*, TLC DVI Clock Outputs These pins provide the differential clock output for the DVI interface corresponding to data on the TDC [2:0] outputs. 16,17 Out TDC0*, TDC0 DVI Data Channel 0 Outputs These pins provide the DVI differential outputs for data channel 0 (blue). 19, 20 Out TDC1*, TDC1 DVI Data Channel 1 Outputs These pins provide the DVI differential outputs for data channel 1 (green). 22, 23 Out TDC2*, TDC2 DVI Data Channel 2 Outputs These pins provide the DVI differential outputs for data channel 2 (red).

25 In VSWING DVI Swing Control

This pin sets the swing level of the DVI outputs. A 1.2K ohms resistor should be connected between this pin and TGND using short and wide traces.

26 In BSCAN BSCAN (internal pull-low)

This pin should be pulled low with a 10K ohm. This pin enables the boundary scan for in-circuit testing. Voltage level is 0 to DVDD. ◊ Intel ® Proprietary

201-0000-062 Rev. 2.0, 06/12/2018 5 Table 1: Pin Description (contd.) Pin # Type Symbol Description

27 In Reserved Reserved (internal pull-down)

This pin should be pulled low with a 10K ohm resistor.

29 In HPDET Hot Plug Detect (internal pull-down)

This input pin determines whether the DVI output driver is connected to a DVI monitor. When terminated, the monitor is required to apply a voltage greater than 2.4 volts. Changes on the status of this pin will be relayed to the graphics controller via the SDVO_INT+/- pins, where toggling between 100MHz and 200MHz is considered an assertion (‘1’ v alue), not toggling at all is considered a de-assertion (‘0’ value). When the HPDET is low, the DVI output is shut down 32, 33 Out SDVO_INT+/- Interrupt Output Pair associated with SDVO Data Channel These pins output one AC-coupled differential pair of interrupt signals used as a hot plug attach/detach notification to VGA controller of a monitor driven by data SDVO_R+/-, SDVO_G+/- and SDVO_B+/-. Toggling between 100MHz and 200MHz on this pair is considered an assertion (‘1’ value); not toggling at all is consi dered a de-assertion (‘0’ value).

34 Out Reserved Reserved

This pin should not be connected in the application.

35 Out Reserved Reserved

This pin should not be connected in the application. 37, 38, 40, 41, 43, 44 In SDVO_R+/-, SDVO_G+/-, SDVO_B+/- SDVO Data Channel Inputs These pins accept 3 AC-coupled differential pairs of inputs from a digital video port of a graphics controller. These 3 pairs of inputs are R, G, and B. The differential p-p input voltage has a maximum value of 1.2V, with a min. value of 175mV. 46, 47 In SDVO_CLK+/- Differential Clock Input associated with SDVO Data channel These pins accept one AC-coupled differential pair of input from a digital video port of a graphics controller. The range of this clock pair is 100~200MHz. For specified pixel rates in specified modes this clock pair will run at an integer multiple of the pixel rate. Refer to Section 2.1.3 for details. The differential p-p input voltage has a maximum value of 1.2V, with a min. value of 175mV. 12,28 Power DVDD Digital Supply Voltage (2.5V) 7,30 Power DGND Digital Ground 15, 21 Power TVDD DVI Transmitter Supply Voltage (3.3V) 18, 24 Power TGND DVI Transmitter Ground 36, 42, 48 Power AVDD Analog Supply Voltage (2.5V) 31, 39, 45 Power AGND Analog Ground 1 Power AVDD_PLL DVI PLL Supply Voltage (3.3V)

6 Power AGND_PLL DVI PLL Ground

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2.0 FUNCTIONAL DESCRIPTION

2.1 Input Interface

2.1.1 Overview

One pair of differential clock signal and three differential pairs of data signals (R/G/B) form one channel data. The input data are 10-bit serialized data. Input data run at 1Gbits/s~2Gbits/s, being a 10x multiple of the clock rate (SDVO_CLK+/-). The CH7307C de-serializes the input into 10-bit parallel data with synchronization and alignment. Then the 10-bit characters are mapped into 8-bit color data or control data (HSYNC, VSYNC, DE).

2.1.2 Interface Voltage Levels

All differential SDVO pairs are AC coupled differential signals. Therefore, there is not a specified DC signal level for the signals to operate at. The differential p-p input voltage has a min of 175mV, and a max of 1.2 V. The differential p-p output voltage has a min of 0.8V, with a max of 1.2V.

2.1.3 Input Clock and Data Timing

A data character is transmitted least significant bit first. The beginning of a character is noted by the falling edge of the SDVO_CLK+ edge. The skew among input lanes is r equired to be no larger than 2ns. The clock is from 100MHz~200MHz. The pixel rate can be 25MP/s~165MP/s. The pixel rate and the clock ra te are not always equal. The clock rate can be a multiple of the pixel rate (1x, 2x, or 4x depending on the pixel rate) so that the clock rate will stay in the 100MHz~200MHz range . In the condition that the clock is running at a multiple of the pixel rate, there isn’t enough pixel data to fill t he data channels. Dummy fill characters (‘000111101 0’) are used to stuff the data stream. The CH7307C supports the following clock multipliers and fill patterns shown in Table 2. Table 2: CH7307C supported Pixel Rates, Clock Rates , Data Transfer Rates and Fill Patterns Pixel Rate Clock Rate – Multiplier Stuffing Format Dat a Transfer Rate - Multiplier 25~50 MP/s 100~200 MHz – 4xPixel Rate Data, Fill, Fil l, Fill 1.00~2.00Gbits/s – 10xClock Rate 50~100 MP/s 100~200 MHz – 2xPixel Rate Data, Fill 1.00 ~2.00Gbits/s – 10xClock Rate 100~200 MP/s 100~200 MHz – 1xPixel Rate Data 1.00~2.00 Gbits/s – 10xClock Rate

2.1.4 Synchronization

Synchronization and channel-to-channel de-skewing is facilitated by the transmission of special characters during the blank period. The CH7307C synchronizes during t he initialization period and subsequently uses the blank periods to re-synchronize to the data stream.

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2.2 DVI Transmitter

Serialized input data, sync and clock signals are input to the CH7307C from the graphics controller’s digital output port. Input is through three differential data pairs and one differential clock pair. The data rate is in the range of 1.0~2Gbits/s. The clock rate, independent with pixel rate, is 1/10 of the data rate; resulting in the range of 100M~200MHz. Horizontal sync and vertical sync information are embedded in the data stream. Some examples of modes supported are shown in the Table 3. For Table 3, input pixel frequencies for given modes were taken from VESA DISPLAY MONITOR TIMING SPECIFICATIONS if they were detailed there, not VESA TIMING DEFINITION FOR FLAT PANEL MONITORS. The device is not dependent upon this set of timing specifications. Any values of input pixels/line, lines/frame and clock rate are acceptable, as long as the pixel rate remains below 165MHz. Table 3: DVI Output Formats Graphics Resolution Active Aspect Ratio Pixel Aspect Ratio Refresh Rate (Hz) Input pixel Frequency (MHz) DVI Frequency (Mbits/Sec) 720x400 4:3 1.35:1.00 <85 <35.5 <355 640x400 8:5 1:1 <85 <31.5 <315 640x480 4:3 1:1 <85 <36 <360 800x600 4:3 1:1 <85 <57 <570 1024x768 4:3 1:1 <85 <95 <950 1280x720 16:9 1:1 <85 <110 <1100 1280x768 15:9 1:1 <85 <119 <1190 1280x1024 4:3 1:1 <85 <158 <1580 1366x768 16:9 1:1 <85 <140 <1400 1360x1024 4:3 1:1 <75 <145 <1450 1400x1050 4:3 1:1 <75 <156 <1560 1600x1200 4:3 1:1 <60 <165 <1650 1920x1080◊ 16:9 1:1 <60 <165 <1650 1920x1200 ◊ 16:10 1:1 <60 <165 <1650 ◊ This mode is implemented with reduced blanking. Table 4: Popular Panel Sizes UXGA 1600x1200 SXGA+ 1400x1050 1360x1024 SXGA 1280x1024 1280x960 XGA 1024x768 1024x600 SVGA 800x600

2.3 Emission Reduction Clock

DVI output can support a +- 2.5% spreading in the output clock to reduce EMI emission. The frequency a nd amplitude of the spreading triangle waveform can be programmed via the serial port.

2.4 Command Interface

Communication is through two-wire path, control clo ck (SPC) and data (SPD). The CH7307C accepts incomi ng control clock and data from graphics controller, and is capable of redirecting that stream to the ADD2 card PROM, DDC, or CH7307C internal registers. The control bus is able to run up to 1MHz when communicating with internal registers, up to 400 kHz for the PROM and up to 100 kHz for the DDC.

8 201-0000-062 Rev. 2.0, 06/12/2018 Internal Device Registers DDC PROM SPC,SPD observer control the switch on/off default position Figure 3: Control Bus Switch Upon reset, the default state of the directional switch is to redirect the control bus to the ADD2 PROM. At this stage, the CH7307C observes the Control bus traffic. If the observing logic sees a control bus transaction destined for the internal registers (device address 70h or 72h), it disables the PROM output pairs, and switches to internal registers. In the condition that traffic is to the internal registers, an opcode command is used to set the redirection circuitry to the appropriate destination (ADD2 PROM or DDC). Redirecting the traffic to internal registers while at the stage of traffic to DDC occurs on observing a STOP after a START on the control bus.

2.5 Boundary Scan Test

CH7307C provides so called “NAND TREE Testing” to v erify IO cell function at the PC board level. This test will check the interconnection between chip I/O and the printed circuit board for faults (soldering, bend leads, open printed circuit board traces, etc.). NAND tree test is a simple serial logic which turns all IO cell signals to input mode, connects all inputs with NAND gates as shown in Figure 4 and switches each signal to high or low according to the sequence in Table 5. The test results then pass out at pin #25 (VSWING) . Figure 4: NAND Tree Connection Testing Sequence Set BSCAN =1; (internal weak pull-low) Set all signals listed in Table 5 to 1. Set all signals listed in Table 5 to 0, toggle one by one with certain time period, suggested 100 ns. Pin #25 will change its value each time an input value changed.

201-0000-062 Rev. 2.0, 06/12/2018 9 Table 5: Signal Order in the NAND Tree Testing Order Pin Name LQFP Pin

1 HPDET 29

2 SDVO_INT+ 32

3 SDVO_INT- 33

4 Reserved 34

5 Reserved 35

6 AS 3

7 SPC 4

8 SPD 5

9 SD_PROM 8

10 SC_PROM 9

11 SD_DDC 10

12 SC_DDC 11

13 TLC* 13

14 TLC 14

15 TDC0* 16

16 TDC0 17

17 TDC1* 19

18 TDC1 20

19 TDC2* 22

20 TDC2 23

Table 6: Signals not tested in NAND Test Pin Name LQFP Pin SDVO_R+ 37 SDVO_R- 38 SDVO_G+ 40 SDVO_G- 41 SDVO_B+ 43 SDVO_B- 44 SDVO_CLK+ 46 SDVO_CLK- 47 RESET* 2 BSCAN 26 Reserved 27 VSWING 25

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3.0 REGISTER CONTROL

The CH7307C is controlled via a serial control port . The serial bus uses only the SC clock to latch data into registers, and does not use any internally generated clocks so that the device can be written to in all power down modes. The device will retain all register values during power down modes. Registers 00h to 11h are reserved for opcode use. All registers except bytes 00h to 11h are reserved for internal factory use. For details regarding Intel ® SDVO opcodes, please contact Intel ®.

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4.0 ELECTRICAL SPECIFICATIONS

4.1 Absolute Maximum Ratings

Symbol Description Min Typ Max Units All 2.5V power supplies relative to GND All 3.3V power supplies relative to GND -0.5 -0.5 3.5 5.0 V TSC Analog output short circuit duration Indefinite Sec TSTOR Storage temperature -65 150 °C TJ Junction temperature 150 °C Vapor phase soldering (5 seconds) 260 °C Vapor phase soldering (11 seconds) 245 °C TVPS Vapor phase soldering (60 seconds) 225 °C Note: 1) Stresses greater than those listed under absolute m aximum ratings may cause permanent damage to the de vice. These are stress ratings only and functional operat ion of the device at these or any other conditions above those indicated under the normal operating condition of t his specification is not implied. Exposure to absol ute maximum rating conditions for extended periods may affect reliability. The temperature requirements of vapor phase soldering apply to all standard and lead free parts. 2) The device is fabricated using high-performance CMO S technology. It should be handled as an ESD sensit ive device. Voltage on any signal pin that exceeds the power supply voltages by more than ± 0.5V can induce destructive latch up.

4.2 Recommended Operating Conditions

Symbol Description Min Typ Max Units AVDD Analog Power Supply Voltage 2.375 2.5 2.625 V AVDD_PLL Analog PLL Power Supply Voltage 3.100 3.3 3.500 V DVDD Digital Power Supply Voltage 2.375 2.5 2.625 V TVDD DVI Power Supply 3.100 3.3 3.500 V VDD33 Generic for all 3.3V supplies 3.100 3.3 3.500 V VDD25 Generic for all 2.5V supplies 2.375 2.5 2.625 V TAMB Ambient operating temperature (Commercial / Automotive Grade 4) 0 70 °C

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4.3 Electrical Characteristics

(Operating Conditions: TA = 0 °C to 70 °C for parts qualified as Commercial / Automotive Grade 4, T A = –40 °C to 85 °C for parts qualified as Industrial / Automotive Grade 3, VDD25 =2.5V ± 5%, VDD33=3.3V ± 5%) Symbol Description Min Typ Max Units IVDD25 Total VDD25 supply current (2.5V supplies) Pixel Rate=162MHz 175 200 mA IVDD33 Total VDD33 supply current (3.3V supply) Pixel Rate=162MHz 75 100 mA IPD Total Power Down Current (all supplies) 50 uA

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4.4 DC Specifications

Symbol Description Test Condition Min Typ Max Unit VRX-DIFFp-p SDVO Receiver Differential Input Peak to Peak Voltage VRX-DIFFp-p = 2 *  VRX-D+ - VRX-D-  0.175 1.200 V ZRX-DIFF-DC SDVO Receiver DC Differential Input Impedance 80 100 120 Ω ZRX-COM-DC SDVO Receiver DC Common Mode Input Impedance 40 50 60 Ω ZRX-COM- INITIAL-DC SDVO Receiver Initial DC Common Mode Input Impedance Impedance allowed when receiver terminations are first turned on 5 50 60 Ω VINT-DIFFp-p SDVO INT Differential Output Peak to Peak Voltage 0.8 1.2 V VSDOL

1 SPD (serial port data) Output

I OL = 2.0 mA 0.4 V VSPIH

2 Serial Port (SPC, SPD) Input

2.0 VDD25 +

0.5 V VSPIL GND-0.5 0.4 V VHYS Hysteresis of Serial Port Inputs 0.25 V VDDCIH DDC Serial Port Input High Voltage 4.0 VDD5 + 0.5 V VDDCIL DDC Serial Port Input Low Voltage GND-0.5 0.4 V VPROMIH PROM Serial Port Input High Voltage 4.0 VDD5 + 0.5 V VPROMIL PROM Serial Port Input Low Voltage GND-0.5 0.4 V VSD_DDCOL

3 SPD (serial port data) Output

Low Voltage from SD_DDC (or SD_EPROM) Input is V INL at SD_DDC or SD_EPROM. 4.0k Ω pull-up to 2.5V. 0.9*V INL + 0.25 V VDDCOL

4 SC_DDC and SD_DDC

and SPD. 5.6k Ω pull-up to 5.0V. 0.933*V INL + 0.35 V VEPROMOL

5 SC_EPROM and

SD_EPROM Output Low Voltage Input is V INL at SPC and SPD. 5.6k Ω pull-up to 5.0V. 0.933*V INL + 0.35 V VMISC1IH

6 RESET*, BSCAN

2.7 VDD33 +

0.5 V VMISC1IL GND-0.5 0.5 V VMISC2IH 7 AS Input High Voltage 0.5 V

14 201-0000-062 Rev. 2.0, 06/12/2018 DC Specifications (contd.) Symbol Description Test Condition Min Typ Max Unit VMISC2IL 7 AS Input Low Voltage DVDD=2.5V GND-0.5 0.5 V VMISC3IH

8 HPDET

2.0 VDD33 +

0.5 V VMISC3IL DVDD=2.5V GND-0.5 0.5 V IMISC1PD BSCAN Pull-Down Current V IN = 3.3V 10 40 µA IMISC1PU RESET* Pull-Up Current V IN = 0V 10 40 µA IMISC2PD HPDET Pull-Down Current V IN = 2.5V 5 20 µA IMISC2PU AS Pull-Up Current V IN = 0V 10 40 µA VH DVI Single Ended Output High Voltage TVDD – 0.01 TVDD + 0.01 V VL DVI Single Ended Output Low Voltage TVDD – 0.6 TVDD – 0.4 V VSWING DVI Single Ended Output Swing Voltage 400 600 mVp-p VOFF DVI Single Ended Standby Output Voltage TVDD = 3.3V ± 5% R TERM = 50 Ω ± 1% RSWING = 1200 Ω ± 1% TVDD – 0.01 TVDD + 0.01 V Notes: 1. Refers to SPD . V SPOL is the output low voltage from SPD when transmitting from internal registers not from DDC or EEPROM. 2. Refers to SPC, SPD. 3. V SD_DDCOL is the output low voltage at the SPD pin when the voltage at SD_DDC or SD_PROM is V INL . Maximum output voltage has been calculated with the worst case of pull-up of 4.0k Ω to 2.5V on SPD. 4. V DDCOL is the output low voltage at the SC_DDC and SD_DDC pins when the voltage at SPC and SPD is V INL . Maximum output voltage has been calculated with 5.6k pull-up to 5V on SC_DDC and SD_DDC. 5. V PROMOL is the output low voltage at the SC_PROM and SD_PROM pins when the voltage at SPC and SPD is V INL . Maximum output voltage has been calculated with 5.6k Ω pull-up to 5V on SC_PROM and SD_PROM. 6. V MISC1 refers to RESET* and BSCAN inputs which are 3.3V compliant. 7. V MISC2 refers to AS which are 2.5V compliant. 8. V MISC3 refers to HPDET that is 2.5V/3.3V compliant.

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4.5 AC Specifications

Symbol Description Test Condition Min Typ Max Unit UI DATA SDVO Receiver Unit Interval for Data Channels Typ. – 300ppm 1/[Data Transfer Rate] Typ. + 300ppm ps fSDVO_CLK SDVO CLK Input Frequency 100 200 MHz fPIXEL DVI Transmitter Pixel rate 25 165 MHz fSYMBOL SDVO Receiver Symbol frequency 1 2 GHz tRX-EYE SDVO Receiver Minimum Eye Width 0.4 UI tRX-EYE-JITTER SDVO Receiver Max. time between jitter median and max. deviation from median 0.3 UI VRX-CM-ACp SDVO Receiver AC Peak Common Mode Input Voltage 150 mV RL RX-DIFF Differential Return Loss 50MHz – 1.25GHz 15 dB RL RX-CM Common Mode Return Loss 50MHz – 1.25GHz 6 dB tSKEW SDVO Receiver Total Lane to Lane Skew of Inputs Across all lanes 2 ns tDVIR DVI Output Rise Time (20% - 80%) f XCLK = 165MHz 75 242 ps tDVIF DVI Output Fall Time (20% - 80%) f XCLK = 165MHz 75 242 ps TSPR SPC, SPD Rise Time (20% - 80%) Standard mode 100K Fast mode 400K 1M running speed 1000 300 150 ns ns ns TSPF SPC, SPD Fall Time (20% - 80%) Standard mode 100K Fast mode 400K 1M running speed 300 300 150 ns ns ns TPROMR SC_PROM, SD_PROM Rise Time (20% - 80%) Fast mode 400K 300 ns TPROMF SC_PROM, SD_PROM Rise Time (20% - 80%) Fast mode 400K 300 ns TDDCR SC_DDC, SD_DDC Rise Time (20% - 80%) Standard mode 100K 1000 ns TDDCF SC_DDC, SD_DDC Fall Time (20% - 80%) Standard mode 100K 300 ns TDDCR-DELAY

1 SC_DDC, SD_DDC Rise

Time Delay (50%) Standard mode 100K 0 ns TDDCF-DELAY

1 SC_DDC, SD_DDC Fall

Time Delay (50%) Standard mode 100K 3 ns tSKDIFF DVI Output intra-pair skew f XCLK = 165MHz 90 ps

16 201-0000-062 Rev. 2.0, 06/12/2018 Symbol Description Test Condition Min Typ Max Unit tSKCC DVI Output inter-pair skew f XCLK = 165MHz 1.2 ns tDVIJIT DVI Output Clock Jitter f XCLK = 165MHz 150 ps Notes: 1. Refers to the figure below, the delay refers to th e time pass through the internal switches. R=5K 3.3V typ. 2.5V typ. To SPC/SPD pin To DDC pin

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5.0 PACKAGE DIMENSIONS

K K B A G EF .008" H J I BO TTO M VIEW TO P VIEW 1X4 5 3X Figure 5: 48 Pin LQFP (Exposed Pad) Package Table of Dimensions No. of Leads SYMBOL 48 (7 X 7 mm) A B C D E F G H I J K Notes: 1. Conforms to JEDEC standard JESD-30 MS-026D. 2. Dimension B: Top Package body size may be smaller than bottom package size by as much as 0.15 mm. 3. Dimension B does not include allowable mold protrus ions up to 0.25 mm per side. 4. (1X) Corner in quadrant with Pin1 identifier (dot) is always chamfered. Exact shape of chamfer is optional. 5. (3X) Corners in quadrants without Pin1 identifier ( dot) may be square or chamfered. Exact shape of cor ner or chamfer is optional.

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6.0 REVISION HISTORY

Table 7: Revisions Rev. # Date Section Description 0.6 05/19/04 All New release for CH7307C 0.61 06/10/04 1.2 Update SPC, SC_DDC, SC_PROM to In/Ou t type. 1.0 09/01/04 All 1.1 10/21/04 4.1 Vapor phase soldering information upd ated 1.11 11/05/04 1.2 Update HPDET description 1.2 11/09/04 4.3 Update power down current number 1.22 10/05/05 4.4, 4.5 Update DC, AC specifications an d order information 1.3 10/28/05 1.2 Update BSCAN pin description. 1.4 07/31/08 2.5 Update Table 5. Pin numbers. 1.5 12/02/08 4.2, 4.3 Update operating temperature. 1.6 10/09/09 2.2 Update Features and General Descripti on and Table.3. 1.7 04/06/11 4.0 Update ambient operating temperature. Automotive Grade 4 and Industrial / Automotive Grade 3. Unify the description of pin 26 and pin 27. Modify some “Absolute Maximum Ratings”. Add some notes for “Pac kage Dimensions”. 1.9 11/19/12 1.2 Pin 26 and pin 27 should be connected to ground through a 10K resistor. 1.91 1/07/14 1.2, 4.1, 4.2 Pins 32/33 (SDVO_INT+/-) an d 46/47 (SDVO_CLK+/-) should be AC-coupled. Move TAMB from 4.1 to 4.2. 1.20 06/12/18 4.2, 6.0, Ordering info Remove Industria l /Automotive Grade 3 (EOL). Revise T AMB section 4.2 + Revision History Section 6.0 + ordering information section.

201-0000-062 Rev. 2.0, 06/12/2018 19 Disclaimer This document provides technical information for th e user. Chrontel reserves the right to make change s at any time without notice to improve and supply the best possi ble product and is not responsible and does not ass ume any liability for misapplication or use outside the lim its specified in this document. We provide no warr anty for the use of our products and assume no liability for errors contained in this document. The customer should ma ke sure that they have the most recent data sheet version. Cust omers should take appropriate action to ensure thei r use of the products does not infringe upon any patents. Chron tel, Inc. respects valid patent rights of third par ties and does not infringe upon or assist others to infringe upon such rights. Chrontel PRODUCTS ARE NOT AUTHORIZED FOR AND SHOULD NOT BE USED WITHIN LIFE SUPPORT SYSTEMS OR NUCLEAR FACILITY APPLICATIONS WITHOUT TH E SPECIFIC WRITTEN CONSENT OF Chrontel. Life support systems are those intended to support or sustain life and whose failure to per form when used as directed can reasonably expect to result in personal injury or death.

ORDERING INFORMATION

Part Number Package Type Number of Pins Voltage Supply Temperature Grade CH7307C-DEF Lead free LQFP with exposed pad 48 2.5V & 3.3V Commercial / Automotive Grade 4 CH7307C-DEF-TR Lead free LQFP with exposed pad in Tape & Reel 48 2.5V & 3.3V Commercial / Automotive Grade 4 Chrontel

2210 O’Toole Avenue, Suite 100,

San Jose, CA 95131-1326 Tel: (408) 383-9328 Fax: (408) 383-9338 www.chrontel.com E-mail: sales@chrontel.com  2014 Chrontel, Inc. All Rights Reserved. Printed in the U.S.A.