CH7511B CHRONTEL | Alldatasheet
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209-1000-023 Rev. 1.2 07/15/2020 1 Chrontel CH7511B eDP to LVDS Converter FEATURES GENERAL DESCRIPTION Supports Embedded DisplayPort (eDP) Specification version 1.2. Support 2 Main Link Lanes at either 1.62Gb/s or 2.7Gb/s link rate for notebook PC applications Supports input color depth 6, 8-bit per pixel in RGB format Supports Enhanced Framing Mode Support VESA and CEA timing standards up to 1920x1200 resolution in 8-bit input with 60Hz refresh rate Support dynamic refresh rate switching Support Gamma correction Panel tuning methods including dithering and 6-bit + FRC Fast and full Link Training for embedded DisplayPort system Support eDP Authentication: Alternative Scramble Seed Reset and Alternative Framing 2 work modes: connect 27MHz crystal, inject 27MHz clock Programmable LCD panel power sequence Support 18-bit Single Port, 18-bit Dual Port, 24-bit Single Port and 24-bit Dual Port LVDS output interface Support both OpenLDI and SPWG bit mapping for LVDS application Support panel select by GPIO pins control or writing the chip registers. Flexible LVDS output pins swapping Blank panel during invalid input Supports PWM. Backlight luminance level control through AUX channel, PWM pin and BLUP/BLDN pin Support Dynamic Backlight Control Support OSD display when BLUP/BLDN pins control Backlight Luminance Hot Plug Detection Loads Boot ROM automatically upon power up Serial BOOT ROM data updated through I2C bus or AUX Channel Programmable power management EMI reduction capability for eDP input and LVDS output. Spread spectrum control is available for transmitting LVDS signal Offered in a 68-pin QFN package Chrontel’s CH7511B is a low -cost, low -power semiconductor device that translates the Embedded DisplayPort signal to the LVDS (Low-voltage Differential Signaling) . This innovative DisplayPort receiver w ith an integrated LVDS transmitter is specially designed to target the All -In-One PC and the notebook market segments. Through the CH7511B’s advanced decoding / encoding algorithm, the input eDP high -speed serialized video data can be seamlessly converted to LVDS, a popular display technology for high -speed serial links in mid/large -sized LCD displays. Leveraging the eDP’s unique source/sink “Link Training” routine, the CH7511B is capable of instantly bring up the video display to the LCD when the initializ ation process is completed between CH7511B and the graphic chip. The CH7511B is designed to meet the Embedded DisplayPort Specification version 1. 2. In the device’s receiver block, which supports two eDP Main Link Lanes input with data rate running at either 1.62Gb/s or 2.7Gb/s, can accept RGB digital formats in either 18 -bit 6:6:6 or 24 -bit 8:8:8 for LVDS output up to 1920x1200. To comply with GPU’s new power saving scheme such as display frame rate reduction, the CH7511B is equipped with the Dynamic Refr esh Rate switching method, which can automatically reduce to the low refresh rate supported by the LVDS panel. The integrated LVDS transmitter supports the single port and the dual port s LVDS outputs to drive display resolution up to WUXGA ( 1920x1200). CH7511B supports panel select by GPIO[0:3] pins control or writing the chip registers. To reduce EMI emission, the CH7511B’s LVDS encoder block has incorporated Spread Spectrum control and its spread percentage can be adjusted through the internal registers. The Backlight On/Off and the PWM are two luminance control functions designed in the CH7511B LVDS power control module. The brightness control commands sent through AUX Channel can be dynamically translated by CH7511B and converted into LCD backlight control signal. The CH7511B will save the last setting of brightness level into the BOOT ROM and restore it upon power up. The CH7511B can dynamically adjust backlight brigntness according to video stream to save power consumption and it supports OSD display in this way. The CH7511B will immediately convert the eDP signal to LVDS output after eDP Link Training is completed. This feature can be achieved by loading the panel’s EDID and the CH7511B’s configuration settings in the serial BOOT ROM connected to t he CH7511B. During system power-up and upon completion of the eDP Link Training through AUX Channel , CH7511B will generate LVDS signal according to the panel power-up timing sequencing stored in the BOOT ROM.
2 209-1000-023 Rev. 1.2 07/15/2020 Main Link Rx (2 Lane) Gamma Correction & Dithering & FRC LVDS Tx
2 Channel
GPIO & IIC Controller Power Sequence Controller PLL HPD eDP Main Link AUX CH9904 Boot ROM IIC Backlight Brightness Control GLED/OLED /PWM In/Out LVDS Power Control Stream Sinks OSD Clock IRQ Panel Select Figure 1: CH7511B Function Block Diagram CH7511B eDP LVDS PWMPWM Backlight Brightness Control Boot ROM Panel Backlight Enable Panel Power Enable Crystal or Reference Clock GPIOs LCD Panel Figure 2: CH7511B Application Diagram
209-1000-023 Rev. 1.2 07/15/2020 3
1.0 PIN ASSIGNMENT
1.1 Package Diagram
PWM_OUT0 AUXP AUXN DVDD GND ENAVDD PWM_IN SPC0 SPD0 SPC1 SPD1 DP1P DP1N AVDD GND DP0P DP0N AVDD HPDET BLUP BLDN OLED GLED PWRDN GPIO[3] GPIO[2] GND GND IRQ CHRONTEL CH7511 QFN 68 3534 AVDD RBIAS REFCK LVDD GPIO[0] GPIO[1] DVDD GND XO XI RESETB LDC0P LDC1N LDC1P LDC2N LDC2P LL1CN PWM_OUT1 Figure 3: CH7511B 68-pin QFN pin out
1.2 Pin Description
Table 1: Pin Description Pin # Type Symbol Description
1 In RESETB Reset Input (Internal pull-up)
When this pin is low, the device is held in the power -on reset condition. When this pin is high (1.8V), reset is controlled through the serial port register. It should be pulled high to DVDD with a 10 K resistor.
2 RESERVED Reserved
This pin should be left open in the application.
5 Out XO
A parallel resonant 27MHz crystal (± 20 ppm) should be attached between this pin and XI. Note: 50ppm to pin XO
6 In XI Crystal Input
A parallel resonant 27MHz crystal (± 20 ppm) should be attached between this pin and XO.
4 209-1000-023 Rev. 1.2 07/15/2020 Pin # Type Symbol Description Note: 50ppm to pin XI
9 In REFCK Reference Clock Input
This pin is also used as clock input pin when injecting 27 MHz (3.3V) clock to CH7511B. 10~17, 19,20, 22~31 Out LL1CP/N, LL2CP/N LDC [7:0] P/N LVDS Output LDC7P/N ~ LDC0P/N can be configured to LVDS differential signals, which are used as A7M/P to A0M/P. LL1CP/N and LL2CP/N are used as CLK1 and CLK2 respectively. 33~34, 37~38 In GPIO [3:0] Panel Select Control Signals These pins could be pulled high (10 K resistor to +3.3V) or low forming into 16 different combinations. Every combination can match with one panel type.
36 Out IRQ Programmable Interrupt output
Output an interrupt signal while there’s input from BLDN or BLUP.
39 Out PWM_OUT1 PWM Output for Backlight Brightness Dimming
PWM Duty Cycle Range: 30~100%(16 steps) The output Frequency from PWM_OUT1 can be up to 400KHz. Voltage level is 3.3V.
41 In PWRDN Power Down Control
CH7511B enters/exit power down state when receiving active low pulse (0V) from this pin. 43,44 In/Out AUXP, AUXN AUX Channel Differential Input/Output These two pins are eDP AUX Channel control, which supports a half-duplex, bi-directional AC-coupled differential signal.
46 Out ENABKL LCD Panel Backlight Enable
Enable backlight of LCD panel (3.3V) Out ENAVDD LCD Panel VCC Enable Enable LCD panel VDD (3.3V)
48 Out PWM_OUT0 PWM Output for Backlight Brightness Dimming / Bypass PWM_IN
PWM Duty Cycle Range: 0~100%(16 steps) The output Frequency from PWM_OUT0 can be up to 400KHz. Voltage level is 3.3V. Bypass PWM input, and while in bypass mode, frequency of PWM_OUT0 can be up to 1MHz.
49 In PWM_IN Backlight brightness PWM input
PWM_IN has two work modes: Bypass mode and Duty Cycle Multiplication with AUX CH mode. In bypass mode, the input frequency to PWM_IN can be up to 1MHz. In Duty Cycle Multiplication with AUX CH mode, the input frequency to PWM_IN can be up to 50KHz. Voltage level is 3.3V.
50 In/Out SPD1 Serial Port Data Input/Output for Chip BOOT ROM/EDID
This pin functions as the bi-directional data pin of the serial port and operates with inputs from 0 to 3.3V. Outputs are driven from 0 to 3.3V. This pin requires an external 4K - 9 K pull up resistor to 3.3V.
51 Out SPC1 Serial Port Clock Output for Chip BOOT ROM/EDID
This pin functions as the clock output of the serial port and operates with output from 0 to 3.3V. This pin requires an external 4K - 9K pull up resistor to 3.3V.
53 In/Out SPD0 Serial Port Data Input/Output for Register Map
This pin is used to access CH7511B internal registers. It functions as the bi- directional data pin of the serial port and operates with input from 0 to 3.3V. Output is driven from 0 to 3.3V. This pin requires an external 6K - 8 K pull up resistor to 3.3V.
54 In SPC0 Serial Port Clock Input for Register Map
This pin is used to access CH7511B internal registers. It functions as the clock input of the serial port and operates with input from 0 to 3.3V. This pin
209-1000-023 Rev. 1.2 07/15/2020 5 Pin # Type Symbol Description requires an external 6K - 8 K pull up resistor to 3.3V.
55 In BLDN Decrement Backlight Brightness Input
56 In BLUP Increment Backlight Brightness Input
57 Out GLED Green LED Control
This pin indicates CH7511B in normal power and mode status. Its output voltage is 3.3V.
58 Out OLED Orange LED Control
This pin indicates CH7511B in abnormal power and mode status. Its output flickers from 0 or 3.3V.
59 Out HPDET Hot Plug Detect
This output pin is used as the connection detection by a DisplayPort Source system. It generates interrupt pulse as defined by DisplayPort standard. The output voltage is 3.3V. A 100 k resistor should be connected between this pin and GND. It should be linked to DisplayPort source. 61,62 64,65 In DP[1:0]P/N Main Link Lane Input These pins accept two AC-coupled differential pairs signals from the eDP transmitter.
68 In RBIAS Band-gap Bias input
A 10 K(1%) resistor should be connected between this pin and GND. 3,4,60,66,6 Power AVDD Analog Power Supply (1.8V) 7,42 Power DVDD Digital Power Supply (1.8V) 18,32,52 Power LVDD LVDS Driver Power Supply and GPO Power Supply (3.3V) 8,21,35,40, 45,63, Thermal Exposed Pad Power GND Power Ground
6 209-1000-023 Rev. 1.2 07/15/2020
2.0 PACKAGE DIMENSIONS
A A I H G BOTTOM VIEW C B F D E Pin 1 Figure 4: 68 Pin QFN Package (8x8 mm) Table of Dimensions No. of Leads SYMBOL 68 (8x8 mm) A B C D E F G H I Milli- meters MIN 7.90 4.30 4.30 0.40 BSC 0.15 0.30 0.70 0 0.203 Notes: 1. All dimensions conform to JEDEC standard MO-207
209-1000-023 Rev. 1.2 07/15/2020 7 Disclaimer This document provides technical information for the user. Chrontel reserves the right to make changes at any time without notice to improve and supply the best possible product and is not responsible and doe s not assume any liability for misapplication or use outside the limits specified in this document. CHRONTEL warrants each part to be free from defects in material and workmanship for a period of one (1) year from date of shipment. Chrontel assumes no liability for errors contained within this document . The customer should make sure that they have the most recent data sheet version. Customers should take appropriate action to ensure their use of the products does not infringe upon any patents. Chrontel , Inc. respects valid patent rights of third parties and does not infringe upon or assist others to infringe upon such rights. Chrontel PRODUCTS ARE NOT AUTHORIZED FOR AND SHOULD NOT BE USED WITHIN LIFE SUPPORT SYSTEMS OR NUCLEAR FACILITY APPLICATIONS WIT HOUT THE SPECIFIC WRITTEN CONSENT OF Chrontel. Life support systems are those intended to support or sustain life and whose failure to perform when used as directed can reasonably expect to result in personal injury or death.
ORDERING INFORMATION
Part Number Package Type Operating Temperature Range Minimum Order Quantity CH7511B-BF 68QFN, Lead-free Commercial : 0 to 70C 260/TRAY CH7511B-BFI 68QFN, Lead-free Industrial : -40 to 85C 260/TRAY Chrontel www.chrontel.com E-mail: sales@chrontel.com 2020 Chrontel - All Rights Reserved.