CH7216A CHRONTEL | Alldatasheet
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209-1000-151 Rev 1.2 2022-12-30 1 Chrontel CH7216A DisplayPort to HDMI 2.0 Converter on USB Type C FEATURES GENERAL DESCRIPTION Compliant with DisplayPort Alternate Mode on USB Type C standard Compliant with Displ ayPort Specification version 1. 4 and Embedded DisplayPort (eDP) Specification vers ion 1.4 Support up to 4 Main Link Lane s at 1.62Gbps,2.7Gbps (HBR), 5.4Gbps (HBR2), or 8.1Gbps (HBR3) link rate Adaptive DisplayPort receiver equalization supported for the compensation of input signal attenuation Support Fast and Full Link Training Support eDP Authentication: Alternative Scramble Seed Reset and Alternative Framing HDMI transmitter compliant with HDMI specification version 2.0 and DVI specification version 1.0 HDMI transmitter supports up to 6.0Gbps data rate for video timing of 4Kx2K@60Hz SCDC supported on HDMI DDC CEC tunneling over AUX is supported High-Dynamic-Range (HDR) Static Metadata: HDR10 (SMPTE ST2084), Hybrid Log -Gamma (HLG), Dolby Vision (SMPTE ST2084) are supported RGB/YCC444/422 to YCC444/422/420 conversions are supported, deep color depth up to 16 bit Progressive 3D video formats supported HDCP engine compliant with HDCP 2. 3 and HDCP 1.4 specification with internal HDCP Keys HDCP 1.4/2.3 repeater supported USB Type -C port compliant with USB Type -C Cable and Connector Specification revision 2.0 Compliant with USB Power Delivery Specification Revision 3.0, with USB Power Delivery BMC transceiver integrated on USB Type-C port Integrated Ra, Rd and Rp for USB Type-C SPDIF/IIS input supported with audio sampling rate up to 192KHz On-chip Audio Decoder which support 8 channel Audio input from DP Rx and output from HDMI Tx , support LPCM(16/20/24 bit) format with sampling rate up to 192kHz, compressed audio format s (AC3, DTS, DTS- HD MA, and Dolby MAT) and HBR audio formats with frame rate up to 1536kHz Embedded MCU to handle the control logic Full speed USB billboard module supported with USB
2.0 PHY integrated
Embedded ROM, integrated EDID Buffer IIC Slave, USB 2.0 are available for firmware update IIC slave interface are available for debug Low power architecture , s upport Auto Power Saving mode and low stand-by current RoHS compliant and Halogen free package Offered in 68 pin QFN package Chrontel’s CH7216A is a low -cost, low -power semiconductor device that translates the DisplayPort signal to HDMI/DVI through the USB Type -C connector. This innovative USB Type -C based DisplayPort receiver with an integrated HDMI Transmitter is specially designed to target the U SB Type -C to HDMI converter, adapter and dongle device. Through the CH7216A’s advanced decoding / encoding algorithm, the input DisplayPort high-speed serialized multimedia data can be seamlessly converted to HDMI/DVI output. The CH7216A’s DP/eDP receiver is compliant with the DisplayPort Specification 1.4 and Embedded DisplayPort (eDP) Specification version 1. 4. With sophisticated DisplayPort signal detection and the Lane Swap/AUX polarity inversion logic, the CH7216A supports USB Type-C cable plug orientation switch. With internal HDCP key Integrated, the device support HDCP 2. 3 specifications. In the device’s receiver block, which supports four DisplayPort Main Link Lanes input with data rate running at 1.62Gbps, 2.7Gbps , 5.4Gbps or 8.1Gpbs, and converted the input signal to HDMI output up to 4Kx2k@60Hz. Leveraging the USB Power Delivery control logic, the USB billboard module for USB device indentify and DisplayPort’s unique source/sink “Link Training” routine, the CH7216A is capable of instantly bring up the video display to the HDMI/DVI TV/Monitor when the initialization process is completed. The CH7216A also supports up to 8 -channel audio input from either DP Rx or SPDIF /IIS port and output from HDMI Tx with sample rate up to 192 KHz. Available audio bandwidth depends on the pixel clock frequency, the video format timing, and whether or not content protection re-synchronization is needed. With sophisticated MCU and the embedded ROM, CH7216A supports auto-boot and EDID buffer. Leveraging the firmware auto -loaded from the embedded ROM, CH7216A supports DP input detection, HDMI connection detection, and determine to enter into Power saving mode automatically.
2 209-1000-151 Rev 1.2 2022-12-30 APPLICATION USB Type C to HDMI 2.0 cable/Adapter On-board DP/eDP to HDMI 2.0 application
209-1000-151 Rev 1.2 2022-12-30 3 TMDS HPD_IN AUX CC0/1_A DisplayPort Main Link 4 x 8.1G CDR USB Billboard / MCU / CEC Tunneling over AUX Repackage Encoder HDCP encryption Serializer USB 2.0 PHY GPIOs Active DDC Buffer DDCDPCD / DDC Register AUX Controller HDP to PD ConverterUSB Power Delivery Control D +/- RAM IIC Slave SPC/SPD IIC Over AUX Transaction HPD_Out ROM Voltage Detection VBUS REF CLOCK GEN Equalizer Pre-emphasis IIS / SPDIF Decoder IIS / SPDIF CEC Figure 1: CH7216A Functional Block Diagram
4 209-1000-151 Rev 1.2 2022-12-30 CH7216A CC0/1 D +/- DP Lane 4X / 2X SBU / AUX TMDS DDC VBUS DCDC HPD USB Type C ALT Mode DFP DP/eDP Tx HDMI 2.0 Rx USB Type C Plug Figure 2: CH7216A USB Type-C to HDMI Dongle Application Block Diagram
209-1000-151 Rev 1.2 2022-12-30 5
1.0 PIN-OUT
1.1 Package Diagram
USB0_DP USB0_DN AVCC RESERVED RESERVED AVCC5V VBUS_DET AUXP RBIAS D2P D2N D3P AVDD D0P D0N D1P D1N AVDD AVCCBG D3N68 AVDD AVDD AGND CC0_A/VCONN/ VCONN_DET VDDS AVDDPLL TXC TX1B GNDS TX0B TX2 TX2B TX1 TX0 AVCC GNDS TXCB VDDS CEC_HM Rd0 HPD_DP/GPIO9 AVCC DVDD DGND HPD_HM SPC0 SPD0 DDC_SDA SCLK/GPIO8 WS/GPIO7 SD0/SPDIF/GPIO6 Ra GPIO4 GPIO5 CC1_A Rd1
51 DDC_SCL
Figure 3: CH7216A 68-Pin QFN Pin Out
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1.2 Pin Description
Table 1: 68 QFN Pin Name Descriptions Pin # Type Symbol Description
3 In XI Crystal Input / External Reference Input
A parallel resonance crystal should be attached between this pin and XO. An external 3.3V CMOS compatible clock also can drive the XI Input
4 Out XO Crystal Output
A parallel resonance crystal should be attached between this pin and XI / FIN. However, if an external CMOS clock is attached to XI/FIN, XO should be left open 5,6 In/Out USB_DN/ USB_DP D+/- Input of USB Type C Interface 7,8 RESERVED RESERVED Pins
10 In VBUS_DET USB VBUS Voltage Detection
Voltage input 0 ~ 5V
13 In RB Reset* Input (Internal pull-up)
When this pin is low, the device is held in the power -on reset condition. When this pin is high, reset is controlled through the serial port register. 14~17 In/Out GPIO[3:0] General Purpose Input/Output Interface 19,20 Out TXCB/ TXC HDMI Clock Outputs These pins provide the differential clock output for the HDMI 23,24 Out TX0B/ TX0 HDMI Data Channel 0 Outputs These pins provide the TMDS differential outputs for data channel 0 26,27 Out TX1B/ TX1 HDMI Data Channel 1 Outputs These pins provide the TMDS differential outputs for data channel 1 30,31 Out TX2B/ TX2 HDMI Data Channel 2 Outputs These pins provide the TMDS differential outputs for data channel 2
33 In Rd0 USB Type-C Dead Battery Rd Resistor
Connect CC0_A to this pin to enable dead battery Rd on CC0_A pin
34 In/Out CC0_A USB Type-C Configure Channel 0
Connect this pin to VCONN pin of USB Type -C Plug Connector if CH7216A is used in VCONN Power Accessory mode. In VCONN_DET USB VCONN Voltage Detection Voltage input 2.7 ~ 5.5v
35 In Ra Ra Resistor
When used in typeC accessory mode, this pin needs connect to CC0.
36 In/Out CC1_A USB Type-C Configure Channel 1
37 In Rd1 USB Type-C Dead Battery Rd Resistor
Connect CC1_A to this pin to enable dead battery Rd on CC1_A pin In/Out GPIO8 General Purpose Input/Output Interface In SCLK I2S Clock Signal
39 In/Out GPIO7 General Purpose Input/Output Interface
In WS I2S Channel Select Signal
40 In/Out GPIO6 General Purpose Input/Output Interface
SPDIF SPDIF Audio Signal Input
44 In/Out SPD0 Serial Port Data Input / Output
209-1000-151 Rev 1.2 2022-12-30 7 This pin functions as the bi -directional data pin of the serial port. External pull-up 6.8 K resister is required
45 In SPC0 Serial Port Clock Input
This pin functions as the clock pin of the serial port. External pull -up
6.8 K resister is required
46 In/Out GPIO5 General Purpose Input/Output
47 In/Out GPIO4 General Purpose Input/Output
48 In HPD_HM HDMI Tx HPD Input
49 Out HPD_DP DP Rx HPD Output
In/Out GPIO9 General Purpose Input/Output
50 In DDC_SDA Serial Port Data to HDMI Receiver
The pin should be connected to data signal of HDMI DDC. This pin requires a pull-up 1.8 kΩ resistor to the desired voltage level
51 Out DDC_SCL Serial Port Clock Output to HDMI Receiver
The pin should be connected to clock signal of HDMI DDC. This pin requires a pull-up 1.8kΩ resistor to the desired voltage level 52,53 In/Out AUXN/AUXP AUX Channel Differential Input/Output These two pins are DisplayPort AUX Channel control, which supports a half-duplex, bi-directional AC-coupled differential signal.
54 In RBIAS HDMI Swing Control
This pin sets the swing level of the HDMI outputs. A 1K-ohm with 1% tolerance resistor should be connected between this pin and ground using short and wide traces. 56,57 In D0P/ D0N DP Main Link Differential Lane 0 Input These pins accept four AC-coupled differential pair signals from the DisplayPort transmitter. 60,61 In D1P/ D1N DP Main Link Differential Lane 1 Input These pins accept four AC-coupled differential pair signals from the DisplayPort transmitter. 63,64 In D2P/ D2N DP Main Link Differential Lane 2 Input These pins accept four AC-coupled differential pair signals from the DisplayPort transmitter. 67,68 In D3P/ D3N DP Main Link Differential Lane 3 Input These pins accept four AC-coupled differential pair signals from the DisplayPort transmitter. 1 Power VDDPLL PLL Power Supply (1.2V) 2,25,41,5 Power AVCC Analog Power Supply(3.3V)
9 Power AVCC5V Analog Power Supply (5V)
11,42 Power DVDD Digital Core/IO Power Supply (1.2V) 12,43 Power DGND Digital Ground 18 Power AVDDPLL PLL Power Supply (1.2V) 21,29 Power VDDS Serializer Power Supply (1.2V) 22,28 Power GNDS Ground 58,59,65, Power AVDD Analog Power Supply (1.2V)
62 Power AGND Analog Ground
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2.0 PACKAGE DIMENSION
D E A BOTTOM VIEW L e b Pin 1 Figure 4: 68 Pin QFN Package (8x8 mm) Table of Dimensions No. of Leads SYMBOL 68 (8x8 mm) D E D2 E2 e b L A A1 A3 Milli- meters Notes: 1. All dimensions conform to JEDEC standard MO-207.
209-1000-151 Rev 1.2 2022-12-30 9 Disclaimer This document prov ides technical information for the user. Chrontel reserves the right to make changes at any time without notice to improve and supply the best possible product and is not responsible and does not assume any liability for misapplication or use outside the limits specified in this document. CHRONTEL warrants each part to be free from defects in material and workmanship for a period of one (1) year from date of shipment. Chrontel assumes no liability for errors contained within this document . The customer should make sure that they have the most recent data sheet version. Customers should take appropriate action to ensure their use of the products does not infringe upon any patents. Chrontel, Inc. respects valid patent rights of third parties and does not infringe upon or assist others to infringe upon such rights. Chrontel PRODUCTS ARE NOT AUTHORIZED FOR AND SHOULD NOT BE USED WITHIN LIFE SUPPORT SYSTEMS OR NUCLEAR FACILITY APPLICATIONS WITHOUT THE SPECIFIC WRITTEN CONSENT OF Chrontel. Life support syst ems are those intended to support or sustain life and whose failure to perform when used as directed can reasonably expect to result in personal injury or death.
ORDERING INFORMATION
Part Number Package Type Content Protection Operating Temperatu re Range Minimum Order Quantity CH7216A-BF 68 QFN, Lead-free None Commercial : 0 to 70C 260/Tray CH7216A-BFK 68 QFN, Lead-free HDCP 1.4 / 2.3 Commercial : 0 to 70C 260/Tray CH7216A-BFI 68 QFN, Lead-free None Industrial : -40 to 85C 260/Tray CH7216A-BFIK 68 QFN, Lead-free HDCP 1.4 / 2.3 Industrial : -40 to 85C 260/Tray Chrontel www.chrontel.com E-mail: sales@chrontel.com 2021 Chrontel - All Rights Reserved.