CH7102A CHRONTEL | Alldatasheet
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Technical content
209-1000-049 Rev 1.4 2021-5-20 1 Chrontel CH7102A HDMI to BT656 Converter FEATURES GENERAL DESCRIPTION HDMI Receiver compliant with HDMI 1.4 specification Support ITU-R 601 or ITU-R 656 compatible YCbCr 4:2:2 output format with embedded syncs or discrete syncs. Support resolution up to 1280 x 720@60Hz or 1920x1080@30Hz for YCbCr 4:2:2 output On-chip Audio encoder which support 2 channel IIS/ S/PDIF audio output Optional HDCP 1.4 specification supported MCU embedded to handle the control logic Support device boot up by automatically loading firmware from on-chip flash Integrated EDID Buffer Crystal Free architecture HDMI input detection supported Support Auto Power Saving mode and low stand-by current Support RGB to YCC conversion in ITU-R BT.601 and 709 color space IIC slave interface and HDMI DDC interface are available for configuration and firmware update. Low power architecture RoHS compliant and Halogen free package Offered in 40-Pin QFN package (5 x 5 mm) APPLICATION Car Infotainment Device Notbook/Ultrabook Tablet Device Handheld/Portable Device Digital Video Systems Chrontel’s CH7102A is a low -cost, low -power semiconductor device that consists of HDMI receiver, YCbCr 4:2:2 encoder and audio encoder , which can convert HDMI signals into 8 bit YCbCr 4:2:2 outputs with IIS or SPDIF audio output. The HDMI Receiver integrated is compliant with HDMI 1.4b. With sophisticated MCU and the On-chip Flash , CH7102A support s auto-boot and programmable EDID ROM. Leveraging the firmware auto loaded from the embedded Flash, CH7102A can support HDMI input detection enter into Power saving mode automatically.
2 209-1000-049 Rev 1.4 2021-5-20 IIS / SPDIF H/V/DE DO[7:0] DDC HPD TMDS HPD Generator HDMI 1.4 RX Sync Generator CSC Video FIFO Audio FIFO Audio Encoder YCbCr 4:2:2 Encoder GCLK MCU & EDID Buffer IIC Slave SPC/SPD On Chip Flash Equalization Optional HDCP Figure 1: CH7102A Functional Block Diagram
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1.0 PIN-OUT
1.1 Package Diagram
DDC_SCL DDC_SDA MCLK RB DVDD DGND SD/SPDIF WS SCLK SPD0 VO HO DEO DO0 CLKO DVDD DGND SPC0 AVCC DO1 DO5 DO7 DO3 RBIAS AVCC DO6 DO4 DO2 HPD RD2P RD2N RD1N AVDD AVCC RD0P RCP RCN RD0N RD1P Figure 2: CH7102A 40-Pin QFN Pin Out
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1.2 Pin Description
Table 1: Pin Name Descriptions Pin # Type Symbol Description
4 In DDC_SCL Serial Port Clock to HDMI/DVI Transmitter
This pin functions as the clock bus of the serial port to HDMI or DVI DDC transmitter. This pin require s a pull -up 47 kΩ resistor to the desired voltage level.
5 In/out DDC_SDA Serial Port Data to HDMI/DVI Transmitter
This pin functions as the data bus of the serial port to HDMI or DVI DDC transmitter. This pin require s a pull -up 47 kΩ resistor to the desired voltage level.
6 Out SD/SPDIF I2S Serial Data or SPDIF Output
7 Out WS I2S Word Select
8 Out SCLK I2S Continuous Serial Clock
9 Out MCLK I2S System Clock
10 In RB Chip Reset
Low to 0V for reset. Typical High level is 3.3V
12 In SPC0 Serial Port Clock Input
This pin functions as the clock pin of the serial port. External pull -up
6.8 K resister is required
13 In/out SPD0 Serial Port Data Input / Output
This pin functions as the bi -directional dat a pin of the serial port. External pull-up 6.8 K resister is required
14 Out VO VSYNC Output of BT656
15 Out HO HSYNC Output of BT656
16 Out DEO Data Enable Output of BT656
17 Out CLKO Clock Output of BT656
20~27 Out DO0~DO7 BT656 Data Output
29 In RBIAS Current Set Resistor Input
This pin sets the DAC current. A 10 K, 1% tolerance resistor should be connected between this pin and AVSS using short and wide traces
30 Out HPD HDMI Receiver Hot Plug output
31,32,33, 34,36,37, 39,40 In RD [2:0] P/N RCP/N HDMI TMDS Input HDMI differential clock and data input pairs 1 Power VDDPLL PLL Power Supply (1.2V) 2,18 Power DVDD Digital IO Power Supply (1.2V) 3,19 Power DGND Digital Ground 11,28,38 Power AVCC Analog Power Supply (3.3V) 35 Power AVDD HDMI Receiver Analog Power Supply (1.2V) Pad Power GND Power Supply Ground
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2.0 PACKAGE DIMENSION
Figure 3: 40 Pin QFN Package Table 2: Table of Dimensions No. of Leads SYMBOL 40 (5 X 5 mm) A B C D E F G H I Milli- meters Notes: 1. Conforms to JEDEC standard JESD-30 MO-220.
6 209-1000-049 Rev 1.4 2021-5-20 Disclaimer This document provides technical information for the user . Chrontel reserves the right to make changes at any time without notice to improve and supply the best possible product and is not responsible and does not assume any liability for misapplication or use outside the limits specified in this document. CHRONTEL warrants each part to be free from defects in material and workmanship for a period of one (1) year from date of shipment. Chrontel assumes no liability for errors contained within this document. The customer should make sure that they have the mo st recent data sheet version. Customers should take appropriate action to ensure their use of the products does not infringe upon any patents. Chrontel, Inc. respects valid patent rights of third parties and does not infringe upon or assist others to infringe upon such rights. Chrontel PRODUCTS ARE NOT AUTHORIZED FOR AND SHOULD NOT BE USED WITHIN LIFE SUPPORT SYSTEMS OR NUCLEAR FACILITY APPLICATIONS WITHOUT THE SPECIFIC WRITTEN CONSENT OF Chrontel. Life support systems are those intended to support or s ustain life and whose failure to perform when used as directed can reasonably expect to result in personal injury or death.
ORDERING INFORMATION
Part Number Package Type Content Protection Operating Temperature Range Minimum Order Quantity CH7102A-BF 40 QFN, Lead-free None Commercial : 0 to 70C 490/Tray CH7102A -BFK 40 QFN, Lead-free HDCP 1.4 Commercial : 0 to 70C 490/Tray CH7102A -BFI 40 QFN, Lead-free None Industrial : -40 to 85C 490/Tray CH7102A -BFIK 40 QFN, Lead-free HDCP 1.4 Industrial : -40 to 85C 490/Tray Chrontel www.chrontel.com E-mail: sales@chrontel.com 2021 Chrontel - All Rights Reserved.