CH1115

CH1115 CHIPWEALTH | Alldatasheet

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Features

 Support maximum 1 28 X 64 dot matrix panel  Embedded 128 X 64 bit s SRAM  Operating voltage: - Logic voltage supply : V DD 1 = 1.65V - 3.5V - DC - DC voltage supply : V DD 2 = 3.0 V - 4. 7 5 V - OLED Operating voltage supply: External V PP supply = 6.4 V - 1 4 .0V Internal V PP generator = 7 . 4 V – 10 . 0 V  Typical segment output current: 3 00  A  Maximum segment output current: 500  A  Typical common sink current: 38.4 mA  Maximum common sink current: 6 4 mA  8 - bit 6800 - series parallel interface, 8 - bit 8080 - series parallel interfa ce, serial 3 - wire & 4 - wire s erial p eripheral i nterface , 400KHz fast I 2 C bus interface  Programmable f rame f requency and multiplexing r atio  C ontinuous horizontal s croll  Single s creen horizontal scroll  Internal or external I REF selection  Row non - overlap  Bre athing Display Effect  Adjust I SEG by pad ( D2 - D7 )  Row r e - mapping and c olumn r e - mapping (ADC)  V ertical s croll  On - c hip o scillator  Programmable I nternal charge pump circuit output  256 - step c ontrast c ontrol on monochrome passive OLED panel  Adaptive Power Save  Low power consumption - Sleep mode: <5  A - VDD1 =0V ， VDD2 = 3.0 V – 4. 7 5 V : < 5  A - VDD1,2=0V ， VPP= 6.4 V – 1 4 .0 V : <5  A  Wide range of operating temperatures: - 40 to + 85  C  Available in COG form , thickness: 300  m General Description CH1115 is a single - chip CMOS OLED/PLED dr iver with controller for organic/polymer light emitting diode dot - matrix graphic display system. CH1115 consists of 128 segments , 64 commons that can support a maximum display resolution of 128 X 64. It is designed for Common Cathode type OLED panel. CH11 15 embeds with contrast control, display RAM oscillator and efficient DC - DC converter , which reduces the number of external components and power consumption. CH1115 is suitable for a wide range of compact portable applications, such as sub - display of mobil e phone, calculator and MP3 player , etc.

2 V0.3 Block Diagram Display data latch 1 28 X 64 - dots Display Data RAM l i n e a d d r e s s d e c o d e r I / O b u f f e r c i r c u i t Output status selector circuit Column address decoder 8 - bit column address counter 8 - bit column address counter Page Address Register Display Timing Generator Circuit CL L i n e c o u n t e r I n i t i a l d i s p l a y l i n e r e g i s t e r V BREF Segment driver Common driver Shift register Power supply circuit I REF V COMH V CL V SL V DD 1 V SS SEG 0 SEG 127 COM 0 COM 63 V DD 2 Bus Holder Command Decoder Bus Holder Oscillator I / O Buffer CLS ( SI / SDA ) ( SCL ) D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 Microprocessor Interface RES IM 2 ( R / W ) ( E ) IM 1 WR RD A 0 CS ( SA 0 ) Charge Pump C 1 N V PP C 1 P C 2 N C 2 P IM 0

3 V0.3 P ad Description Power Supply Symbol I/O Description V DD 1 Supply Power supply input: 1.65 - 3. 5V V DD 2 Supply 3.0 – 4. 7 5 V power supply pad for Power supply for charge pu mp circuit. T h is pin should be disconnected when V PP is supplied externally V SS Supply Ground . V SL Supply This is a segment voltage reference pad. This pad should be connected to V SS externally . V CL Supply This is a common voltage reference pad. T his pad should be connected to V SS externally . O L E D Driver Supplies Symbol I/O Description I REF O This is a segment current reference pad. A resistor should be connected between this pad and V SS . Set the current at 1 8.75  A . V COMH O This is a pad for the voltage output high level for common signals. A capacitor should be connected between this pad and V SS . V BREF NC This is an internal voltage reference pad for booster circuit. K eep floating. V PP P OLED panel power supply . Generated by internal charge pump. Connect to capacitor . It could be supplied externally . C 1N, C1P P Connect to c harge pump capacitor . T h ese pin s are not used and should be disconne c ted when Vpp is supplied externally. C 2P, C2N P Connect to c harge pump capacitor . T h ese pin s are n ot used and should be disconne c ted when Vpp is supplied externally.

4 V0.3 System Bus Connection Pads Symbol I/O Description CL I/O This pad is the system clock input. When internal clock is enabled, this pad should be L eft open. The internal clock is output from this pad. When internal oscillator is disabled, this pad receives display clock signal from external clock source. CLS I This is the internal clock enable pad. CLS = “H”: Internal oscillator circuit is enabled . CLS = “L”: Internal oscillator circu it is disabled (requires external input). When CLS = “L”, an external clock source must be connected to the CL pad for normal operation. IM0 IM1 IM2 I Th ese are the MPU interface mode select pad s .

8080 I 2 C 6800 4 - wire SPI 3 - wire SPI

CS I This pad is the chip select input. When CS = “ L”, then the chip select becomes active, and data/command I/O is enabled. RES I This is a reset signal input pad . When RES is set to “L”, the settings are initialized. The reset operation is performed by the RES signal level. A0 I This is the Data/Command control pad that determines whether the data bits are data or a command. A0 = “H”: the inputs at D0 to D7 are treated as display data. A0 = “L”: the inputs at D0 to D7 are transferred to the command registers . In I 2 C interface, this pad serves as SA0 to distinguish the different address of OLED driver. WR ( W R / ) I This is a M P U interface input pad . When connected to an 8080 MPU, this is active LOW. This pad connects to the 8080 MPU WR signal. The signals on the data bus are latched at the rising edge of the WR signal. When connected to a 6800 Series MPU: This is the read/write control signal input terminal. When W R / = “ H”: Read. W hen W R / = “ L”: Write. RD (E) I This is a M P U interface input pad . When connected to an 8080 series MPU, it is active LOW. This pad is connected to the RD signal of the 8080 series MPU, and the data bus is in an output status when this signal is “L”. When connected to a 6800 series MPU , t his is active HIGH. This is used as an enable clock input of the 6800 series MPU. When RD = “H”: Enable . When RD = “L”: Disable . D 0 - D 7 (SCL) (SI /SDA ) I/O I I /O This is an 8 - bit bi - directional data bus that conn ects to an 8 - bit or 16 - bit standard MPU data bus. When the serial interface is selected, then D0 serves as the serial clock input pad (SCL) and D1 serves as the serial data input pad (SI). At this time, D2 to D7 are set to high impedance. When the I 2 C inte rface is selected, then D0 serves as the serial clock input pad (SCL) and D1 serves as the serial data input pad (S DA ). At this time, D2 to D7 are set to high impedance.

5 V0.3 OLED Drive Pads Symbol I/O Description SEG 0 ,2, - 12 6 O These pads are even Segment signal output for OLED display. SEG 1,3 - 12 7 O These pads are odd Segment signal output for OLED display. COM 0 - 63 O These pads are Common signal output for OLED display. Test Pads Symbol I/O Description TEST1 - 3 I Test pad, internal pull low, no connec tion for user. Dummy - These pads are not used. K eep floating.

6 V0.3 Pad Configuration Chip Outline Dimensions Item Pad No. Size ( µ m) X Y Chip boundary - 6 44 0 68 4 Chip height All pads 300 Bump size I/O 40 80 SEG 15 110 COM 15 110 110 15 Pad pitch COM 30 SEG 28 .05 I/O 55 Bump height All pads 9 ± 2 Alignment Mark Location unit : µm NO X Y ALK_ L - 3157 - 28 8 ALK_ R 3157 - 28 8

7 V0.3 Functional Description Microprocessor Interface Selection The 8080 - Parallel Interface , 6800 - Parallel Interface, Serial Interface (SPI) or I 2 C Interface can be s elected by different selections of IM0~2 as shown in Table 1. Table. 1 Interface Config Data signal C ontrol signal IM0 IM1 IM2 D7 D6 D5 D4 D3 D2 D1 D0 E / RD WR CS A0 RES 6800 0 0 1 D7 D6 D5 D4 D3 D2 D1 D0 E W R / CS A0 RES 8080 0 1 1 D7 D6 D5 D4 D3 D2 D1 D0 RD WR CS A0 RES 4 - Wire SPI 0 0 0 H z （ Note1) SI SCL Pull High or Low CS A0 RES 3 - Wire SPI 1 0 0 H z （ Note1) SI SCL Pull High or Low CS Pull Low RES I 2 C 0 1 0 H z （ Note1) S DA SCL Pull High or Low Pull Low SA0 RES Note1 : When Serial Interface (SPI) or I 2 C Interface is selected, D7~D2 is H z . D7~ D2 is recommended to connect the V DD1 or V SS . It is also allowed to leave D7~ D2 unconnected . 6800 - series Parallel In terface The parallel interface consists of 8 bi - directional data pads (D 7 - D 0 ), W R / , E , A0 and CS . It includes 2 forms. Form 1: A falling edge of E input serve as READ latch signal while CS is kept low and W R / is kept high. A falling edge of E input serve as WRITE latch signal while CS is kept low and W R / is kept low. This is shown in Table.2 below. Table.2 - Control pins of 6800 int erface (Form 1) Function CS A0 W R / E Write command L L L ↓ Read status L L H ↓ Write data L H L ↓ Read data L H H ↓ 1. ’ ↓ ‘ stands for falling edge of signal. 2. ’ H ‘ stands for high in signal, ‘ L ’ stands for low in signal.

8 V0.3 Figure. 1 Example of write procedure in 6800 para llel interface form 1 Figure. 2 Example of read procedure in 6800 parallel interface form 1

9 V0.3 Form 2: A rising edge of CS input serve as READ latch signal while E is kept high and W R / is kept high . A rising edge of CS input serve as WRITE latch signal while E is kept high and W R / is kept low. A low in A0 indicates COMMAND read/write and high in A0 indicates DATA read/write. This i s shown in Table.3 below. Table.3 - Control pins of 6800 interface (Form 2) Function CS A0 W R / E Write command ↑ L L H Read status ↑ L H H Write data ↑ H L H Read data ↑ H H H Note: 1. ’ ↓ ‘ stands for falling ed ge of signal. 2. ’ H ‘ stands for high in signal, ‘ L ’ stands for low in signal. Figure. 3 Example of write procedure in 6800 parallel interface form 2

10 V0.3 Figure. 4 Example of read proc edure in 6800 parallel interface form 2 In order to match the operating frequency of display RAM with that of the microprocessor, some pipeline processing are internally performed, which require the insertion of a dummy read before the first actual displ ay data read. This is shown in Figure. 5 Read data process – insertion of dummy read

11 V0.3 8080 - series Parallel Interface The parallel interface consists of 8 bi - directional data pads (D 7 - D 0 ), WR , RD , A0 and CS . It includes 2 forms. Form 1: A rising edge of RD input serve as data READ latch signal while CS is kept low. A rising edge of WR input serve as da ta READ latch signal while CS is kept low. A low in A0 indicates COMMAND read/write and high in A0 indicates DATA read/write. This is shown in Table.4 below. Table.4 - Control pins of 8080 interface (Form 1) Function CS A0 RD WR Write command L L H ↑ Read status L L ↑ H Write data L H H ↑ Read data L H ↑ H Note: 1. ’ ↑ ‘ stands for rising edge of signal. 2. ’ H ‘ stands for high in signal, ‘ L ’ stands for low in signal. Figure. 6 Example of write procedure in 8080 p arallel interface form 1

12 V0.3 Figure. 7 Example of read procedure in 8080 parallel interface form 1 Form 2: A rising edge of CS input serve as data READ latch signal while RD is kept l ow. A rising edge of CS input serve as data READ latch signal while WR is kept low. A low in A0 indicates COMMAND read/write and high in A0 indicates DATA read/write. This is shown in Table.5 below. Table.5 - Control pins of 8080 interface (Form 2) Function CS A0 RD WR Write command ↑ L H L Read status ↑ L L H Write data ↑ H H L Read data ↑ H L H

13 V0.3 Figure.8 Examp le of write procedure in 8080 parallel interface form 2 CS A 0 RD WR low D [ 7 : 0 ] high Figure.9 Example of read procedure in 8080 parallel interface form 2 In order to match the operating frequency of display RAM with that of the microprocessor, some p ipeline processing are internally performed, which require the insertion of a dummy read before the first actual display data read. This is shown in

14 V0.3 Figure.10 Read data process – insertion of dummy read

15 V0.3

4 Wire Serial Interfa ce ( 4 - wire SPI)

The serial interface consists of serial clock SCL, serial data SI, A0 and CS . SI is shifted into an 8 - bit shift register on every rising edge of SCL in the order of D 7 , D6, … and D 0 . A0 is sampled on every eighth clock and the data byte in the shift register is written to the d isplay d ata RAM (A0=1) or command register (A0=0) in the same clock. See Figure .11 Table. 6 IM0 IM1 IM2 Type CS A0 RD WR D0 D1 D2 to D7 0 0 0 4 - wire SPI CS A0 - - SCL SI (H z ) Note: “ - ” pin m ust always be HIGH or LOW . D7~ D2 is recommended to connect the V DD1 or V SS . It is also allowed to leave D7~ D2 unconnected . The serial interface is initialized when CS is high. In this state, SCL clock pulse or SDI data have no effect. A falling edge on CS enables the serial interface and indicates the start of data transmission. The SPI is also able to work properly when the CS always keep low , b ut it is not recomm ended. SI (D1) CS 1 2 3 4 5 6 7 8 9 10 11 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 SCL(D0) Figure .11 4 - wire SPI data transfer When the chip is not active, the shift registers and the counter are reset to their initial statuses. Read is not possible while i n serial interface mode. Caution is required on the SCL signal when it comes to line - end reflections and external noise. We recommend the operation be rechecked on the actual equipment.

16 V0.3

3 Wire Serial Interface ( 3 - wire SPI)

The 3 wire serial interface cons ists of serial clock SCL, serial data SI, and CS . SI is shifted into an 9 - bit shift register on every rising edge of SCL in the order of C D / , D 7 , D6, … and D 0 . The C D / bit (first of the 9 bit) wi ll determine the transferred data is written to the d isplay d ata RAM ( C D / =1) or command register ( C D / =0) . Table. 7 IM0 IM1 IM2 Type CS A0 RD WR D0 D1 D 2 to D7 1 0 0 3 - wire SPI CS Pull Low - - SCL SI (H z ) Note: “ - ” pin m ust always be HIGH or LOW . D7~ D2 is recommended to connect the V DD1 or V SS . It is also allowed to leave D7~ D2 unconnected . The serial interface is initialized whe n CS is high. In this state, SCL clock pulse or SDI data have no effect. A falling edge on CS enables the serial interface and indicates the start of data transmission. The SPI is also able to work properly when the CS always keep low , b ut it is not recomm ended. SI ( D 1 ) CS 1 2 3 4 5 6 7 8 9 10 11 D / C D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 D / C D 7 SCL ( D 0 ) Figure. 1 2 3 - wire SPI data transfer When the chip is not active, the shift registers and the counter are reset to their initial statuses. Read is not pos sible while in serial interface mode. Caution is required on the SCL signal when it comes to line - end reflections and external noise. We recommend the operation be rechecked on the actual equipment. I 2 C - bus Interface The CH1115 can transfer data via a stan dard I 2 C - bus and has slave mode only in communication. The command or RAM data can be written into the chip and the status and RAM data can be read out of the chip. Note: “ - ” pin m ust always be HIGH or LOW . D7~ D2 is recommended to connect the V DD1 or V SS . It is also allowed to leave D7~ D2 unconnected . CS signal could always pu ll low in I 2 C - bus application. Characteristics of the I 2 C - bus The I 2 C - bus is for bi - directional, two - line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull - up resistor. Data transfer may be initiated only when the bus is not busy. Note: The positive supply of pull - up resistor must equal to the value of V DD1 . IM0 IM1 IM2 Type CS A0 RD WR D0 D1 D2 to D7 0 1 0 I 2 C Interface Pull Low SA 0 - - SCL SDA (H z )

17 V0.3 Bit Transfer One data bit is transferred during each clock pulse. Th e data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as a control signal. SDA SCL Data line stable: Data valid Change data allowed Figure. 1 3 Bit Transfer Start and Stop conditions Both data and clock lines remain HIGH when the bus is not busy. A HIGH - to - LOW transition of the data line, while the clock is HIGH is defined as the START condition (S). A LOW - to - HIGH transition of the data line while the clock is HIGH is defined as the STOP conditi on (P). SDA SCL SDA SCL START condition STOP condition S P Figure. 1 4 Start and Stop conditions System configuration  Transmitter: The device that sends the data to the bus.  R eceiver: The device that receives the data from the bus.  M aster: The device that initiates a transfer , generates clock signals and terminates a transfer.  Slave: The device addressed by a master.  Multi - Master: More than one master can attempt to control the bus at the same time without corrupting the message  Arbitration: Procedure to ensure that, if more tha n one master simultaneously tries to control the bus, only one is allowed to do so and the message is not corrupted.  Synchronization: Procedure to synchronize the clock signals of two or more devices. MASTER TRANSMITTER /RECEIVER SLAVE RECEIVER SLAVE TRANSMITTER /RECEIVER MASTER TRANSMITTER MASTER TRANSMITTER /RECEIVER SDA SCL Figure . 1 5 System configu ration

18 V0.3 Acknowledge Each byte of eight bits is followed by an acknowledge bit. The acknowledge bit is a HIGH signal put on the bus by the transmitter during which time the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges must pull - down t he SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse (set - up and hold times must be taken into consideration). A master receiver must signal an end of data to the t ransmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event the transmitter must leave the data line HIGH to enable the master to generate a stop condition. S 1 2 8 9 START condition clock pulse for acknowledgement acknowledge not acknowledge DATA OUTPUT BY TRANSMITTER DATA OUTPUT BY RECEIVER SCL FROM MASTER Figure .1 6 Ackn owledge Protocol The CH1115 supports both read and write access. The W R/ bit is part of the slave address. Before any data is transmitted on the I C - bus, the device that should respond is addressed first. Two 7 - bit slave addresses (0111 100 and 0111101) are reserved for the CH1115 . The least significant bit of the slave address is set by connecting the input SA0 to either logic 0(VSS) or 1 (VDD 1 ). The I C - bus protocol is illustrated in Fig. 16 . The sequence is initiated with a START condit ion (S) from the I C - bus master that is followed by the slave address. All slaves with the corresponding address acknowledge in parallel, all the othe rs will ignore the I C - bus transfer. After acknowledgement, one or more command words follow which define the status of the addressed slaves. A command word consists of a control byte, which defines Co and C D / (note1) , plus a data byte (see Fig. 16 ). The last control byte is tagged with a cleared most significant bit, the continuation bit Co. After a control byte with a cleared Co - bit, only data bytes will follow. The state of the C D / - bit defines whether the data - byte is interpreted as a command or as RAM - data. The control and data bytes are also acknowledged by all address ed slaves on the bus. After the last control byte, depending on the C D / bit setting, either a series of display data bytes or command data bytes may follow. If the C D / bit was set to ‘1’, these display bytes are store d in the display RAM at the address specified by the data pointer. The data pointer is automatically updated and the data is directed to the intended CH1115 device. If the C D / bit of the last control byte was set to ‘0’, these command b ytes will be decoded and the setting of the device will be changed according to the received commands. The acknowledgement after each byte is made only by the addressed slave. At the end of the transmission the I C - bus master issues a stop condition (P). I f the W R/ bit is set to one in the slave - address, the chip will output data immediately after the slave - address according to the C D / bit, which was sent during the last write access. If no acknowledge is generated by the master after a byte, the driver stops transferring data to the master.

19 V0.3 S 0 1 1 1 1 0 S A

1 A data byte A data byte A data byte A data byte A P

A 1 DC control byte A data byte A 0 DC control byte A data byte S 0 1 1 1 1 0 S A

0 A P

2n>=0 bytes 1 byte n>=0 bytes slave address C 0 WRITE R W 0 1 1 1 1 0 S A A C 0 DC 0 0 0 0 0 0 slave address Control Byte C 0 S - start condition P - stop condition A - Acknowledge A - Not Acknowledge M - I 2 C master S' - I 2 C slave from S' from S' from S' from S' from S' from S' from M from M from M from M Figure .1 7 I 2 C Protocol Note1: 1. Co ＝ “ 0 ” : The last control byte , only data bytes to follow , Co ＝ “ 1 ” : Next two bytes are a data byte and another control b yte ; 2. C D / ＝ “ 0 ” : The data byte is for command operation, C D / ＝ “ 1 ” : The data byte is for RAM operation. Access to Display Data RAM and Internal Registers This module determines whether the input data is interpreted as dat a or command. When A0 = “H”, the inputs at D 7 - D 0 are interpreted as dat a and be written to display RAM . When A0 = “L” , the inputs at D 7 - D0 are interpreted as command, they will be decoded and be written to the corresponding command registers. Display D ata RAM The Display Data RAM is a bit mapped static RAM holding the bit pattern to be displayed. The size of the RAM is 128 X 64 bits. For mechanical flexibility, re - mapping on both s egment and c ommon outputs can be selected by software. For vertical scr olling of the display, an internal register storing display start line can be set to control the portion of the RAM data to be mapped to the display.

20 V0.3 The Page Address Circuit As shown in Figure. 18 , page address of the display data RAM is specified through the Page Address Set Command. The page address must be specified again when changing pages to perform access. The Column Address As shown in Figure.18 , the display data RAM column address is specified by the Colum n Address Set command. The specified column address is incremented (+1) with each display data read/ write command. This allows the MPU display data to be accessed continuously. Because the column address is independent of the page address, when moving, fo r example, from page0 column 7FH to page 1 column 00H, it is necessary to re - specify both the page address and the column address. Furthermore, as shown in Table. 8 , the Column r e - mapping (ADC) command (segment driver direction select command) can be used to reverse the relationship between the display data RAM column address and the segment output. Because of this, the constraints on the IC layout when the OLED module is assembled can be minimized. Table. 8 Segment Output SEG0 SEG 128 ADC “0” 0 (H)  Col umn Address  7F (H) ADC “1” 7F (H)  Column Address  0 (H) The Line Address Circuit The line address circuit, as shown in Figure.1 8 , specifies the line address relating to the common output when the contents of the display data RAM are displayed. Using the display start line address set command, what is normally the top line of the display can be specified (this is the COM0 output when the common output mode is normal, and the COM63 output for CH1115 , when the common output mode is reversed. The display area is a 64 - line area for the CH1115 from the display start line address. If the line addresses are changed dynamically using the display start line address set command, screen scrolling, page swapping, etc. that can be performed relationship between dis play data RAM and address (if initial display line is 1DH).

21 V0.3 OUTPUT COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM17 COM18 COM19 COM20 COM21 COM22 COM23 COM24 COM25 COM26 COM27 COM28 COM29 COM30 COM31 COM32 COM33 COM34 COM35 COM36 COM37 COM38 COM39 COM40 COM41 COM42 COM43 COM44 COM45 COM46 COM47 COM48 COM49 COM50 COM51 COM52 COM53 COM54 COM55 COM56 COM57 COM58 COM59 COM60 COM61 COM62 COM63 Line Address 00H D3 D2 D1 D0 01H 02H 0 0 0 0 03H 04H 05H 06H 07H 08H D3 D2 D1 D0 09H 0AH 0 0 0 1 0BH 0CH 0DH 0EH 0FH 10H D3 D2 D1 D0 11H 12H 0 0 1 0 13H 14H 15H 16H 17H 18H D3 D2 D1 D0 19H 1AH 0 0 1 1 1BH 1CH 1DH 1EH 1FH 20H D3 D2 D1 D0 21H 22H 0 1 0 0 23H 24H 25H 26H 27H 28H D3 D2 D1 D0 29H 2AH 0 1 0 1 2BH 2CH 2DH 2EH 2FH 30H D3 D2 D1 D0 31H 32H 0 1 1 0 33H 34H 35H 36H 37H 38H D3 D2 D1 D0 39H 3AH 0 1 1 1 3BH 3CH 3DH 3EH 3FH D0=”0” 00H 01H 02H 7DH 7EH 7FH D0=”1” 7FH 7DH 7DH 02H 01H 00H SEG0 SEG1 SEG2 SEG125 SEG126 SEG127 Column Address ADC Page Address D5 LCD OUT PAGE6 PAGE7 Data PAGE 0 PAGE1 PAGE3 PAGE2 PAGE4 PAGE5 Figure. 18

22 V0.3 The Oscillator Circuit This is a RC type oscillator ( Figure .1 9 ) that produces the display clock. The oscillator circuit is only enabled when CLS = “H”. When CLS = “L”, the oscillation stops and the display clock is input ted through the CL terminal. MUX Internal OSC CL CLK DIVIDER DCLK Internal Display Clock CLS Figure .1 9

23 V0.3 Charge Pump Regulator This block accompanying only 2 external capacitors , i s used to generate a 7 .4V~ 10 .0 V voltage for OLED panel. This regulator can be turned ON/OFF by software command 8 B h setting. Charge Pump output voltage control T his block is used to set the voltage value of charge r pump output. T he driving voltage can be adjusted from 7 . 4 V up to 10 .0V. This used to meet different demand of the panel. Current Control and Voltage Control This block is used to derive the incoming power sources into different levels of internal use voltage and current. V PP and VDD 2 are exte rnal power supplies. I REF is a reference current source for segment current drivers. Common Drivers/Segment Drivers Segment drivers deliver 128 current sources to drive OLED panel. The driving current can be adjusted up to 500  A with 256 steps. Common dri vers generate voltage scanning pulses. Reset Circuit When the RES input falls to “L” , these reenter their default state. The default settings are shown below: 1. Display is OFF . Common and segment are in high impedance state . 2. 128 X 64 Display mode. 3. Normal segment and display data column address and row address mapping (SEG 0 is mapped to column address 00 H and COM 0 mapped to row address 00 H) . 4. Shift register data clear in serial interface . 5. Display start line is set at display RAM line address 0 0H. 6. Column address counter is set at 0 . 7. Normal scanning direction of the common outputs . 8. Contrast control register is set at 80H . 9. Internal DC - DC is selected .

24 V0.3 Commands The CH1115 uses a combination of A0, RD (E) and WR ( W R / ) signals to identify data bus signals. As the chip analyzes and executes each command using internal timing clock only regardless of external clock, its processing speed is very high and it s busy ch eck is usually not required. The 8080 series microprocessor interface enters a read status when a low pulse is input to the RD pad and a write status when a low pulse is input to the WR pad. The 6800 series micropro cessor interface enters a read status when a high pulse is input to the W R / pad and a write status when a low pulse is input to this pad. When a high pulse is input to the E pad, the command is activated. (For timing, see AC Characteris tics.). Accordingly, in the command explanation and command table, RD (E) becomes 1(HIGH) when the 6800 series microprocessor interface reads status of display data. This is an only different point from the 8080 series microprocessor i nterface. Taking the 8080 series, microprocessor interface as an example command will explain below. When the serial interface is selected, input data starting from D7 in sequence. Command Set 1. Set Lower Column Address: (00H - 0FH) 2. Set Higher Column Address: (10H – 1 F H) Specifies column address of display R AM. Divide the column address into 4 higher bits and 4 lower bits. Set each of them into succession s . When the microprocessor repeats to access to the display RAM, the column address counter is incr emented during each access until address 127 is accessed. The page address is not changed during this time. A0 E RD W R / WR D7 D6 D5 D4 D3 D2 D1 D0 Higher bits 0 1 0 0 0 0 1 0 A6 A5 A4 Lower bi ts 0 1 0 0 0 0 0 A3 A2 A1 A0 A6 A5 A4 A3 A2 A1 A0 Display address 0 0 0 0 0 0 0 0 (POR) 0 0 0 0 0 0 1 1 : : 1 1 1 1 1 1 1 127 Note: Don’t use any commands not mentioned above.

25 V0.3 3. Set Breathing Display Effect : (Double Bytes Command) This c ommand set Breathing Display Effect ON/OFF and Time Interval .  Breathing Light Set: ( 23 H) A0 E RD W R / WR D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 0 0 1 0 0 0 1 1 0 1 0 ON/ OFF * * A4 A3 A2 A 1 A0  ON/OFF se t: When ON/OFF =”L”, Breathing Light OFF . (POR) When ON/OFF =”H”, Breathing Light ON .  Breathing Display Effect Maximum B rightness Adjust Set: ( A4 – A3 ) A 4 A 3 Maximum B rightness (Contrast+1) 0 0 256 (POR) 0 1 128 1 0 64 1 1 32  Breathing Display Eff ect Time Interval Set: ( A2 – A0 ) A 2 A 1 A 0 Time Interval step 0 0 0 1 Frames 0 0 1 2 Frames (POR) 0 1 0 3 Frames : : : : 1 1 0 7 Frames 1 1 1 8 Frames CHIP CHIP CHIP CHIP CHIP CHIP Figure .20

26 V0.3 4 . Additional Horizontal Scroll Setup : (Three Bytes Co mmand) This command consists of 3 consecutive bytes to set up the horizontal scroll parameters. It determined the scrolling start column position and end column position. The end column position must be larger than start column position.  Additional Horizon tal Scroll Setup Mode Set: (24H) A0 E RD W R / WR D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 0 0 1 0 0 1 0 0 0 1 0 A7 A6 A5 A4 A3 A2 A1 A 0 0 1 0 B7 B6 B5 B4 B3 B2 B1 B0  Start Column Position Set: ( A7 – A0 ) A0 E RD W R / WR D7 D6 D5 D4 D3 D2 D1 D0 Column Position 0 1 0 * 0 0 0 0 0 0 0 0 (POR) 0 1 0 * 0 0 0 0 0 0 1 1 0 1 0 : : 0 1 0 * 1 1 1 1 1 1 0 126 0 1 0 * 1 1 1 1 1 1 1 127  End Colum n Position Set: ( B7 – B0 ) A0 E RD W R / WR D7 D6 D5 D4 D3 D2 D1 D0 Column Position 0 1 0 * 0 0 0 0 0 0 0 0 0 1 0 * 0 0 0 0 0 0 1 1 0 1 0 : : 0 1 0 * 1 1 1 1 1 1 0 126 0 1 0 * 1 1 1 1 1 1 1 127 (POR) Note: “*” stands for “Don’t care”. Please see the f ollowing f igure for relationship of start column position and end column position . CHIP Start column Position End column Position 0 127 CHIP Start page address End page address Figure .21

27 V0.3 5 . Horizontal Scroll Setup: ( Four Bytes Command) This command co nsists of 4 consecutive bytes to set up the horizontal scroll parameters. It determined the number of horizontal scroll per step , scrolling start page, time interval and end page. Before issuing this command, the horizontal scroll must be deactivated (2EH ). Otherwise, ram content may be corrupted.  Horizontal Scroll Setup Mode Set: (26H - 27H ) A0 E RD W R / WR D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 0 0 1 0 0 1 1 D 0 1 0 * * * * * A2 A1 A 0 0 1 0 * * * * * C2 C1 C 0 D Scroll Direction Set

0 Scroll Right (POR)

1 Scroll Left

 Start Page Address Set : ( A2 – A0 ) A0 E RD W R / WR D7 D6 D5 D4 D3 D2 D1 D0 Start Page Address 0 1 0 * * * * * 0 0 0 0 (POR) 0 1 0 : :  Time Interval Set : ( B2 – B0 ) A0 E RD W R / WR D7 D6 D5 D4 D3 D2 D1 D0 Tim e Interval 0 1 0 * * * * * 0 0 0 6 frames (POR) 0 1 0 * * * * * 0 0 1 32 frames 0 1 0 * * * * * 0 1 0 64 frames 0 1 0 * * * * * 0 1 1 128 frames 0 1 0 * * * * * 1 0 0 3 frames 0 1 0 * * * * * 1 0 1 4 frames 0 1 0 * * * * * 1 1 0 5 frames 0 1 0 * * * * * 1 1 1 2 frames  End Page Address Set: ( C2 – C0 ) A0 E RD W R / WR D7 D6 D5 D4 D3 D2 D1 D0 End Page Address 0 1 0 : : 0 1 0 * * * * * 1 1 1 7 (POR) Note : “*” stands for “Don’t care”.

28 V0.3 6 . Set Scroll Mode : (2 8 H – 2 B H) C ontrol c ontinuous or single screen scroll . A0 E RD W R / WR D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 0 0 1 0 1 0 D 1 D 0 D 1 D 0 Scroll mode 0 0 Continuous horizontal/vertical scroll (default) 0 1 Single Screen scroll 1 x 1 Column scroll mode  Single column scroll mode The display scroll one column after the 2 B H+2FH c ommand s are written. The scr oll is end after the 2EH c ommand is written . E xample:

29 V0.3 7 . Set Deactivate /Activate Horizontal Scroll: (2EH - 2FH) Stop or start motion of horizontal scrolling. This command should only be issued after horizontal scroll setup parameters (24H/26H/27H/ 28H/29H/ 2CH/2DH) are defined. A0 E RD W R / WR D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 0 0 1 0 1 1 1 D When D=”L”, Sto p motion of horizontal scroll . (POR) When D=”H”, Star t motion of horizontal scroll . Note: The following actions are prohibited after the horizontal scroll is activated  Changing additional horizontal scroll setup parameters.  Changing horizontal scroll setup parameters.  Changing scroll m ode setup parameters . After the deactivate horizontal scroll issued, the display of screen is reset to original status. 8 . Set Pump voltage value : (30H~3 3 H) Specifie s output voltage (V PP ) of the internal charge r pump. A0 E RD W R / WR D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 0 0 1 1 0 0 A1 A0 A1 A0 Pump output voltage (V PP ) 0 0 10.0 0 1 7.4 1 0 8.0(Power on) 1 1 9.0 9 . Set Display Start Line : (40H - 7FH) Specifies line address (refer to Figure. 18 ) to determine the initial display line or COM0. The RAM display data becomes the top line of O L E D screen. It is followed by the higher number of lines in ascending order, corresponding to the duty cycle. When th is command changes the line address, the smooth scrolling or page change takes place. A0 E RD W R / WR D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 0 1 A5 A4 A3 A2 A1 A0 A5 A4 A3 A2 A1 A0 Line address 0 0 0 0 0 0 0 0 0 0 0 0 1 1 : : 1 1 1 1 1 0 62 1 1 1 1 1 1 63

30 V0.3 10 . Set Contrast Control Register : (Double Bytes Command) This command is to set c ontrast s etting of the display. The chip has 256 contrast steps from 00 to FF. The segment output current incr eases as the contrast step value increases. Segment output current setting: I SEG = (  +1) /256 X I REF X scale factor Where:  is contrast step ; Scale factor = 16.  The Contrast Control Mode Set: (81H) When this command is input, the c ontrast data register set command becomes enabled. Once the c ontrast c ontrol mode has been set, no other command except for the c ontrast data register command can be used. Once the c ontrast data set command has been used to set data into the register, then the c ontrast c ontrol mod e is released. A0 E RD W R / WR D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 1 0 0 0 0 0 0 1 0 1 0 A7 A6 A5 A4 A3 A2 A1 A0  Contrast Data Register Set: ( 00H – FFH ) By using this command to set eight bits of da ta to the c ontrast data register; the OLED segment output assumes one of the 256 current levels. When this command is input, the c ontrast c ontrol mode is released after the c ontrast data register has been set. A0 E RD W R / WR D7 D6 D5 D4 D3 D2 D1 D0 I SEG 0 1 0 0 0 0 0 0 0 0 0 Small 0 1 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 1 0 0 1 0 : : 0 1 0 1 0 0 0 0 0 0 0 POR 0 1 0 : : 0 1 0 1 1 1 1 1 1 1 0 0 1 0 1 1 1 1 1 1 1 1 Large Wh en the c ontrast c ontrol function is not used, set the D7 - D0 to 1000,0000.

31 V0.3 11. I REF Resistor S et and Adjust I SEG by PAD : ( Double Bytes Command ) I REF can be controlled by external resister or internal resister.  I REF Resister Set: ( 82H ) A0 E RD W R / WR D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 1 0 0 0 0 0 1 0 0 1 0 ON / OFF * * * * D A 1 A 0 When D = “L”, External resistor is selected ( POR ) . When D = “ H ”, Internal resistor is selected.  I nternal Resistor S et: ( A1 – A0 ) A 1 A 0 Resistor (K) 0 0 510 ( POR ) 0 1 310 1 0 220 1 1 180 W hen VPP=9V, Contrast=255, I REF Resistor & IREF Table(Just for reference): I REF Resistor (K) I REF (uA) I SEG (uA) 360 12.50 200 160 18.75 300 70 25.0 400 30 31.25 500  Adjust I S EG by PAD[6:2] When ON/OFF = “L”, Disable I SEG adjust. (POR). When ON/OFF = “H”, Enable I SEG adjust . I SEG change with the value of D2 - D 6 pin. Step number D6 D5 D4 D3 D2 I SEG adjust U p 0 0 0 0 0 0 0% 1 0 0 0 0 1 3% 2 0 0 0 1 0 6% 3 0 0 0 1 1 9% 4 0 0 1 0 0 12% 5 0 0 1 0 1 15% 6 0 0 1 1 0 18% 7 0 0 1 1 1 21% 8 0 1 0 0 0 24% 9 0 1 0 0 1 27% 10 0 1 0 1 0 30% 11 0 1 0 1 1 33% 12 0 1 1 0 0 36% 13 0 1 1 0 1 39% 14 0 1 1 1 0 42% 15 0 1 1 1 1 45% 0 1 0 0 0 0 0%

32 V0.3 D own 1 1 0 0 0 1 - 3% 2 1 0 0 1 0 - 6% 3 1 0 0 1 1 - 9% 4 1 0 1 0 0 - 12% 5 1 0 1 0 1 - 15% 6 1 0 1 1 0 - 18% 7 1 0 1 1 1 - 21% 8 1 1 0 0 0 - 24% 9 1 1 0 0 1 - 27% 10 1 1 0 1 0 - 30% 11 1 1 0 1 1 - 33% 12 1 1 1 0 0 - 36% 13 1 1 1 0 1 - 39% 14 1 1 1 1 0 - 42% 15 1 1 1 1 1 0% N ote1: When 8080/6800 interface is used, I SEG adjust is d isable d . Note2: W hen I SEG adjust is used, Contrast value should be set to 0x80 . E xample: up step 9, Pin[D6:D2]=[01001] Figure .22 1 2 . Set Segment Re - map : (A0H - A1H) Change the relationship between RAM column address and segment driver. The order of segment driver output pads can be reversed by software. This allows flexible IC layout during OLED module assembly. For details, refer to the column addres s section of Figure. 18 . When display data is written or read, the column address is incremented by 1 as shown in Figure.18 . A0 E RD W R / WR D7 D6 D5 D4 D 3 D2 D1 D0 0 1 0 1 0 1 0 0 0 0 ADC When ADC = “L”, the right rotates (normal direction). (POR) When ADC = “H”, the left rotates (reverse direction).

33 V0.3 1 3 . Set SEG pads hardware configuration : ( A2 H – A3H ) This command is to set the SEG signals pad configu ration to match the OLED panel hardware layout . A0 E RD W R / WR D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 1 0 1 0 0 0 1 D When D = “L”, Even on the left . ( POR ) When D = “H”, Even on the right. Please see t he f ollowing f igure for Set Segment Re - map and SEG pads hardware configuration . Figure .2 3

34 V0.3 1 4 . Set Entire Display OFF/ON : (A4H - A5H) Forcibly turns the entire display on regardless of the contents of the display data RAM. At this time, the contents of the display data RAM are held. This command has priority over the normal/reverse display command. A0 E RD W R / WR D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 1 0 1 0 0 1 0 D When D = “L”, the normal display status is provided. ( POR ) When D = “H”, the entire display ON status is provided. 1 5 . Set Normal/Reverse Display: (A6H - A7H) Reverses the display ON/OFF status without rewriting the contents of the display data RAM. A0 E RD W R / WR D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 1 0 1 0 0 1 1 D When D = “L”, the RAM data is high, being OLED ON potential (normal display). (POR) When D = “H”, the RAM data is low, being OLED ON potentia l (reverse display) 1 6 . Set Multiplex Ration: (Double Bytes Command) This command switches default 6 4 multiplex modes to any multiplex ratio from 1 to 64 . The output pads COM 0 - COM63 will be switched to corresponding common signal.  Multiplex Ration Mode Set : (A8H) A0 E RD W R / WR D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 1 0 1 0 1 0 0 0  Multiplex Ration Data Set: (00H - 3FH) A0 E RD W R / WR D7 D6 D 5 D4 D3 D2 D1 D0 Multiplex Ratio 0 1 0 * * 0 0 0 0 0 0 1 0 1 0 * * 0 0 0 0 0 1 2 0 1 0 * * 0 0 0 0 1 0 3 0 1 0 : : 0 1 0 * * 1 1 1 1 1 0 63 0 1 0 * * 1 1 1 1 1 1 64 (POR)

35 V0.3 1 7 . Set DC - DC OFF/ON: (Double Bytes Command) This command is to contr ol the DC - DC voltage converter. The converter will be turned on by issuing this command then display ON command. The panel display must be off while issuing this command.  DC - DC Control Mode Set: ( A DH) A0 E RD W R / WR D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 1 0 1 0 1 1 0 1  DC - DC ON/OFF Mode Set: (8AH - 8BH) A0 E RD W R / WR D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 1 0 0 0 1 0 1 D When D = “L”, DC - DC is dis able d . When D = “H”, DC - DC will be turned on when display on. (POR) Table. 9 DC - DC STATUS DISPLAY ON/OFF STATUS Description 0 0 Sleep mode 0 1 External V PP must be used. 1 0 Sleep mode 1 1 Built - in DC - DC is used, Normal Display 1 8 . Display OFF / ON : (A EH - AFH) Alternatively turns the display on and off. A0 E RD W R / WR D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 1 0 1 0 1 1 1 D When D = “L”, Display OFF O L E D . ( POR ) When D = “H”, Display ON OLED. When the display OFF command is executed, power saver mode will be entered. Sleep mode: This mode stops every operation of the OLED display system, and can reduce current consumption nearly to a static current value if no access is made from the microprocessor. Th e internal status in the sleep mode is as follows: 1) Stops the oscillator circuit and DC - DC circuit. 2) Stops the OLED drive and outputs H z as the segment/common driver output. 3) Holds the display data and operation mode provided before the start of the sleep mod e. 4) The MPU can access to the built - in display RAM.

36 V0.3 19 . Set Page Address : (B0H - B 7 H) Specifies page address to load display RAM data to page address register. Any RAM data bit can be accessed when its page address and column address are specified. The di splay remains unchanged even when the page address is changed. A0 E RD W R / WR D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 1 0 1 1 A 3 A 2 A 1 A 0 A 3 A 2 A 1 A 0 Page address 0 0 0 0 0 0 0 0 1 1 0 0 1 0 2 0 0 1 1 3 0 1 0 0 4 0 1 0 1 5 0 1 1 0 6 0 1 1 1 7 Note: Don’t use any commands not mentioned above for user. 2 0 . Set Common Output Scan Direction: (C0H - C8H) This command sets the scan direction of the common output allowing layout flexibility in OLED module design. In addition, the display will have immediate effect once this command is issued. That is, if this command is sent during normal display, the graphic display will be vertically flipped. A0 E RD W R / WR D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 1 1 0 0 D * * * When D = “L”, Scan from COM0 to COM [N - 1]. ( POR ) When D = “H”, Scan from COM [N - 1] to COM0.

37 V0.3 2 1 . Set Display Offset: (Double Bytes Command) This is a double byte command. The next com mand specifies the mapping of display start line to one of COM0 - 63 (it is assumed that COM0 is the display start line, that equals to 0). For example, to move the COM16 towards the COM0 direction for 16 lines, the 6 - bit data in the second byte should be gi ven by 010000. To move in the opposite direction by 16 lines, the 6 - bit data should be given by (64 - 16) , so the second byte should be 100000.  Display Offset Mode Set: (D3H) A0 E RD W R / WR D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 1 1 0 1 0 0 1 1  Display Offset Data Set: (00H~3FH) A0 E RD W R / WR D7 D6 D5 D4 D3 D2 D1 D0 COM x 0 1 0 * * 0 0 0 0 0 0 0 (POR) 0 1 0 * * 0 0 0 0 0 1 1 0 1 0 * * 0 0 0 0 1 0 2 0 1 0 : : 0 1 0 * * 1 1 1 1 1 0 62 0 1 0 * * 1 1 1 1 1 1 63 Note: “*” stands for “Don’t care”

38 V0.3 2 2 . Set Display Clock Divide Ratio / Oscillator Frequency: (Double Bytes Command) This command is used to set the frequency of the internal disp lay clocks ( DCLKs ) . It is defined as the divide ratioused to divide the oscillator frequency. POR is 8 . Frame frequency is determined by divide ratio, number of display clocks per row, MUX ratio and oscillator frequency.  Divide Ratio/Oscillator Frequency M ode Set: (D 5 H) A0 E RD W R / WR D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 1 1 0 1 0 1 0 1 0 1 0 A 7 A 6 A 5 A 4 * * A 1 A 0 A 1 - A0 defines the divide ration of the display clocks (DCLK). A 1 A 0 Divide Ration 0 0 8 (POR) 0 1 16 1 0 3 1 1 4 A7 - A4 sets the o scillator f requency . Oscillator f requency increase with the value of A[7:4] and vice versa. A7 A6 A5 A4 Oscillator Frequency of ƒOSC 0 0 0 0 - 17.1 % 0 0 0 1 - 13.3 % 0 0 1 0 - 10.3 % 0 0 1 1 - 7.0 % 0 1 0 0 - 3.6 % 0 1 0 1 ƒOSC (POR) 0 1 1 0 + 3.0 % 0 1 1 1 + 6.2 % 1 0 0 0 + 8.6 % 1 0 0 1 + 11.2 % 1 0 1 0 + 13.8 % 1 0 1 1 + 16.3 % 1 1 0 0 + 18.6 % 1 1 0 1 + 20.7 % 1 1 1 0 + 22.8 % 1 1 1 1 + 25.1 %

39 V0.3 2 3 . Set Adaptive Power Save : (D 6 H - D7H ) This command sets Adaptive P ower Save . A0 E RD W R / WR D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 1 1 0 1 0 1 1 D When D = “L”, Normal. When D = “H”, Adaptive Power Save ( POR ) . 2 4 . Set Dis charge/ Pre - charge P eriod: ( Double Bytes Comm and ) This command is used to set the duration of the Dis charge/ Pre - charge period. The interval is counted in number of DCLK. POR is 6 DCLK s .  Pre - charge P eriod Mode Set: (D 9 H) A0 E RD W R / WR D7 D 6 D5 D4 D3 D2 D1 D0 0 1 0 1 1 0 1 1 0 0 1  Dis charge/ Pre - charge P eriod Data Set: (00H - FFH) A0 E RD W R / WR D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 A 7 A 6 A 5 A 4 A 3 A 2 A 1 A 0 Pre - charge P eriod Adjust: (A3 - A0) A 3 A 2 A 1 A 0 Pre - charge P eriod 0 0 0 0 0 DCLK (Note) 0 0 0 1 3 DCLKs 0 0 1 0 6 DCLKs (POR) : : 1 1 1 0 42 DCLKs 1 1 1 1 4 5 DCLKs Dis charge P eriod Adjust: (A7 - A4) A 7 A 6 A 5 A 4 Dis charge P eriod 0 0 0 0 INVALID 0 0 0 1 3 DCLKs 0 0 1 0 6 DCLKs (POR) : : 1 1 1 0 42 DCLKs 1 1 1 1 4 5 DCLKs Note: When set A[3:0]=0, the period for display will increase 6 DCLKs. And there is no pre - charge period so that it will save power consumption.

40 V0.3 2 5 . Set VCOM D eselect L evel : (Double Byte s Command) This command is to set the common pad output voltage level at deselect stage.  VCOM D eselect L evel Mode Set: ( DB H) A0 E RD W R / WR D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 1 1 0 1 1 0 1 1  VCOM D eselect L evel Data Set: (00H - FFH) A0 E RD W R / WR D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 A 7 A 6 A 5 A 4 A 3 A 2 A 1 A 0 V COM = β X V REF = (0.430 + A[7:0] X 0.006415) X V REF A[7:0] β A[7:0] β 00H 0.430 20H 0 .635 0 1 H 0.436 2 1 H 0.642 0 2 H 0.442 2 2 H 0.648 0 3 H 0.449 2 3 H 0.654 0 4 H 0.456 2 4 H 0.661 05H 0.462 25H 0.667 06H 0.468 26H 0.674 07H 0.475 27H 0.680 08H 0.481 28H 0.687 09H 0.488 29H 0.693 0AH 0.494 2AH 0.699 0BH 0.501 2BH 0.706 0CH 0.507 2CH 0.712 0DH 0.513 2DH 0.719 0EH 0.520 2EH 0.725 0 FH 0.526 2 FH 0.731 10H 0.533 30H 0.738 1 1 H 0.539 3 1 H 0.744 1 2 H 0.525 3 2 H 0.751 1 3 H 0.552 3 3 H 0.757 1 4 H 0.558 3 4 H 0.764 15H 0.565 35H 0.770 (POR) 16H 0.571 36H 0.776 17H 0.578 37H 0.783 18H 0.584 38H 0.7 89 19H 0.590 39H 0.796 1AH 0.596 3AH 0.802 1BH 0.603 3BH 0.808 1CH 0.610 3CH 0.815 1DH 0.616 3DH 0.821 1EH 0.622 3EH 0.828 1FH 0.629 3FH 0.834 40H - F E H 1 FF External N ote: V COM voltage must be less than VPP voltage.

41 V0.3 2 6 . Set row non - overlap / SEG H iz P eriod: ( Double Bytes Command ) . This command is used to set the duration of the row non - overlap / SEG Hiz P eriod period.  row non - overlap / SEG Hiz P eriod Set: (D C H) A0 E RD W R / WR D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 1 1 0 1 1 1 0 0  R ow non - overlap / SEG Hiz P eriod Data Set: (00H - FFH) A0 E RD W R / WR D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 A 7 A 6 A 5 A 4 A 3 A 2 A 1 A 0 R ow non - overlap P eriod Adjust: (A 4 - A0) A 4 A 3 A 2 A 1 A 0 Row non - overlap P eriod 0 0 0 0 0 0 DCLK 0 0 0 0 1 3 DCLK s (POR) 0 0 0 1 0 6 DCLKs : : : : : : 1 1 1 1 0 90 DCLKs 1 1 1 1 1 93 DCLKs SEG Hiz P eriod Adjust: (A7 – A 5 ) A 7 A 6 A 5 Front 0 0 0 0 DCLK (POR) 1 0 0 1 DCLK 1 1 1 2 DCLK s Please see the f ollowing f igure for Dis - charge/ Pre - charge /Row non - overlap / SEG Hiz. Figure .2 4

42 V0.3 2 7 . Read - Modify - Write: (E0H) A pair of Read - Modify - Write and End commands must always be used. Once read - modify - write is issued, column address is not incremental by read display data command but incremental by write display data command only. It continues until End command is issued. When the End is issued, column address returns to the address when read - modify - write is issued. This can reduce the microprocessor load when data of a specific display area is repeatedly changed during cursor blinking or others. A0 E RD W R / WR D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 1 1 1 0 0 0 0 0 Cursor display sequence: Set Page Address Set Column Address Read-Modify-Write Dummy Read Read Data Write Data Completed? End Yes No Data process Figure. 2 5 2 8 . End: (EEH) Cancels Read - Modify - Write mode and returns column address to the original address (when Read - Modify - Write is issued.) A0 E RD W R / WR D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 1 1 1 0 1 1 1 0 Read-Modify-Write mode is selected Return N N+1 N+2 N+m N N+3 End Column address Figure. 2 6

43 V0.3 29 . NOP: (E3H) Non - Operation Command. A0 E RD W R / WR D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 1 1 1 0 0 0 1 1 3 0 . Write Display Data Write 8 - bit data in display RAM. As the column address is incremental by 1 automatically after each write, the microprocessor can continue to write data of multiple words. A0 E RD W R / WR D7 D6 D5 D4 D3 D2 D1 D0 1 1 0 Write RAM data 3 1 . Read Status A0 E RD W R / WR D7 D6 D5 D4 D3 D2 D1 D0 0 0 1 - ON/OFF ID ON/OFF: Indicates whether the d isplay is on or off. When goes low the display turns on. When goes high, the display turns off. This is the opposite of Display ON/OFF command. ID ： These bits contain the information of the chip. The output bits 0 1 0 1 0 1 (it means CH1115 ). N ote: C D / or A0 must be set to low befor e read ing s tatus. 3 2 . Read Display Data Reads 8 - bit data from display RAM area specified by column add ress and page address. As the column address is increment by 1 automatically after each write, the microprocessor can continue to read data of multiple words. A single dummy read is required immediately after column address being setup. Refer to the displa y RAM section of FUNCTIONAL DESCRIPTION for details. Note that no display data can be read via the serial interface. A0 E RD W R / WR D7 D6 D5 D4 D3 D2 D1 D0 1 0 1 Read RAM data N ote: C D / or A0 must be set to high befor e read ing display data .

44 V0.3 Command Table Command Code Function A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0 1. Set Column Address 4 lower bits 0 1 0 0 0 0 0 Lower column addre ss Sets 4 lower bits of column address of display RAM in register. (POR = 00H) 2. Set Column Address 4 higher bits 0 1 0 0 0 0 1 Higher column address Sets 4 higher bits of column address of display RAM in register. (POR = 10H) 3. Set Breathing Light an d Blinking 0 1 0 0 0 1 0 0 0 1 1 This command is to control breathing light. (POR = 0 1 H) 0 1 0 ON/ OFF * * * A4 A2 A1 A0 4. Additional Horizontal Scroll Setup Mode Set 0 1 0 0 0 1 0 0 1 0 0 This command consists of 3 consecutive bytes to set up the ho rizontal scroll parameters. It determined the scrolling start column position(POR=00H) and end column position(POR= 7FH ). 0 1 0 * S tart C olumn A ddress 0 1 0 * End C olumn A ddress 5. Horizontal Scroll Setup 0 1 0 0 0 1 0 0 1 1 D This command consists of 4 consecutive bytes to set up the horizontal scroll parameters. It determined scroll mode, scroll start page(POR=00H), time interval (POR=00H) between each scroll step in terms of frame frequency , and end page(POR=0 7 H). 0 1 0 * * * * * Start Page Add ress 0 1 0 0 * * * * T ime I nterval 0 1 0 0 * * * * End Page Address 6 . Set Scroll Mode 0 1 0 0 0 1 0 1 D This command is to Control continuous or Single screen scroll . (POR=2 C H) 7 . Set Deactivate / Activate Horizontal Scroll 0 1 0 0 0 1 0 1 1 1 D Stop(0) or Start(1) motion of horizontal scrolling. (POR=2EH) 8 . Set Pump voltage value 0 1 0 0 0 1 1 0 0 Pump voltage value This command is to control the DC - DC voltage output value and select pump mode. (POR=3 2 H) 9 . Set Display Start Line 0 1 0 0 1 Line address Specifies RAM display line for COM0. (POR = 40H) 10. The Contrast Control Mode Set 0 1 0 1 0 0 0 0 0 0 1 This command is to set Contrast Setting of the display. The chip has 256 contrast steps from 00 to FF. (POR = 80H) Contrast Da ta Register Set 0 1 0 Contrast Data

45 V0.3 11. I REF Resistor Set and Adjust I SEG by PAD 0 1 0 1 0 0 0 0 0 1 0 This command is to set internal or external I REF resistor and Adjust I SEG by PAD . (POR=00H) 0 1 0 ON/ OFF * * * * D A1 A0 1 2 . Set Segment Re - map ( ADC) 0 1 0 1 0 1 0 0 0 0 ADC The right (0) or left (1) rotation. (POR = A0H) 1 3 . Set SEG pads hardware configuration 0 1 0 1 0 1 0 0 0 1 D The EVEN left (0) or right (1) rotation. (POR = A 2 H) 1 4 . Set Entire Display OFF/ON 0 1 0 1 0 1 0 0 1 0 D Selects no rmal display (0) or Entire Display ON (1). (POR = A4H) 1 5 . Set Normal/ Reverse Display 0 1 0 1 0 1 0 0 1 1 D Normal indication (0) when low, but reverse indication (1) when high. (POR = A6H) 1 6 . Multiplex Ration Mode Set 0 1 0 1 0 1 0 1 0 0 0 This command switches default 63 multiplex mode to any multiplex ratio from 1 to 64 . (POR = 3FH) Multiplex Ration Data Set 0 1 0 * * Multiplex Ratio 1 7 . DC - DC Control Mode Set 0 1 0 1 0 1 0 1 1 0 1 This command is to control the DC - DC voltage DC - DC will be turned o n when display on converter (1) or DC - DC OFF (0). (POR = 8BH) DC - DC ON/OFF Mode Set 0 1 0 1 0 0 0 1 0 1 D 1 8 . Display OFF / ON 0 1 0 1 0 1 0 1 1 1 D Turns on OLED panel (1) or turns off (0). (POR = AEH) 19 . Set Page Address 0 1 0 1 0 1 1 Page Address Spe cifies page address to load display RAM data to page address register. (POR = B0H)

46 V0.3 Command Table (Continued) Command Code Function A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0 2 0 . Set C ommon Output Scan Direction 0 1 0 1 1 0 0 D * * * Scan from COM0 to COM [N - 1 ] (0) or Scan from COM [N - 1] to COM0 (1). (POR = C0H) 2 1 . Display Offset Mode Set 0 1 0 1 1 0 1 0 0 1 1 This is a double byte command which specifies the mapping of display start line to one of COM0 - 63 . (PO R = 00H) Display Offset Data Set 0 1 0 * * COM x 2 2 . Set Display Divide Ratio/Oscillator Frequency Mode Set 0 1 0 1 1 0 1 0 1 0 1 This command is used to set the frequency of the internal display clocks . (POR = 5 0H) Divide Ratio/Oscillator Frequency Data Set 0 1 0 Oscillator Frequency * * Divide Ratio 23 . Set Adaptive Power Save 0 1 0 1 1 0 1 0 1 1 D This command sets Adaptive Power Save ON/OFF (POR = D7 H) 2 4 . Dis - charge / Pre - charge P eriod Mode Set 0 1 0 1 1 0 1 1 0 0 1 This command is used to set the duration of the dis - charge and pre - charge period . (POR = 22H) Dis - charge / Pre - charge P eriod Data Set 0 1 0 Dis - charge P eriod Pre - charge P eriod 2 5 . VCOM D eselect L evel Mode Set 0 1 0 1 1 0 1 1 0 1 1 This command is to set the common pad output vo ltage level at deselect stage. (POR = 35H) VCOM D eselect L evel Data Set 0 1 0 VCOM (β X V REF ) 2 6 .Set r ow n on - overlap / SEG Hiz P eriod 0 1 0 1 1 0 1 1 1 0 0 This command is to set Line overlap / SEG Hiz P eriod (POR = 01 H) 0 1 0 SEG Hiz P eriod Row no n - overlap P eriod 2 7 . Read - Modify - Write 0 1 0 1 1 1 0 0 0 0 0 Read - Modify - Write start. 2 8 . End 0 1 0 1 1 1 0 1 1 1 0 Read - Modify - Write end. 29 . NOP 0 1 0 1 1 1 0 0 0 1 1 Non - Operation Command 3 0 . Write Display Data 1 1 0 Write RAM data 3 1 . Read Sta tus 0 0 1 BUSY ON/ OFF * * * 0 0 0 3 2 . Read Display Data 1 0 1 Read RAM data Note: Do not use any other command, or the system malfunction may result.

47 V0.3 1. Power On and Initialization 1.1. B uilt - in DC - DC pump power is being used immediately after turni ng on the power: VPP Turn on the VDD 1 and VDD 2 power , keep the RES pin =" L "( > 10 us ) Release the reset state ( RES pin =" H " ) Reset timing depends on C H 11 15 data sheet Initialized state ( Default ) Set up initial code ( user setup ) Clear inter n al RAM to " 00 H " Set d isplay on : AFH VDD 1 is off VDD 2 is off Send display data Wait 100 ms P ower on sequence ：

48 V0.3 1.2. E xternal power is being used immediately after turning on the power: VPP Turn on the VDD 1 and VPP power , keep the RES pin =" L "( > 10 us ) Release the reset state ( RES pin =" H " ) Reset timing depends on C H 11 15 data sheet Initialized state ( Default ) Set up initial code ( user setup ) Clear inter n al RAM to " 00 H " Set d isplay on : AFH VDD 1 is off External power VPP is off Send display data Wait 100 ms P ower on sequence ：

49 V0.3 1.3 . Power Off P ower off sequence ：

50 V0.3 Absolute Maximum Rating* *Comments Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to this device. These are stress ratings only. Functional operation of this device under these or any other conditions abov e those indicated in the operational sections of this specification is not implied or intended. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability.

Electrical Characteristics

DC Characteristics (V SS = 0V, V DD1 = 1.65 - 3.5V T A =+25  C, unless otherwise specified) Symbol Parameter Min. Typ. Max. Unit Condition V DD1 Operating voltage 1.65 - 3.5 V V DD2 Operating voltage 3.0 - 4. 7 5 V V PP (External) OLED Operating voltage 6.4 1 4 . 0 V Vpp (Internal) Charge Pump Output Voltage loading =1 2 mA ( I REF = - 1 8.75  A, Contrast  = 256 ) t loading =1 8 mA ( I REF = - 1 8.75  A, Contrast  = 256 ) loading =18mA ( I REF = - 1 8.75  A, Contrast  = 256 ) loading =18mA ( I REF = - 1 8.75  A, Contrast  = 256 ) I DD1 Dynamic current consumption 1 - - 600  A V DD1 = 3V, V DD2 = 3 .7 V, I REF = - 1 8.75  A, Contrast  = 256 , Internal charge pump OFF , Display ON , display data = All ON, No panel attached . I DD2 Dynamic current consumption 2 - - 3.5 m A V DD1 = 3V, V DD2 =3 .7 V, I REF = - 1 8.75  A, Contrast  = 256 , inte rnal charge pump ON, Display ON, Display data = All ON, No panel attached . I PP OLED dynamic current consumption - - 1.5 m A V DD1 = 3V, V DD2 = 3 .7 V, V PP = 9 V (external) , I REF = - 1 8.75  A, Contrast  = 256, Display ON, display data = All ON, No panel atta ched . Connect charge pump capacitor I SP Sleep mode current consumption in V DD1 & V DD2 - - 5  A During sleep, T A = +25  C, V DD1 = 3 .0 V, V DD2 = 3 .0 V. Sleep mode current consumption in V PP - - 5  A During sleep, T A = +25  C, V PP = 9 V (E xternal ) I SEG Segme nt output current - - 30 0 -  A V DD1 = 3V, V PP = 9 V, I REF = - 1 8.75  A, R LOAD = 20 k  , Display ON. Contrast  = 256. - - 37.5 -  A V DD1 = 3V, V PP = 9 V, I REF = - 1 8.75  A, R LOAD = 20 k  ,  Display ON. Contrast  = 32 . ∆ I SEG1 Segment output current uniformity - -  3 % ∆ I SEG1 = (I SEG - I MID )/I MID X 100% I MID = (I MAX + I MIN )/2 I SEG [0: 127 ] at contrast  = 256. ∆ I SEG2 Adjacent segment output current uniformity - -  2 % ∆ I SEG2 = (I SEG [N] - I SEG [N+1])/(I SEG [N] + I SEG [N+1]) X 100% I SEG [0: 127 ] at contrast  = 256.

51 V0.3 DC Characteristics (Continued) Symbol Parameter Min. Typ. Max. Unit Condition V IHC High - level input voltage 0.8 X V DD1 - V DD1 V A0, D0 - D7, RD (E), WR ( W R / ), CS , CLS, C L, IM0~2 and RES . V ILC Low - level input voltage V SS - 0.2 X V DD1 V V OHC High - level output voltage 0.8 X V DD1 - V DD1 V I OH = - 0.5mA (D0 - D7, and CL). V OLC L ow - level output voltage V SS - 0.2 X V DD1 V I OL = 0.5mA ( D0 , D2 - D7, and CL ) V OLC S SDA l ow - level output voltage V SS -

0.2 X V DD1

V VDD1<2V I OL =3mA (SDA)

0.4 VDD1>2V

I LI Input leakage current - 1.0 - 1.0  A V IN = V DD1 or V SS (A0, RD (E), WR ( W R / ), CS , CLS, IM0~2 and RES ). I H z H z leakage current - 1.0 - 1.0  A When the D0 - D7, and CL are in high impedance. f OSC Oscillation frequency 7.2 8 8.8 M Hz T A = +25  C. f FRM Frame frequency for 64 Commons 94.5 105 115.5 Hz When f OSC = 8 *(1 +8.6% ) M Hz, D ivide ratio = 8 , Discharge: 2 DCLKs , Pre - charge: 2 DCLKs Code: D5H = 80H, D9H = 22H R ON1 Common switch resistance - 16 - Ω Vpp=9V,Vcom= GND +0.4V R ON2 Common switch resistance - 500 - Ω Vpp=9V,VCOM=0.770 × Vpp - 0.4V

52 V0.3 AC Characteristics (1) Sy stem buses Read/Write characteristics 1 (For the 8080 Series Interface MPU) RD , WR CS 8080 - series parallel interface cycle (Form1) RD , WR CS 8080 - series parallel interface cycle (Form2)

53 V0.3 Symbol Parameter Min. Typ. Max. Unit Condition t CYC8 System cycle time 600 - - n s t AS8 Address setup time 0 - - n s t AH8 Address hold time 0 - - n s t DS8 Data setup time 80 - - n s t DH W 8 Write Data hold time 20 - - n s t DH R 8 Read Data hold ti me 20 - - ns T O H8 Output disable time - - 140 n s C L = 100pF t ACC8 RD access time - - 280 n s C L = 100pF t CCLW Control L pulse width (WR) 30 0 - - n s t CCLR Control L pulse width (RD) 30 0 - - n s t CCHW Control H pulse width (WR) 30 0 - - n s t CCHR Control H pulse width (RD) 300 - - n s t R Rise time - - 30 n s t F Fall time - - 30 n s t CS8 Chip select setup time 0 - - n s t CSH8 Chip select hold time 40 - - n s t CSHR8 Chip select hold time to read signal 40 - - n s

54 V0.3 Symbol Parameter Min. Typ. Max. Unit Condition t CYC8 System cycle time 300 - - n s t AS8 Address setup time 0 - - n s t AH8 Address hold time 0 - - n s t DS8 Data setup time 40 - - n s t DH W 8 Write Data hold time 10 - - n s t DH R 8 Read Data hold time 10 - - ns t O H8 Output disable time - - 70 n s C L = 100pF t ACC8 RD access time - - 140 n s C L = 100pF t CCLW Control L pulse width (WR) 150 - - n s t CCLR Control L pulse width (RD) 1 5 0 - - n s t CCHW Control H pulse w idth (WR) 1 5 0 - - n s t CCHR Control H pulse width (RD) 1 5 0 - - n s t R Rise time - - 15 n s t F Fall time - - 15 n s t CS8 Chip select setup time 0 - - ns t CSH8 Chip select hold time 20 - - ns t CSHR8 Chip select hold time to read signal 20 - - ns

55 V0.3 ( 2) System buses Read/Write Characteristics 2 (For the 6800 Series Interface MPU) E W R/ CS 6800 - series parallel interface cycle (Form1) A 0 D 0 ~ D 7 ( WRITE ) t AS 6 D 0 ~ D 7 ( READ ) E t F t CYC 6 t AH 6 t DHR 6 t ACC 6 t R t DS 6 t DHW 6 t CCLR t CCHR t CCHW t CCLW W R/ CS t CS 6 t CSH 6 t CSHR 6 t OH 6 6800 - series parallel interface cycle (Form2)

56 V0.3 Symbol Parameter Min. Typ. Max. Unit Condition t CYC6 System cycle time 600 - - ns t AS6 Address setup time 0 - - ns t AH6 Address hold time 0 - - ns t DS6 Data setup time 8 0 - - ns t DH W 6 Write Data hold time 20 - - ns t DH R 6 Read Data hol d time 20 - - ns t OH6 Output disable time - - 14 0 ns C L = 100pF t ACC6 Access time - - 28 0 ns C L = 100pF t EWHW Enable H pulse width (Write) 3 00 - - ns t EWHR Enable H pulse width (Read) 30 0 - - ns t EWLW Enable L pulse width (Write) 3 00 - - ns t EWLR Enable L pulse width (Read) 3 00 - - ns t R Rise time - - 30 n s t F Fall time - - 30 n s t CS 6 Chip select setup time 0 - - ns t CSH 6 Chip select hold time 40 - - ns t CSHR 6 Chip select hold time to read signal 40 - - ns

57 V0.3 Symbol Parameter Min. Typ. Max. Unit Condition t CYC6 System cycle time 300 - - ns t AS6 Address setup time 0 - - ns t AH6 Address hold time 0 - - ns t DS6 Data setup time 40 - - ns t DH W 6 Write Data hold time 10 - - ns t DH R 6 Read Data hold time 10 - - ns t OH6 Output disable time - - 70 ns C L = 100pF t ACC6 Access time - - 140 ns C L = 100pF t EWHW Enable H pulse width (Write) 150 - - ns t EWHR Enable H pulse width (Read) 1 5 0 - - ns t EWLW Enable L pulse width (Write) 1 5 0 - - ns t EWLR Enable L pulse width (Read) 1 5 0 - - ns t R Rise time - - 15 n s t F Fall time - - 15 n s t CS 6 Chip select setup time 0 - - ns t CSH 6 Chip select hold time 20 - - ns t CSHR 6 Chip select hold time to read signal 20 - - ns

58 V0.3 (3) System buses Write characteris tics 3 (For 4 wire SPI ) CS SCL SI t R t CSS t CSH t SAS t SAH t SCYC t SLW t SHW t SDH t SDS t F t F Symbol Parameter Min. Typ. Max. Unit Condition t SCYC Serial clock cycle 5 00 - - ns t SAS Address setup time 30 0 - - ns t SAH Address hold time 30 0 - - ns t SDS Data setup time 20 0 - - ns t SDH Data hold time 20 0 - - ns t CSS CS setup time 24 0 - - ns t CSH CS hold time time 120 - - ns t SHW Serial clock H pulse width 20 0 - - ns t SLW Serial clock L pulse width 20 0 - - ns t R Rise time - - 30 n s t F Fall time - - 30 n s Symbol Parameter Min. Typ. Max. Unit Condition t SCYC Serial clock cycle 25 0 - - ns t SAS Address setup time 15 0 - - ns t SAH Address hold time 15 0 - - ns t SDS Data set up time 10 0 - - ns t SDH Data hold time 10 0 - - ns t CSS CS setup time 120 - - ns t CSH CS hold time time 60 - - ns t SHW Serial clock H pulse width 10 0 - - ns t SLW Serial clock L pulse width 10 0 - - ns t R Rise time - - 15 n s t F Fall time - - 15 n s

59 V0.3 ( 4 ) System buses Write characteristics 4 (For 3 wire SPI ) CS SCL SI t R t CSS t CSH t SCYC t SLW t SHW t SDH t SDS t F t F Symbol Parameter Min. Typ. Max. Unit Condition t SCYC Serial clock cycle 5 00 - - ns t S DS Data setup time 20 0 - - ns t SDH Data hold time 20 0 - - ns t CSS CS setup time 24 0 - - ns t CSH CS hold time time 120 - - ns t SHW Serial clock H pulse width 2 0 0 - - ns t SLW Serial clock L pulse width 2 0 0 - - ns t R Rise time - - 30 n s t F Fall time - - 30 n s Symbol Parameter Min. Typ. Max. Unit Condition t SCYC Serial clock cycle 2 5 0 - - ns t SDS Data setup time 1 0 0 - - ns t SDH Data hold time 10 0 - - ns t CSS CS setup time 120 - - ns t CSH CS hold time time 60 - - ns t SHW Serial clock H pulse width 10 0 - - ns t SLW Serial clock L pulse width 10 0 - - ns t R Rise time - - 15 n s t F Fall time - - 15 n s

60 V0.3 ( 5 ) I 2 C interface characteristics t BU F t HD:START t R t SU:START t HIGH t SU:DATA t SU:STOP SDA SCL SDA t LOW t HD:DATA t F Symbol Parameter Min. Typ. Max. Unit Condition f SC L S CL clock frequency DC - 400 kHz T LOW S CL clock Low pulse width 1.3 - - u S T HIGH S CL clock H pulse width 0.6 - - u S T SU :DATA data setup time 100 - - nS T HD :DATA data hold time 0 - 0.9 uS T R SCL ， SDA rise time 20+0.1Cb - 300 nS T F SCL ， SDA fall time 20+0.1Cb - 300 nS Cb Capacit y load on each bus line - - 400 pF T SU : S TART Setup timefor re - START 0.6 - - u S T HD:START START Hold time 0.6 - - u S T SU :STO P Setup time for STOP 0.6 - - u S T BUF Bus free times between STOP and START condition 1.3 - - uS

61 V0.3 ( 6 ) Reset Timing Internal circuit status RES During reset End of reset t RW t R Symbol Parameter Min. Typ. Max. Unit Condition t R Reset time - - 2 .0  s t R W Reset low pulse width 2 0 .0 - -  s Symbol Parameter Min. Typ. Max. Unit Condition t R Reset time - - 1.0  s t R W Reset low pulse width 10 .0 - -  s

62 V0.3 Application Circuit (for reference only) Reference Connection to MPU: 1. 8080 series interface: (I nt ernal oscillator , Built - in DC - DC ) Figure. 27 Note: R 1 : about 3 1 0 k  , R 1 = (Voltage at I REF - V SS )/I REF

63 V0.3 2. 6800 Series Interface: (I nternal oscillator , Built - in DC - DC) V DD 1 D 7 ~ D 0 A 0 RD CS WR RES IM 1 V SS V SL V CL CLS CL A 0 E CS R / W RES D 7 ~ D 0 MPU + C 3 V DD CH 1115 I REF R 1 C 4 V PP V COMH C 5 C 1 C 2 C 1 N C 1 P C 2 N C 2 P V BREF V DD 2 C 7 + V DD 2 IM 2 IM 0 Figure. 28 Note: R 1 : about 3 1 0 k  , R 1 = (Voltage at I REF - V SS )/I REF

64 V0.3 3. Serial Interface ( 3 - wire or 4 - wire SPI) : ( I nternal oscillator , External V PP , Max 1 4 .0V ) V DD 1 V SS V SL V CL CLS CL I REF + C 3 External V PP R 1 V DD D 7 ~ D 2 IM 1 D 0 D 1 A 0 RD CS WR RES A 0 CS RES SI MPU SCL V PP V COMH C 5 C 1 N C 1 P C 2 N C 2 P V BREF C 4 CH 1115 NC / Fix to Vss / Fix to V DD 1 . V DD 2 NC Either fix to Vss ( Max : 14 . 0 V ) Not used in 3 - wire SPI , Fix to Vss . IM 2 IM 0 4 - wire SPI : IMO Fix to VSS . 3 - wire SPI : IMO Fix to VDD 1 . Figure. 29 Note: C 3 - C 5 : 4.7  F  R 1 : about 3 1 0 k  , R 1 = (Voltage at I REF - V SS )/I REF WR and RD are not used in SPI mode, should fix to VSS or VDD1. CS can fix to VSS in SP I mode .

65 V0.3 4 . I 2 C Interface: ( In ternal oscill ator , Built - in DC - DC ) V SS V SL V CL V DD 1 CLS CL I REF C 3 CH 1115 R 1 D 7 ~ D 2 IM 1 D 0 D 1 SA 0 RD CS WR RES CS RES SDA MPU SCL C 4 V PP V COMH C 5 C 1 C 2 C 1 N C 1 P C 2 N C 2 P V BREF NC / Fix to Vss / Fix to V DD 1 . Either fix to Vss . V DD 2 V DD 1 C 7 + V DD 2 IM 2 IM 0 Figure. 30 Note: R 1 : about 3 1 0 k  , R 1 = (Voltage at I REF - V SS )/I REF The least significant bit of the slave address is set by connecting the input SA0 to either logic 0 (VSS) or 1 (VDD 1 ). WR and RD are not used in I 2 C mode, should fix to VSS or VDD1. CS can fix to VSS in I 2 C mode . The positive supply of pull - up resistor must equal to the value of V DD1 .

66 V0.3 Orde ring Information Part No. Package CH1115 G Gold bump on chip tray Version Content Date 0 .0 Original Nov.2016 0 . 1 P age 28: Add single column scroll P age 31: Modify IREF Resistor & IREF Table Page 36: Modify Oscillator Frequency of ƒ OSC P age 39: Modify Adaptive Power Save POR value P age 40: Add VCOMH external P age 41: Row non - overlap default 3 Dclks P age 50: Modify V DD2 voltage range P age 50: Modify Charge Pump Output Voltage P age 51: Add RON1 and RON2 dc character P age 51: Mo dify f OSC and f FRM Aug.2017 0 . 2 P age 51: Modify f OSC and f FRM Mar .201 8 0 . 3 P age 5 0 : Modify VDD2 Operating voltage P age 5 8 : Modify System buses Write characteristics 3 P age 5 9 : Modify System buses Write characteristics 4 May .201 8