CEZC4092 CET-MOS | Alldatasheet
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40V, 43A, RDS(ON) = 8.4mW @VGS = 10V. RDS(ON) = 13mW @VGS = 4.5V. Super High dense cell design for extremely low RDS(ON). High power and current handing capability. ABSOLUTE MAXIMUM RATINGS TC = 25 C unless otherwise noted Parameter Symbol Limit Units Drain-Source Voltage Gate-Source Voltage Drain Current-Continuous Maximum Power Dissipation VDS VGS ID@RqJc PD IDM@RqJA ±20 V W A A V http://www.cet-mos.com Rev 1. 2023.Jau ID@RqJA 13 A Drain Current-Pulsed a IDM@RqJc 172 A N-Channel Enhancement Mode Field Effect Transistor S G D Details are subject to change without notice . P-PAK 3X3 Pb-free lead plating ; RoHS compliant. Halogen Free. Operating and Store Temperature Range TJ,Tstg -55 to 150 C Thermal Characteristics Thermal Resistance, Junction-to-Case Parameter Symbol Limit Units C/WRqJc Thermal Resistance, Junction-to-Ambient b C/W50RqJA
Electrical Characteristics TC = 25 C unless otherwise noted Parameter Symbol Min Units Off Characteristics Drain-Source Breakdown Voltage Zero Gate Voltage Drain Current Gate Body Leakage Current, Forward Gate Threshold Voltage Static Drain-Source On-Resistance BVDSS IDSS IGSSR IGSSF 8.47 -100 100 mW V nA nA µA V Gate Body Leakage Current, Reverse On Characteristics c Dynamic Characteristics d Input Capacitance Reverse Transfer Capacitance Output Capacitance Switching Characteristics d Turn-On Delay Time Turn-Off Fall Time Turn-Off Delay Time Turn-On Rise Time Total Gate Charge Gate-Source Charge Gate-Drain Charge Drain-Source Diode Characteristics and Maximun Ratings Drain-Source Diode Forward Current Drain-Source Diode Forward Voltage c Test Condition VGS = 0V, ID = 250µA VGS(th) RDS(on) Ciss Coss Crss td(on) tr td(off) tf Qg Qgs Qgd IS VSD Typ Max VDS = 40V, VGS = 0V VGS = 20V, VDS = 0V VGS = -20V, VDS = 0V VGS = VDS, ID = 250µA VGS = 10V, ID =15A VGS = 4.5V, ID =8A VDS = 32V, ID = 10A, VGS = 4.5V VDS = 25V, VGS = 0V, f = 1.0 MHz VGS = 0V, IS = 1A 1045 165 120 1.3 1310 mW pF pF pF ns ns ns ns nC nC nC A V VDD = 32V, ID = 10A, VGS = 10V, RGEN = 6W Notes : a.Repetitive Rating : Pulse width limited by maximum junction temperature. b.Surface Mounted on FR4 Board, t < 10 sec. c.Pulse Test : Pulse Width < 300µs, Duty Cycle < 2%. d.Guaranteed by design, not subject to production testing.
Figure 12. Normalized Thermal Transient Impedance Curve
D A c E e K L L2 E2 E3D2 b PIN #1 DOT BY MARKING P-PAK 3X3 產品外觀尺寸圖 (Product Outline Dimension) SINGLE PAD尺寸圖 0.650.50 0.35 1.70 2.28 1.40 0.42 0.40 0.30 0.35 2.50 0.43 3.35 (SINGLE PAD) (Lead Pattern Recommendation) MILLIMETERS INCHES SYMBOLS MIN MAX MIN MAX A 0.7 0.85 0.028 0.033 b 0.20 0.40 0.008 0.016 c 0.10 0.25 0.004 0.010 D 3.15 3.45 0.124 0.136 D1 3.00 3.25 0.118 0.128 D2 2.29 2.65 0.090 0.104 E 3.15 3.45 0.124 0.136 E1 2.90 3.20 0.114 0.126 E2 1.54 1.94 0.061 0.076 E3 0.28 0.65 0.011 0.026 E4 0.37 0.77 0.015 0.030 e 0.65(BSC) 0.026(BSC) K 0.50 0.89 0.02 0.035 L 0.30 0.50 0.012 0.020 L1 0.06 0.20 0.002 0.008 L2 0.27 0.57 0.011 0.022 CEZC4092