CEZ8R04 CET-MOS | Alldatasheet
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Technical content
N-Channel Enhancement Mode Field Effect Transistor CEZ8R04
FEATURES
40V, 49A, RDS (ON) = 7.8mW @VGS = 10V. Super high dense cell design for extremely low RDS(ON). High power and current handing capability. ABSOLUTE MAXIMUM RATINGS TC = 25 C unless otherwise noted Parameter Symbol Limit Units Drain-Source Voltage Gate-Source Voltage Maximum Power Dissipation VDS VGS ID PD IDM 29.7 ±20 V W A A V http://www.cet-mos.com Rev 1. 2023.Nov G S S S D D D D Drain Current-Continuous ID 49 A Drain Current-Pulsed a IDM 196 A P-PAK 5X6 Surface mount Package. Pb-free lead plating ; RoHS compliant. Halogen Free. Details are subject to change without notice . RDS(ON) = 12mW @VGS = 4.5V. Operating and Store Temperature Range TJ,Tstg -55 to 150 C Thermal Characteristics Thermal Resistance, Junction-to-Case Parameter Symbol Limit Units C/W4.2RqJC Thermal Resistance, Junction-to-Ambient C/W20RqJA D D D D S S S G 1 2 3 4 8 7 6 5 @RqJC RqJA RqJA RqJC Single Pulsed Avalanche Energy g Single Pulsed Avalanche Current g EAS IAS 40.5 mJ A
Electrical Characteristics TC = 25 C unless otherwise noted Parameter Symbol Min Units Off Characteristics Drain-Source Breakdown Voltage Zero Gate Voltage Drain Current Gate Body Leakage Current, Forward Gate Threshold Voltage Static Drain-Source On-Resistance BVDSS IDSS IGSSR IGSSF 7.86 -100 100 mW V nA nA µA V Gate Body Leakage Current, Reverse On Characteristics b Dynamic Characteristics c Input Capacitance Reverse Transfer Capacitance Output Capacitance Switching Characteristics c Turn-On Delay Time Turn-Off Fall Time Turn-Off Delay Time Turn-On Rise Time Total Gate Charge Gate-Source Charge Gate-Drain Charge Drain-Source Diode Characteristics and Maximun Ratings Drain-Source Diode Forward Current Drain-Source Diode Forward Voltage b Test Condition VGS = 0V, ID = 250µA VGS(th) RDS(on) Ciss Coss Crss td(on) tr td(off) tf Qg Qgs Qgd IS VSD Typ Max VDS = 40V, VGS = 0V VGS = 20V, VDS = 0V VGS = -20V, VDS = 0V VGS = VDS, ID = 250µA VGS = 10V, ID = 12A VDS = 20V, ID = 10A, VGS = 4.5V VDS = 20V, VGS = 0V, f = 1.0 MHz VGS = 0V, IS = 1A 725 250 7.7 2.8 1.2 pF pF pF ns ns ns ns nC nC nC A V VDD = 20V, ID = 20A, VGS = 10V, RGEN = 10W 129.2 mW VGS = 4.5V, ID = 8A Gate input resistance Rg f=1MHz,open Drain 2 W Notes : a.Repetitive Rating : Pulse width limited by maximum junction temperature. b.Pulse Test : Pulse Width < 300µs, Duty Cycle < 2%. c.Guaranteed by design, not subject to production testing. d.L = 1mH, IAS = 9A, VDD = 24V, RG = 25W, Starting TJ = 25 C.
Figure 12. Normalized Thermal Transient Impedance Curve
SINGLE PAD 尺寸圖 P- PAK5X6 產品外觀尺寸圖 (Product Outline Dimension) SINGLE PAD 尺寸圖 P - PA K5X6 產品外觀尺寸圖 (Product Outline Dimension) 6 .2 5 3.80 1 . 270 . 5 0 . 5 50. 770 . 5 4 . 5 0.80SINGLE PAD D A H E L1b e (2X ) c D 1 PIN #1 DOT BY MARKING 10 °TYP. 0. 10 MAX RECOMMENDED LAND PATTERN A 0.800 1.170 0.031 0.046 b 0.340 0.490 0.013 0.019 c 0.20 0.34 0.008 0.013 D 4.800 5.100 0.009 0.011 D1 3.800 4.200 0.150 0.165 D2 3.180 3.78 0.125 0.149 D3 0.150 0.360 0.006 0.142 E 5.650 5.900 0.222 0.232 e 1.270 TYP 0.050 TYP H 5.900 6.150 0.232 0.242 L1 0.050 0.250 0.002 0.010 L2 0.380 0.620 0.015 0.024 L3 0.380 0.75 0.015 0.030 CEZ8R04