CET6961 CET-MOS | Alldatasheet
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P-Channel Enhancement Mode Field Effect Transistor CET6961
FEATURES
-60V, -4.1A, RDS(ON) = 110mW @VGS = -10V. RDS(ON) = 150mW @VGS = -4.5V. High dense cell design for extremely low RDS(ON). Rugged and reliable. SOT-223 package. ABSOLUTE MAXIMUM RATINGS TA = 25 C unless otherwise noted Parameter Symbol Limit Units Drain-Source Voltage Gate-Source Voltage Drain Current-Continuous Drain Current-Pulsed a Maximum Power Dissipation VDS VGS ID PD IDM -60 2.98 -16.4 -4.1 ±20 V W A A V S G D SOT-223 G D D S RoHS compliant. http://www.cet-mos.com Rev 1. 2022.May Details are subject to change without notice . Operating and Store Temperature Range TJ,Tstg -55 to 150 C Thermal Characteristics Thermal Resistance, Junction-to-Ambient b Parameter Symbol Limit Units C/W42RqJA
Electrical Characteristics TA = 25 C unless otherwise noted Parameter Symbol Min Units Off Characteristics Drain-Source Breakdown Voltage Zero Gate Voltage Drain Current Gate Body Leakage Current, Forward Gate Threshold Voltage Static Drain-Source On-Resistance BVDSS IDSS IGSSR IGSSF 110 -1 -3 -100 100 mW V nA nA µA V Gate Body Leakage Current, Reverse On Characteristics c Dynamic Characteristics d Input Capacitance Reverse Transfer Capacitance Output Capacitance Switching Characteristics d Turn-On Delay Time Turn-Off Fall Time Turn-Off Delay Time Turn-On Rise Time Total Gate Charge Gate-Source Charge Gate-Drain Charge Drain-Source Diode Characteristics and Maximun Ratings Drain-Source Diode Forward Current Drain-Source Diode Forward Voltage c Test Condition VGS = 0V, ID = -250µA VGS(th) RDS(on) Ciss Coss Crss td(on) tr td(off) tf Qg Qgs Qgd IS VSD Typ Max -60 VDS = -60V, VGS = 0V VGS = 20V, VDS = 0V VGS = -20V, VDS = 0V VGS = VDS, ID = -250µA VGS = -10V, ID = -1A VDD = -30V, ID = -1A, VGS= -10V, RGEN= 6W VDS = -30V, ID = -3A, VGS = -4.5V VDS = -30V, VGS = 0V, f = 1.0 MHz VGS = 0V, IS = -1A 960 8.5 2.1 3.3 -2.4 -1.2 pF pF pF ns ns ns ns nC nC nC A V 150 mW VGS = -4.5V, ID =-1A 106 Notes : a.Repetitive Rating : Pulse width limited by maximum junction temperature b.Surface Mounted on FR4 Board, t < 10 sec. c.Pulse Test : Pulse Width < 300µs, Duty Cycle < 2%. d.Guaranteed by design, not subject to production testing.
Figure 1. Output Characteristics Figure 2. Transfer Characteristics Figure 3. Capacitance Figure 5. Gate Threshold Variation Figure 6. Body Diode Forward Voltage Figure 4. On-Resistance Variation
102 VGS=0V
Figure 12. Normalized Thermal Transient Impedance Curve