CES2315 CET-MOS | Alldatasheet
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Technical content
P-Channel Enhancement Mode Field Effect Transistor CES2315
FEATURES
-30V, -4A, RDS(ON) = 50mW @VGS = -10V. RDS(ON) = 85mW @VGS = -4.5V. High dense cell design for extremely low RDS(ON). Rugged and reliable. SOT-23 package. ABSOLUTE MAXIMUM RATINGS TA = 25 C unless otherwise noted Parameter Symbol Rating Units Drain-Source Voltage Gate-Source Voltage Drain Current-Continuous Drain Current-Pulsed a Maximum Power Dissipation VDS VGS ID PD IDM -30 1.25 -16 - 4 V W A A S G D G D S SOT-23 RoHS compliant http://www.cet-mos.com Rev 3. 2020.June Details are subject to change without notice . V±25 Operating and Store Temperature Range TJ,Tstg -55 to 150 C Thermal Characteristics Thermal Resistance, Junction-to-Ambient b Parameter Symbol Limit Units C/W100RqJA
Electrical Characteristics TA = 25 C unless otherwise noted Parameter Symbol Min Units Off Characteristics Drain-Source Breakdown Voltage Zero Gate Voltage Drain Current Gate Body Leakage Current, Forward Gate Threshold Voltage Static Drain-Source On-Resistance BVDSS IDSS IGSSR IGSSF 5040 -100 100 mW V nA nA µA V Gate Body Leakage Current, Reverse On Characteristics c Dynamic Characteristics d Input Capacitance Reverse Transfer Capacitance Output Capacitance Switching Characteristics d Turn-On Delay Time Turn-Off Fall Time Turn-Off Delay Time Turn-On Rise Time Total Gate Charge Gate-Source Charge Gate-Drain Charge Drain-Source Diode Characteristics and Maximun Ratings Drain-Source Diode Forward Current b Drain-Source Diode Forward Voltage c Test Condition VGS = 0V, ID = -250µA VGS(th) RDS(on) Ciss Coss Crss td(on) tr td(off) tf Qg Qgs Qgd IS VSD Typ Max -30 VDS = -30V, VGS = 0V VGS = 20V, VDS = 0V VGS = -20V, VDS = 0V VGS = VDS, ID = -250µA VGS = -10V, ID = -3.8A VGS = -4.5V, ID = -3A VGS = 0V, IS = -1A 650 130 11.2 1.7 2.0 -1.2 8560 mW pF pF pF ns ns ns ns nC nC nC A V VDD = -15V, ID = -1A, VGS = -10V, RGEN = 6W VDS = -15V, ID = -3.6A, VGS = -10V VDS = -15V, VGS = 0V, f = 1.0 MHz Notes : a.Repetitive Rating : Pulse width limited by maximum junction temperature. b.Surface Mounted on FR4 Board, t < 5 sec. c.Pulse Test : Pulse Width < 300µs, Duty Cycle < 2%. d.Guaranteed by design, not subject to production testing.
Figure 12. Normalized Thermal Transient Impedance Curve