CEM1008 CET-MOS | Alldatasheet
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Technical content
Dual N-Channel Enhancement Mode Field Effect Transistor CEM1008
FEATURES
100V, 2.8A, RDS(ON) = 125mW @VGS = 10V. Super high dense cell design for extremely low RDS(ON). High power and current handing capability. Surface mount Package. ABSOLUTE MAXIMUM RATINGS TA = 25 C unless otherwise noted Parameter Symbol Limit Units Drain-Source Voltage Gate-Source Voltage Drain Current-Continuous Drain Current-Pulsed a Maximum Power Dissipation VDS VGS ID PD IDM 100 11.2 2.8 ±20 V W A A V RoHS compliant. http://www.cet-mos.com Rev 2. 2016.Dec Details are subject to change without notice . SO-8 D1 D1 D2 D2 S1 G1 S2 G2 8 7 6 5 1 2 3 4 Operating and Store Temperature Range TJ,Tstg -55 to 150 C Thermal Characteristics Thermal Resistance, Junction-to-Ambient b Parameter Symbol Limit Units C/W62.5RqJA
Parameter Symbol Min Units Off Characteristics Drain-Source Breakdown Voltage Zero Gate Voltage Drain Current Gate Body Leakage Current, Forward Gate Threshold Voltage Static Drain-Source On-Resistance BVDSS IDSS IGSSR IGSSF 125105 2 4 -100 100 mW V nA nA µA V Gate Body Leakage Current, Reverse On Characteristics c Dynamic Characteristics d Input Capacitance Reverse Transfer Capacitance Output Capacitance Switching Characteristics d Turn-On Delay Time Turn-Off Fall Time Turn-Off Delay Time Turn-On Rise Time Total Gate Charge Gate-Source Charge Gate-Drain Charge Drain-Source Diode Characteristics and Maximun Ratings Drain-Source Diode Forward Current b Drain-Source Diode Forward Voltage c Test Condition VGS = 0V, ID = 250µA VGS(th) RDS(on) Ciss Coss Crss td(on) tr td(off) tf Qg Qgs Qgd IS VSD Typ Max 100 VDS = 100V, VGS = 0V VGS = 20V, VDS = 0V VGS = -20V, VDS = 0V VGS = VDS, ID = 250µA VGS = 10V, ID = 1A VDD = 50V, ID = 2.8A, VGS = 10V, RGEN = 25W VDS = 80V, ID = 2.8A, VGS = 10V VDS = 25V, VGS = 0V, f = 1.0 MHz VGS = 0V, IS = 1A 495 105 1.4 4.8 1.5 1.2 pF pF pF ns ns ns ns nC nC nC A V Electrical Characteristics Tc = 25 C unless otherwise noted Notes : a.Repetitive Rating : Pulse width limited by maximum junction temperature. b.Surface Mounted on FR4 Board, t < 10 sec. c.Pulse Test : Pulse Width < 300µs, Duty Cycle < 2%. d.Guaranteed by design, not subject to production testing.
Figure 12. Normalized Thermal Transient Impedance Curve