CECS20N65LN CET-MOS | Alldatasheet
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FEATURES
650V, 19A, RDS(ON) = 180mW @VGS = 10V. Super High dense cell design for extremely low RDS(ON). High power and current handing capability. ABSOLUTE MAXIMUM RATINGS TA = 25 C unless otherwise noted Parameter Symbol Limit Units Drain-Source Voltage Gate-Source Voltage Drain Current-Continuous Maximum Power Dissipation VDS VGS ID PD 650 167 ±30 V W A V RoHS compliant. http://www.cet-mos.com Rev 1. 2019.Sep DFN8*8 Drain Current-Pulsed a IDM 76 A N-Channel Enhancement Mode Field Effect Transistor S G D G D S S S Details are subject to change without notice . G S S S Operating and Store Temperature Range TJ,Tstg -55 to 150 C Thermal Characteristics Thermal Resistance, Junction-to-Case b Parameter Symbol Limit Units C/W0.75RqJc
Electrical Characteristics Tc = 25 C unless otherwise noted Parameter Symbol Min Units Off Characteristics Drain-Source Breakdown Voltage Zero Gate Voltage Drain Current Gate Body Leakage Current, Forward Gate Threshold Voltage Static Drain-Source On-Resistance BVDSS IDSS IGSSR IGSSF 180150 2.5 4.5 -100 100 mW V nA nA µA V Gate Body Leakage Current, Reverse On Characteristics c Dynamic Characteristics d Input Capacitance Reverse Transfer Capacitance Output Capacitance Switching Characteristics d Turn-On Delay Time Turn-Off Fall Time Turn-Off Delay Time Turn-On Rise Time Total Gate Charge Gate-Source Charge Gate-Drain Charge Drain-Source Diode Characteristics and Maximun Ratings Drain-Source Diode Forward Current b Drain-Source Diode Forward Voltage c Test Condition VGS = 0V, ID = 250µA VGS(th) RDS(on) Ciss Coss Crss td(on) tr td(off) tf Qg Qgs Qgd Typ Max 650 VDS = 650V, VGS = 0V VGS = 30V, VDS = 0V VGS = -30V, VDS = 0V VGS = VDS, ID = 250µA VGS = 10V, ID = 10A VDD = 520V, ID = 10A, VGS = 10V, RGEN = 6W VDS = 520V, ID = 10A, VGS = 10V VDS =150V, VGS= 0V, f = 1.0 MHz 1520 7.6 9.2 1.5 pF pF pF ns ns ns ns nC nC nC A V CECS20N65LN IS VSD VGS = 0V, IS = 10A Notes : a.Repetitive Rating : Pulse width limited by maximum junction temperature. b.Surface Mounted on FR4 Board, t < 10 sec. c.Pulse Test : Pulse Width < 300µs, Duty Cycle < 2%. d.Guaranteed by design, not subject to production testing.
Figure 12. Normalized Thermal Transient Impedance Curve