CDP65C51

CDP65C51 HARRIS | Alldatasheet

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CMOS Asynchronous Communications January 1991 Interface Adapter (ACIA) Features Pinout * Compatible With 8-Bit Microprocessors PACKAGE TYPES D, E AND M * Full Duplex Operation With Buffered Recelver and Transraitter TOP VIEW * Data Set/Modem Control Functions + Internal Baud Rate Generator With 15 Programmable Baud Rates er ee {50 to 19,200) cso—f2 art gz * Program Selectable Internally or Externally Controlled Receiver esi—]326[— IG Rate mot Re * Operates at Baud Rates Up To 250,000 Via Proper Crystal or Clock made aslo os Selection mot? — aal— os * Programmable Word Lengths, Number of Stop Bits and Parity Bit Ree 2 os Generation and Detection io ho a 3 * Programmable Interrupt Control Bm tal— 00 * Program Reset aoe 7 ose * Program Selectable Serial Echo Mode Reon te Be rsi—is 8 Yoo * Two Chip Selects so aEF * 4MHz, 2MHz or 1MHz Operation (CDP65C51 and CDP6SC51A-4, -2,-1 Types, Respectively) * Single 3V to 6V Power Supply * Full TTL Compatibility * Synchronous CTS Operation

Description

The CDP6SCS1 and CDP65C51A Asynchronous Commu- the CPU to easily select the CDP65C51A operating modes nications Interface Adapters (ACIA) provide an easily and data-checking parameters and determine operational «3 implemented, program controlled interface between 8-bit status. 2= microprocessor based systems and serial communication EE data sets and modems. The CDP65C51A is identical tothe The Command Register controls parity, reciever echo | | = CDP6SCS1 except for the implementation of the CTS func- ™0de, transmitter interrupt control, the state of the RTS ine, | | ° a tion. If a not-clear-to-send signal is received during the '@celver interrupt control, and the state of the DTR line. transmission of a character, the CDP6SCS1A wil frst allow The Control Register controls the number of stop bits, completion of that transmission, and then disable the word length, receiver clock source and baud rate. ransmitter. The Status Register indicates the states of the IRO, OSR The CDP6SCS51 and CDP65CS1A have an internal baud ang OCD lines, transmitter and receiver data registers, and rate generator. This feature eliminates the need for multiple Sverrun, framing and parity error conditions. component support circuits, a crystal being the only other part required. The Transmitter baud rate can be selected The transmitter and receiver data registers are used for tem- under program control to be either 1 of 15 different rates porary data storage by the CDP65SCS1A transmit and re- from 50 to 19,200 baud, or 1/16 times an external clock ceive circuits. rate. The receiver baud rate may be selected under program control to be either the transmitter rate, or at 1/16 times an The CDPGSCS1 and CDP6SC51A-1, ~2 and -4 types are ‘external clock rate. The CDP6SC51 and CDP6SC51A have capable of interfacing with microprocessors with cycle programmable word lengths of 5, 6, 7 or 8 bits; even, odd or times of 1MHz, 2MHz and 4MHz, respectively. no parity; 1, 1% or 2 stop bits, ‘The CDP65C51 and CDP6SC51A are supplied in 28 lead The CDP65SCS1 and CDP6SC51A are designed for maxi- hermetic dual-in-line sidebrazed ceramic packages (D suf- mum programmed control from the CPU, to simplify _fix),in 28 lead dual-in-line plastic packages (E suffix) and in hardware implementation. Three separate registers permit 28 lead dual-in-line small outline (SO) packages (M) suffix. Copyright © Harris Corporation 1991 File Number 2747 5-11

CDP65C51, CDP65C51A DC SUPPLY-VOLTAGE RANGE, (Voo) DC INPUT CURRENT, ANY ONE INPUT o000...00.occcccecscceecnsereccsscrecsceresstersereretiereeseeesees 210 mA, POWER DISSIPATION PER PACKAGE (Po): For Ta = -85 to +100°C (PACKAGE TYPE D) oo... seoccecccccessserecsscerrtsesterserecsateeessesrersses 500 MW For Ta = 40 to +85°C (PACKAGE TYPE M)* oo... .ccccceccscceecseecesstteesseesessceeesseeeesstereeseees 425 mW DEVICE DISSIPATION PER OUTPUT TRANSISTOR OPERATING-TEMPERATURE RANGE (T,): PACKAGE TYPE D 20.02... ccceeeeseceesecencereeseeeeeseteeereeeessetsesssesetsessssseesessse “65:10 +125°C STORAGE-TEMPERATURE RANGE (Ty) «2.000022 eccccecccceceseceeessceseseceeeseeeesseseeseeesees 650 4150°C LEAD TEMPERATURE (DURING SOLDERING): * Printed-circuit board mount: §7 mm x 87 mm minimum area x 1.6 mm thick G10 epoxy glass, or equivalent. + RECOMMENDED OPERATING CONDITIONS at T, = -40° to +85°C For maximum reliability, nominal operating conditions should be selected so that operation Is always within the following ranges: [aaa] US | eee | Be Operating Vonage Range tt ety | [LinputVoltageRange Cd Ves oY STATIC ELECTRICAL CHARACTERISTICS at Ts = ~40° to +85°C, Voo = 5V + 5% Peers a Or [Quiescent Device Current to S| T0200 A ‘Output Low Current (Sinking): Vo. = 0.4 V Tow | m™ | D0-D7, TxD, RxC, RTS, DTR, TRO ‘Output High Current (Sourcing): Von = 4.6 V Ton |e | - | - | (D0-D7, TxD, RxC, ATS, OTR) Kfoonmomemecminy | | ~ | me | (00-D7, TxD, RxC, ATS, DTA, TRO) P= | - |» | (D0-D7, TxD, RxC, RTS, DTR) [InputLowVoltage Me Tes PV Input High Voltage Vw (Except XTLI and XTLO) P= | om | (XTLI and XTLO) Voo Input Leakage Current: Vin= 0 to 5V Tw Ht (92, RAW, RES, CS0, CST, ASO, RS1, CTS, RxD, OCD, OSA) ” [Input Leakage Current for High Impedance State(D0-O7)nss_—| TT 12 [A | [Output Leakage Current (off state): Vour=5V(RG) torr =| =P 2A [Input Capacitance (except XTLiandXTLO) Cw Tt [Output Capacitance Cor SP CP tT 512

CDP65C51, CDP65C51A (CDP65C51/51A INTERFACE REQUIREMENTS This is a description of the interface requirements for the _D0-D7 (Data Bus) (18-25) CDP6SC51 and CDP6SCS51A. Fig. 1 Is the Interface Diagram The D0-D7 pins are the eight data lines used to transfer data and the Terminal Diagram shows the pinout configuration for between the processor and the CDP65C51/51A. These lines the CDP6SC51A. are bidirectional and are normally high impedance except dur- ing Read cycles when the CDP65C51/51A are selected, <=, ©80, CSI (Chip Selects) (2, 3) os coor > | ati | The two chip select inputs are normally connected to the pro- cessor address lines either directly or through decoders. The TRANSMIT CDP65C51/51A are selected when CSO Is high and CS1 is DATAS ww _ mad low. ~~ ve RSO, RS1 (Register Selects) (13, 14) SC The two register select lines are normally connected to the pro- DB’ cessor address lines to allow the processor to select the vari- Eid 7 me 24S CDP65C51/51A intemal registers. The following table eS xu Shows the internal register select coding. os GENERATOR mo Rst TABLET [Ast [ rso [Write [Read Transmit Data | Receiver Data wi sconTmoL pal Register Register Programmed Reset| Status Register (Data is “Don't woo m0 Care”) vss [+ fo [Command Register es | Control Register Only the Command and Control registers are read/write. ‘920m-36860 The Programmed Reset operation does not cause any data transfer, but is used to clear bits 4 through 0 in the Fig. 1 - COP65C51/51A interface diagram Command Register and bit 2 in the Status Register. The |. Control Register is unchanged by a Programmed Reset. It | o 3 MICROPROCESSOR INTERFACE should be noted that the Programmed Reset is slightly |B = ‘SIGNAL DESCRIPTION different from the Hardware Reset (RES); these-differences |= = FE cnesen (4) are shown in Figs. 3, 4 and §. Se During system initialization a low on the RES: input will ACIA/MODEM INTERFACE cause a hardware reset to occur. The Command Register SIGNAL DESCRIPTION and the Control Register will be cleared. The Status Register will be cleared with the exception of the indications XTLI, XTLO (Crystal Pins) (6, 7) of Data Set Ready and Data Carrier Detect, which are These pins are normally directly connected to the external externally controlled by the DSR and OCD lines, and the crystal (1.8432 MHz) used to derive the various baud rates transmitter Empty bit, which will be set. A hardware reset is (see “Generation of Non-Standard Baud Rates”). Alterna- required after power-up. tively, an externally generated clock may be used to drive the XTLI pin, in which case the XTLO pin must float. XTLI is $2 (Input Clock) (27) the input pin for the transmit clock. The input clock is the system @2 clock and is used to clock all data transfers between the system microprocessor and °*0 (Transmit Data) (10) . the CDP65C51/51A. The TxD output line is used to transfer serial NRZ BIW (Reais (nonreturn-to-zero) data to the modem. The LSB (least /W (Read/Write) (28) significant bit) of the Transmit Data Register is the first data The R/W input, generated by the microprocessor, isusedto bit transmitted and the rate of data transmission is control the direction of data transfers. AhighontheR/Wpin determined by the baud rate selected or under control of an allows the processor to read the data supplied by the external clock. This selection is made by programming the CDP65C51/51A, alow allows a write to the CDP6SC51/51A. Control Register. IRQ (Interrupt Request) (26) RxD (Receive Data) (12) The iRQ pin isan interrupt output from the interrupt control The RxD input line is used to transfer serial NRZ data into logic. It is an open drain output permitting several devices the ACIA from the modem, LSB first. The receiver data rate to be connected to the common IRQ microprocessorinput. _ is either the programmed baud rate or under the control of Normally at high level, IRQ goes low when an interrupt an externally generated receiver clock. The selection is ‘occurs. made by programming the Control Register. 5-13

CDP65C51, CDP65C51A CDP65C51/51A INTERFACE REQUIREMENTS (Cont'd) RxC (Receive Clock) (5) DTR (Data Terminal Ready) (11) The RxC is a bidirectional pin which serves as either the This output pin is used to indicate the status of the CDP65C51/ receiver 16X clock input or the receiver 16X clock output. —_§1A to the modem. A low on DTA Indicates the CDP65C51/ The latter mode results if the internal baud-rategeneratoris 51 is enabled, a high indicates it is disabled. The processor selected for receiver data clocking. controls this pin via bit 0 of the Command Register. ATS (Request to Send) (8) een se fea an nd the COPSSC: The RTS output pin is used to control the modem from the input pin is used to indicate to the CDPESCS1/51A processor. The state of the ATS pin is determined by the _ "Status of the modem. A low indicates the “ready” state and contents of the Command Register. a high, “not ready”. DCD (Data Carrier Detect) (16) CTS (Clear to Send) (9) The DCD input pin is used to indicate to the CDP65C51/51A The GTS input pin is used to control the transmitter __ the status of the carrier detect output of the modem. A low indi- operation. Theenablestateis with CTSiow. Thetransmitter _cates that the modem carrier signal is present and a high, that it is automatically disabled if CTS is high. is not. CDP65C51 AND CDP65C51A INTERNAL ORGANIZATION This is a functional description of the CDP65C51/51A. Ablock —_can cause an interrupt will set bit7 and the appropriate bit of diagram of the CDP65C51/51A is presented in Fig. 2. bits 3 through 6 in the Status Register if enabled. Bits 5 and6 correspond to the Data Carrier Detect (DCD) logic and the DATA BUS BUFFERS Data Set Ready (DSR) logic. Bits 3 and 4 correspond to the The Data Bus Buffer interfaces the system data lines to the in- Receiver Data Register full and the Transmitter DataRegister temal data bus. The Data Bus Buffer is bi-directional. When the _ empty conditions. These conditions can cause an interrupt R/W line is high an the chip is selected, the Data Bus Buffer request if enabled by the Command Register. passes the Data to the system data lines from the CDP65C51/ VO CONTROL 514 internal data bus, When the R/W line is low and the chip's tne 1/0 Control Logi: i gic controls the selection of internal selected, the Data Bus Butter writes the data from the system registers in preparation for a data transfer on the internal data bus to the internal data bus. data bus and the direction of the transfer to or from the INTERRUPT LOGIC register. The interrupt Logic will cause the TRG line to the — The registers are selected by the Register Select and Chip microprocessor to-go low when conditions are met that Select and Read/Write lines as described in Table |, previously. Dara TRANSMIT iRo-<—fnrenAuer| ? BoD i Hea | i Ke 3 Hy t aw | > ‘Bauo fac co. i Iho) cera on mu = on comms oR eo of] [Lape = Fig. 2 - Internal organization. s2cM-36890R" 5-14

CDP65C51, CDP65C51A CDP65C51/51A INTERNAL ORGANIZATION (Cont'd) TIMING AND CONTROL Recelver Data Register Full (Bit 3) The Timing and Control logic controls the timing of data This bit goes to a “1” when the CDP65C51/51A transfers data transfers on the internal data bus and the registers, theData from the Receiver Shift Register to the Receiver Data Bus Buffer, and the microprocessor data bus, and the Register, and goes to a “0” when the processor reads the hardware reset features. Receiver Data Register. Timing is controlled by the system @2 clock input. The chip Transmitter Data Register Empty (Bit 4) will perform data transfers to or from the microcomputer This bit goes to a “1” when the CDP65C51/51A transfers data data bus during the $2 high period when selected. from the Transmitter Data Register to the Transmitter Shift All registers will be initialized by the Timing and Control Register, and goes to a “0” when the processor writes new Logic when the Reset (RES) line goes ow. Seethe individual data onto the Transmitter Data Register. register description for thestate of the registers following Data Carrier Detect (Bit 5) and hardware reset. Data Set Ready (Bit 6) TRANSMITTER AND RECEIVER DATA REGISTERS ‘These bits reflect the levels of the DCD and DSR inputs to the '1/51A. A “0” indicates a high (false). Whenever These registers are used a temporary data storage for the CDP65C5 CDP65C51/51A Transmit and Recelve circuits. Both the either of these Inputs changes state, in immediate processor mitter and Receiver are selected by a Register Select 0 ‘lor occurs sree ao0 When to inerae ee (RSO) and Register Select 1 (RS1) low condition. The the Command Register is a“0"). When the interrupt occurs, Read/Write line determines which actually uses the internal _ status bits will indicate the levels of the inputs immediately data bus: the Transmitter Data Registeriswriteonly andthe afterthe change ofstate occurred. Subsequentleve changes leceiver Data Register is read only. will not affect é status bits until the ister is ist bi it interrogated by the processor. At that time, another interrupt Bit 0 is the first bit to be transmitted from the Transmitter Data Register (least significant bit first). The higher order wi immediately occur and the status bits will reflect the bits follow in order. Unused bits in this register are “don't iH input levels. 1,0 (en2),and care”. ‘raming Error (Bit 1), Overrun (Bit 2), a The Receiver Data Register holds the first received data bit Parity Error (BIt 0) in bit 0 (least significant bit first). Unused high-order bits None of these bits causes a processor interrupt to occur, are "0". Parity bits are not contained in the Receiver Data _ but they are normally checked at the time the Receiver Data Register. They are stripped off after being used for parity Register is read so that the validity of the data can be checking. verified. STATUS REGISTER Interrupt (Bit 7) Fig. 3 indicates the format of the CDP65C51/51A Status Regi- This bit goes to a “0” when the Status Register has been ster. A description of each status bit follows. readby the processor, and goes toa"I" whenever any kind | yp 3 of interru urs. eeeeeee CONTROL REGISTER EE The Control Register selects the desired transmitter baud | © ONO PARITY ERROR rate, receiver clock source, word length, andthe number of | ™ 9 Banrty enon DerectED stop bits. FRAMING ERROR Selected Baud Rate (Bits 0, 1, 2, 3) 1” FRAMING ERROR OETECTEO These bits, set by the processor, select the Transmitter Oven baud rate, which can beat 1/16 an external clock rate or one $OvERMUN Has OCCURRED of 15 other rates controlled by the internal baud-rate RECEIVER DATA REGISTER FULL generator as shown in Fig. 4. cet Receiver Clock Source (Bit 4) ‘TRANSMITTER DATA REGISTER EMPTY This bit controls the clock source to the Receiver. A “0” pete dail causes the Receiver to operate at a baud rate of 1/16 an . external clock. A "'1” causes the Receiver to operate at the oeepuam cere same baud rate as is selected for the transmitter as shown in $7 BEB nian WoT BErEcrED) Fig. 4. oe comneaon Word Length (Bits 5, 6)

1 Se meninornenon These bits determine the word length to be used (5, 6,7 or8

ONO INTERRUPT (INS PIN HGH. bits). Fig. 4 shows the configuration for each number of bits TCINTERRUPTHAS OCCURRED TRO PINLOM) — desired. besaae Tene oro oN ‘Stop Bit Number (Bit 7) [o]=|=[ioJofoTo) wanowane reser (Re5} This bit determines the number of stop bits used. A “0” EEFEF TOF Fjesocnam reser szewserton always indicates one stop bit. A“1" indicates 1% stop bits if the word length is S with no parity selected, 1 stop bit if the word length is 8 with parity selected, and 2 stop bits in all Fig. 3 - Status register format. other configurations. 5-15

CDP65C51, CDP65C51A ‘CDP65C51/51A INTERNAL ORGANIZATION (Cont'd) Data Terminal Ready (Bit 0) 2 + This bit enables all selected interrupts and controls the [:>" artical * [seraserstsomisar state of the Data Terminal Ready (OTH) line. AO" indicates LI ee the microcomputer system is not ready by setting the OTR line high. A “1” indicates the microcomputer system is SELECTED BAUD RATES ready be setting the DTA line low. When the DTRbitis set to $258 aexexrernarciock “0”, the receiver and transmitter are both disabled. Soot se nave. ere Ts tivo Recelver Interrupt Control (Bit 1) igo ae 84U8 This bit disables the Receiver from generating an interrupt 0110 © 300 sauo when set to a'“1". The Receiver interrupt is enabled when 8488 Ta00 BAUD this bit is set to a “0” and Bit 0 is set to a"1”. 180% ta00 stue fero ieo Sito Transmitter Interrupt Control (Bits 2, 3)

1190 Me £8u2 These bits control the state of the Ready to Send (ATS) line

130 ee BAvp and the Transmitter interrupt. Fig. 5 shows the various vent toe ‘8U0 configurations of the ATS line and Transmit Interrupt bit RECEIVER CLOCK SOURCE (RCS) settings. 0- EXTERNAL RECEIVER CLOCK,

1 BAUD RATE: Receiver Echo Mode (Bit 4)

eee This bit enables the Receiver Echo Mode. Bits 2. and 3 must 00 sarTs be zero. In the Receiver Echo Mode, the Transmitter returns 91 rare each transmission received by the Receiver delayed by % bit 44 sens time. A “1" enables the Receiver Echo Mode. A “0” bit STOP BIT NUMBER (SBN) disables the mode. 7es43210 _ Soa Ree aire Parity Mode Enable (Bit 5) CREPE tccmuncser _, Fonwtcsanoworany This bit enables parity bit generation and checking. A“O" Tonwceanoranity disables parity bit generation by the Transmitter and parity bit checking by the Receiver. A'1” bit enables generation oe 36701 and checking of parity bits. Fig, 4 - COP65C51/51A control register. Parity Mode Control (Bits 6, 7) These bits determine the type of parity generated by the COMMAND REGISTER Transmitter, (even, odd, mark or space) and the type of The Command Register controls specific modes and _ parity check done by the Receiver (even, odd, or no check). functions (Fig. 5). Fig. 5 shows the possible bit configurations for the Parity Mode Control bits. 7 6 s «4 3 2 5 0 [rc] [ec _] Ld LJ DATA TERMINAL READY (OTR) 0- DATA TERMINAL NOT READY (OTR PIN HIGH,

1 ATA TERMINAL READY (OTR PIN LOW

RECEIVER INTERRUPT CONTROL (RD) oc neceiven invennurt enasteo RECEIVER INTERRUPT DIsmBUEO TRANSMITTER INTERRUPT CONTROL (TIC) =e Noa 8 8 vg won, rmansmir rennurr ovsanveo™ 0} GTS- Low. Taawsu WTeMAUrr Enaate { 0 AYE- Cow, TaansMIT IvTERRUPY DIsaaLeD

19 RYS: tow: TaansMr INTERRUPT BISABLED

RECEIVER ECHO MODE (REM) = RECEIVER NORMAL MODE NOTE: When changing command register ~ RECEIVER EoMO MO! bits 3 and 2 from 0,1 to 1,0 a ‘break’ may be Panty MODE ENABLE PME) mary ott generated. To avoid the generation of this °° Rgioaniry orrcenenareo. break, always change from 0,1 to 0,0 to 1,0. Paniry cueck bisaeceo += PARITY MODE ENABLED. PARITY MODE CONTROL (PMC) 1esaa210 3 § 000 panrry rrasmiTTED/RECEIVEO [oJoJofoToToToTo] wanowane nese (RES) 39 Mani Paniry aT TRawsMirreD [EL-l-lejejorefo}nocnan neser Panrty chek oisaaced. 1+ Soace vanise pit transmirTeo Panity CHECK DISABLED. “017s 2 ANO.3 MUST BE ZERO FOR RECEIVER ECHO MODE. HTS WiLL OE LOW. Fig. 5 - CDP65C51/51A command register #470081 5-16

CDP65C51, CDP65C51A CDP65C51/51A INTERNAL ORGANIZATION (Cont'd) TRANSMITTER AND RECEIVER ‘SHIFT REGISTER ‘xD Bits 0-3 of the Control Register select the divisor used to generate the baud rate for the Transmitter. If the Receiver clock is to use the same baud rate as the transmitter, then Suse RxC becomes an output and can be used to slave other cir- (8) cuits to the CDP65C51/51A Fig. 6 shows the Transmitter and Receiver layout. CONTROL me vu Fig. 6 - Transmitter receiver clock circuits. ‘CDP65C51/51A OPERATION ‘TRANSMITTER AND RECEIVER OPERATION Continous Data Transmit (Fig. 7) In the normal operating mode, the processor interrupt (iRQ) is Processor must then identify that the Transmit Data Register is used to signal when the CDP65C51/51A is ready to accept the ready to be loaded and must then load it with the next data next data word to be transmitted. This interrupt occurs at the word. This must occur before the end of the Stop Bit, otherwise beginning of the Start Bit. When the processor reads the Status a continuous “Mark” will be transmitted. Register of the CDP65C51/51A, the interrupt is cleared. The LL “LEP EP) LEE EDT LEP EE) LEED EET L UA at La oat | 1 i i i ' a2 H i i i ! Ss = ee af processon 3 (TRANSMIT OATA COAG NEW DATA a TOCKEAR Fig. 7 - Continuous data transmit. Similar to the above case, the normal mode is to generate a ‘Stop Bit The processor must read the Status Register and rad Processor interrupt when the CDP65C51/51A has received a the data word before the next interrupt, otherwise the Overrun full data word. This occurs at about the 8/16 point through the condition occurs. EER EEE Gere — er a START - | START EE ' Ler ae) 1 LEI ~ ! ) | eageusige mresmson nga mas Fig. 8 - Continuous data receive. 5-17

CDP65C51, CDP65C51A (CDP65C51/51A OPERATION (Cont'd) Transmit Data Register Not Loaded By Processor (Fig. 9) Ifthe processor is unable toload the Transmit ata Register processor finally loads new data, a Start Bit immediately in the allocated time, then the TxO line will go to the occurs, the data word transmission is started, and another “MARK” condition until the data is loaded. When the interrupt is initiated, signaling for the next data word. cnanen CconriNvoUS “MAR Han ants cnanansa sro . stor . . oon . J [ell EE cnanacren LaelT EE LET EL | roe | | Ys \\ Ricmuer | [Soes wer Zone ron oara ew ORTAIN WHEN PROCESSOR FINALLY LOADS mearsen ite rennvers _MEWDRTA. TRANSMISSION STANTS. Enerr Conmucat IMMEDIATELY AND INTERRUPT ENARACTER RATE OCCURS, INOICATING TRANSMIT Processor Even touch" DATA REGIoTER Emery reaos, novarars s2cm-se7aent stares Trasunre0 necisren Fig. 9 - Transmit data register not loaded by processor. Effect of CTS on CDP65SC51 Transmitter (Fig. 10) GTS is the Clear-to-Send signal generated by the modem. _ indicate the Transient Data Register is empty. ‘Since there is {tis normally low (true state) but may go high in the event of _ no status bit for CTS, the processor must deduce that CTS some modem problems. When this occurs, the TxD line has gone to the False (high) state. This is covered later. CTS immediately goes to the “Mark” condition. Interrupts contin- is a transmit control line only, and has no effect on the ue at the same rate, but the Status Register does not CDP65C51 Receiver Operation. cha en nanan ‘CONTINUOUS “MARK” “ET EPP EER Sre | | — im NOT CLEARTOSEND os CLEAR TOSEND | EB cots ay eroceston nao InDIcaTING MODEM PROCESSOR STATUs REGISTER. IBypraeaor ro. Inrennupr’ SMCEoRrA REGISTER Reece outa reo Ar wonwa TSgrtiurry;macksson IumeDurevy oes Stanret” Must oebucE THAT Toran" CONITION TIME Evers sounce or INtenauer rm3 1s Covenro eustWiene ‘iris nOTE) s2cu-26798 Fig. 10 ~ Effect of CTS on CDP65C51 transmitter 5-18

CDP65C51, CDP65C51A (CDP65C51/51A OPERATION (Cont'd) TRANSMITTER AND RECEIVER OPERATION (Cont'd) Effect of CTS on CDP65C51A Transmitter (Fig. 10A) CTS is the Clear-to-Send signal generated by the modem. It _ shifted out of the Transmitter Shift Register. Since there is is normally low (true state) but may go high in the event of _no status bit for GTS, the processor must deduce that CTS some modem problems. When this occurs, the TxD line has gone to the False (high) state. This is covered later. CTS goes to the "MARK" condition following the complete is a transmit control line only, and has no effect on the transmission of any character which is currently being | CDP65C51A Receiver Operation. Normal transmission will resume when CTS goes low again. onan an CHAR anes CONTINUOUS MARK" Eo -- Ea “ET ED Re EERE EET = iorsnorassenren Toawnre ets soestow Nor CLEAR-TO.SEND as CLEAR-TO-SEND, H _ | inoientnc wooo Snot neaor oes To mann ConoiTion Stren commcere cnamncren ‘Stnawsurrteo Fig. 10A - Effect of CTS on CDP65SCS51A transmitter ‘ Effect of Overrun on Receiver (Fig. 11) rd If the processor doesnot read the Receiver DataRegisterin Data Register, but the Overrun status bit is set. Thus, the | & the allocated time, then, when the following interrupt Data Register will contain the last valid data word received | ™ ‘occurs, the new data word is nottransferredtothe Receiver _ and all following data is lost. Hanan cwananss Han ent? onan ene a ak a ASE CONCORECCsCOREOCeCOREODECE START - | SR - | Star - START - | | | | ina {7 Fonmeceiven STATUS. | READ OAT | | PRENOUS BATA OVERRUN, para Reaister REGISTER sEGISTEN Sr SET me Srarus mS N ~ SS Novennun BIT SET IN, —— ‘Starus neGisven Fig. 11 - Effect of overrun on receiver. 5-19

CDP65C51, CDP65C51A (CDP65C51/51A OPERATION (Cont'd) TRANSMITTER AND RECEIVER OPERATION (Cont'd) Echo Mode Timing (Fig. 12) In Echo Mode, the TxD linere-transmits:the data on the RxD line, delayed by % of the bit time. Fe EE EE PEE z Sogeoo szomaerer 172 oxTA BIT OU Fig. 12 - Echo mode timing. Effect of CTS on Echo Mode Operation (Fig. 13) See “Effect of CTS on Transmitter” forthe effect of CTS.on —_the processor interrupts signify that the Receiver Data the Transmitter. Receiver operation is unaffected by CTS, _Registeris full, so the processor has no way of knowing that 80, in Echo Mode, the Transmitter is affected in the same the Transmitter has ceased to echo. way as “Effect of CTS on Transmitter”. In this case however, cHan en CHAR ant CHAR ene? CHAR E43 Sl NI TTS a sro _ stor . toe . 10> . ~ PLETED) | PEPE Lett EET LET EL mm NOT-CLEAR-TO-SEND os reo) LPT EET | Pl Svan START ) | EFS Gors 10. Fase" CONDITION onmat - RECEWER DATA inreanuprs ecu sera0 Fig. 13 - Effect of CTS on echo mode. 5-20

CDP65C51, CDP65C51A €DPSSC51/514 OPERATION (Cont) TRANSMITTER AND RECEIVER OPERATION (Cont'd) Overrun in Echo Mode (Fig. 14) If Overrun occurs in Echo Mode, the Receiver isaffectedthe —_ line goes to the "MARK" condition until the first Start Bit same way as described in “Effect of Overrun on Receiver”. _ after the Receiver Data Register is read by the processor. For the re-transmitted data, when overrun occurs, the TxD J LEP EET LEPT ECT LET ECT LferT Ted Pa K— | T — a ee LET [Tal Tek ATA REGISTER PATA REGISTER CHARACTER (#n) RESUMES BEADS INDITION ~ Fig. 14 - Overrun in echo mode. Framing Error (Fig. 15) Framing Error is caused by the absence of Stop Bit(s) on Framing Error separately, so the status bit will always g received data. The status bit is set when the processor _ reflect the last data word received. 3 7 interrupt occurs. Subsequent data words are tested for ao sa ee i I te Ere aL nl = ll ll fig, 18-Framing err 5-21

CDP65C51, CDP65C51A ‘CDP65C51/51A OPERATION (Cont'd) ‘TRANSMITTER AND RECEIVER OPERATION (Cont'd) Effect of DCD on Receiver (Fig. 16) DCD is a modem output used to indicate the status of the carr | Once such a change of state occurs, subsequent transitions er frequency detection circuit of the modem. This line goes _will not cause interrupts or changes in the Status Register until high for a loss of carrier. Normally, when this occurs, the mo- the first interrupt is serviced. When the Status Register is read dem will stop transmitting data (RxD on the CDP65C51/51A _by the processor, the CDP65C51/51A automatically checks ‘some time later). The CDP65C51/51A will cause a processor _the level of the DCD line, and if it has changed, another inter- ‘interrupt whenever DCD changes state and will indicate this rupt occurs. condition via the Status Register. ape) H Lee ely L Ly sgose | ‘seus piste | | | we ——- — TTT i ssstraet i / ee ee RET HE, | ee GOING HIGH Gone tow ENABLEDUNTIL necewven Fig. 16- Ect of BSB on csv Timing with 1% Stop Bits (Fig. 17) It is possible to select 1% Stop Bits, but this occurs only for processor interrupt for Receiver Data Register Full occurs 5-bit data words with no parity bit. In this case, the halfway through the trailing half-Stop Bit. Fig. 17 Timing wt 1-172 stop bs 5-22

CDP65C51, CDP65C51A TRANSMITTER AND RECEIVER OPERATION (Cont'd) Transmit Continuous “BREAK” (Fig. 18) The mode is selected via the CDP65C51/51A Command When the Command Register is programmed back to nor- Register and causes the Transmitter to send continuous mal transmit mode, a Stop Bit is generated and normal “BREAK” characters after both the transmitter and trans- transmission continues. mitter-holding registers have been emptied. VTS rr ae ve LET EET Leis eet RECT LEE rp ~ START ~ pe ~ er = I N O TRANSMIT Tranemit Ec ss Receive Continuous “BREAK” (Fig. 19) 2 In the event the modem transmits continous “BREAK” Reception will resume only after a Stop Bit is encountered 3 FJ characters, the CDP65C51/51A will terminate receiving. by the CDP6SC51/51A. ez of — ; —— a wo TT EET Leas PLT Lit mS | non Lewore: X 5-23

CDP65C51, CDP65C51A ‘COP65C51/51A OPERATION (Cont'd) STATUS REGISTER OPERATION 2. If Bit 0 of Command Register is “0” (disabled), then - a) All interrupts disabled, including those caused by Because of the special functions of the various status bits, DCD and DSR transitions. there is a suggested sequence for checking them. When an _b) Receiver disabled, but a character currently being interrupt occurs, the CDP65C51/51A should be interrogated, received will be completed first. as follows: c) Transmitter is disabled after both the Transmit Data and Tran: ft 1. Read Status Register d Transmit Shift Registers have been emptied This operation automatically clears Bit 7 (IAQ), O94 Parity occurs when the sum ofall the "1" bits in the data word (including th i Subsequent transitions on BSR and BCD will cause (including the parity bit) is odd, another interrupt 4. In the Receive Mode, the received parity bit does not go ‘ into the Receiver Data Register, but is used to generate 2. Check IRQ Bit parity error for the Status Register. 4 not set, interrupt source is not the CDP65C51/51A. 5. Transmitter and Receiver may be in full operation 3. Check DCD and OS simultaneously. This is “full-duplex” mode These must be compared to their previous levels, which 6. If the RxD line inadvertently goes low and then high must have been saved by the processor. If they are both during the first 9 receiver clocks after a Stop Bit; a false “9” (modem “on-line") and they are unchanged then the Start Bit will result. remaining bits must be checked. For false Start Bit detection, the CDP65C51/51A does not 4. Check ROAF (Bit 3) begin to receive data, instead, only a true Start Bit initiates Check for Receiver Data Register Full ; vue ‘operation. recaution to consider with the crystal MI 5. Check Parity, Overrun, and Framing Error (Bits 0-2) circuit ie crystal oscillator Only if Receiver Data Register is Full The XTLI input may be used as an external clock input. The XTLO pin must be floating and may not be 6. Check TORE (Bit 4) used for any other function. Check for Transmitter Data Register Empty. 8. DCD and DSR transitions, although causing immediate 7. If none of the above, then CTS must have gone to the Processor interrupts, have no effect on transmitter False (high) state Operation. Data will continue to be sent, unless the processor forces transmitter to turn off. Since these are high-impedance inputs, they must not be permitted to PROGRAMMED RESET OPERATION float (un-connected). If unused, they must be terminated A program reset occurs when the processor performs a write either to Gnd or Vop. operation to the CDP65SC51/51A with ASO high and RS1 low. The program reset operates somewhat different from GENERATION OF NON-STANDARD BAUD RATES the hardware reset (RES pin) and is described as follows: 1. Internal registers are not completely cleared. The data. PW!sors sheet indicates the effect of a program reset on internal__ The internal counter/divider circuit selects the appropriate registers. divisor for the crystal frequency by means of bits 0-3 of the 2. The OTR line goes high immediately. COP65C51/51A Control Register. . The divisors, then, are determined by bits 0-3 in the Control 3. Receiver and transmitter interrupts are disabled fs immediately. If7RQ is low when the reset occurs, itstays P°9!Ster and their values are shown in Table I low until serviced, uniess interrupt was caused by DCD. orbSR transition. ia ¥ Generating Other Baud Rates 4. DGD and DSR interrupts disabled immediately. IfTRQis 8Y using a different crystal, other baud rates may be low and was caused by DCD or DSR, then it goes high, 9enerated. These can be determined by also DCD and DSR status bits subsequently will follow the input lines, although no interrupt will occur. Baud Rate - ClSt@l Frequency 5. Overrun cleared, if set Divisor Furthermore, itis possible to drive the CDP65C51/51A with an MISCELLANEOUS NOTES ON OPERATION off chip oscillator to achieve the same thing. In this case, XTLI 1. I Echo Mode is selected, ATS goes low (pin 6) must be the clock input and XTLO (pin 7) must be ano connect. 5-24

CDP65C51, CDP65C51A CDP65C51/51A OPERATION (Cont'd) Table II - Divisor Selection CONTROL DIVISOR SELECTED REGISTER FOR THE BAUD RATE GENERATED | BAUD RATE GENERATED BITS INTERNAL COUNTER WITH 1.8432 MHz WITH FREQUENCY (F) No Divisor Selected 1.8432 x 10 36,864 Ea = 59 5364 24,576 24576 = 75 7 1.8432 x 10° 16,768 ——E7e8~ «109.92 5768 1.8432 x 10° F = 134.58 1.8432 x 10° F 12,288 T7728 = 150 1.8432 x 10 F 6.144 aig —* 900 1.8432 x 10° F 3,072 a7 = 800 7.8432 x 10° F = 1200 1.8432 x 10° 1,024 ———7ya — = 1800 024 1.8432 x 10° F 1 0 1 0 768 = 2400 1.8432 x 10° F 1 0 1 1 $2 = 3600 ti 1,8432 x 10° F 1 1 0 «0 384 = 4800 ® a a 1 1,0 4 256 eG 7200 5 eg 1 1°40 = 9600 ef 1.8432 x 10° F 1 1 404 = 19200 DIAGNOSTIC LOOP-BACK OPERATING MODES A simplified block diagram for a system incorporating a CDP65C51/51A is shown in Fig. 20. processon Row Raw coNTHOL ron = Lew | TO DATA LN Fig. 20 - Simplitied system diagram. 5-25

CDP65C51, CDP65C51A CDP65C51/51A OPERATION (Cont'd) DIAGNOSTIC LOOP-BACK OPERATING MODES (Cont'd) Occasionally it may be desirable to include in the system a 3. Connects transmitter outputs to respective receiver facility for “loop-back” diagnostic testing, of which there inputs: are two kinds: 8) TxD to AxD 1. Local Loop-Back b) BTR to BED Loop-back from the point of view of the processor. In this ATS to GTS case, the Modem and Data Link must be effectively 6) RTS to CTS disconnected and the ACIA transmitter connected back LLB may be tied to a peripheral control pin to provide to its own receiver, so that the processor can perform processor control of local loop-back operation. In this way, diagnostic checks on the system, excluding the actual _the processor can easily perform local loop-back diagnostic data channel. testing. 2. Remote Loop-Back int of vi ; Remote loop-back does not require this circuitry, so LLB Loop-back from the point of view of the Data Link and Modem. inthis case, the processor, itsel,sdisconnected — foitgwings w HOWeNer: the Processor must select the andall received datais immediately retransmitted, so the system on the other end of the Data Link may operate _1. Control Register bit 4 must be 1", so that the transmitter independent of the local system. clock = receiver clock. The CDP85C51/51A does not contain automatic loop back 2. Command Register bit 4 must be “1” to select Echo operating modes, but they may be implemented with the Mode. addition of a small amount of external circuitry. 3. Command Register bits 3 and 2 must be “1” and "0", Fig. 21 indicates the necessary logic to be used with the respectively, to disable transmitter interrupts. CDP6SC51/51A. 4, Command Register bit 1 must be “0” to disable receiver The LLB line is the positive-true signal to enable local loop- interrupts. back operation. Essentially, LLB = high does the following: jn tnis way, the system retransmits received data without 1. Disables outputs TxD, DTA, and ATS (to Modem). any effect on the local system. 2. Disables inputs RxD, DCD, CTS, DSR (from Modem). copescer/e1a TA no nxo 060 TTS Dan sey concrsy *Y 18 ” SxD {| a zal Bee, a ee ee al ‘crs “oo “a ose. eM seu Ww uJ po a a Dre Pe] a on a cin Fee 6 nr a s2en- 36790 a ut — oom NOTES: 1. HIGH ON-LLB SELECTS LOCAL LOOP-BACK MODE. 2. Hilon on netsr SeLecT inpUT GATES" INPUTS To-v"ourPUTs: LOW GATES "x TO, Fig. 21 - Loop-back circuit schematic, 5-26

CDP65C51, CDP65C51A DYNAMIC ELECTRICAL CHARACTERISTICS—READ/WRITE CYCLE VoD = 5V + 5%, Ta = -40°C to +85°C, CL = 75pF [cyioting tee | tT = [los [= foes | - [os | [eerisewan te | mo | | mo | pm | - | | [pAvssustime we | veo | - | | - | | - [= | [pfveowtine tow fo | - | o | - | © | - | = | [oasausseuntine ——‘oow | veo | | | - [a [| - | m | [cswewroutine ww | 29 | - | | - | s | - | = | [reesnoutme wn | | - | | - | | - [| . Vie oe vie tac oan 3 ‘pe Mw y Write-timing waveforms Rw ‘™ Toa Read-timing waveforms sg 5-27

CDP65C51, CDP65C51A Vpp = 5V 5%, Ta = -40°C to +85°C. CDP65C51/S1A-1 ‘CDP65C51/51A-2 CDP65C51/S1A-4 [nisPapegionowey wy | | ewe ff we | fo | | (ty, ty = 10ns to 30ns) 1 * The baud rate with external clocking is: Baud Rate = ——— 16 x Tocy tev touy xTul few tee _ too Ro TRO Fig. 23 - Transmit timing waveforms with external clock. Fig. 24 - Interrupt and output timing waveforms. ‘cov’ 1.8432 MHz CS xTLO oh ir arco Yeu = NOTE: RxD RATE IS IMG Axe RATE INTERNAL CLOCK EXTERNAL CLOCK 92cs-36r78 92cs- hast Fig. 25 - Receive external clock timing waveforms. Fig. 26 - Transmitter clock generation. §-28