CDP6402 HARRIS | Alldatasheet

Document overview

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Technical content

Features

3.2MHz (Max Freq.) at VDD = 5V

  • Baud Rate
  • 4V to 10.5 Operation
  • Automatic Data Formatting and Status Generation
  • Fully Programmable with Externally Selectable Word Length (5 - 8 Bits), Parity Inhibit, Even/Odd Parity, and 1, 1-1/2, or 2 Stop Bits
  • Operating Temperature Range oC to +125oC
  • Replaces Industry Type IM6402 and Compatible with HD6402

Description

The CDP6402 and CDP6402C are silicon gate CMOS Universal Asynchronous Receiver/Transmitter (UART) circuits for interfacing computers or microprocessors to asynchronous serial data channels. They are designed to provide the necessary formatting and control for interfacing between serial and parallel data channels. The receiver converts serial start, data, parity, and stop bits to parallel data verifying proper code transmission, parity and stop bits. The transmitter converts parallel data into serial form and automatically adds start parity and stop bits. The data word can be 5, 6, 7 or 8 bits in length. Parity may be odd, even or inhibited. Stop bits can be 1, 1-1/2, or 2 (when transmitting 5-bit code). The CDP6402 and CDP6402C can be used in a wide range of applications including modems, printers, peripherals, video terminals, remote data acquisition systems, and serial data links for distributed processing systems. The CDP6402 and CDP6402C are functionally identical. They differ in that the CDP6402 has a recommended operating voltage range of 4V to 10.5V, and the CDP6402C has a recommended operating voltage range of 4V to 6.5V. Pinout (40 LEAD PDIP, SBDIP) TOP VIEW

Ordering Information

AGE TEMP. RANGE 5V/200K BAUD 10V/400K BAUD PKG. NO. PDIP -40 oC to +85oC CDP6402CE CDP6402E E40.6 Burn-In CDP6402CEX - SBDIP -40 oC to +85oC CDP6402CD CDP6402D D40.6 Burn-In CDP6402CDX CDP6402DX V DD NC GND RRD RBR8 RBR7 RBR6 RBR5 RBR4 RBR3 RBR2 RBR1 PE FE OE SFD RRC DRR DR RRI TRC EPE CLS1 CLS2 SBS PI CRL TBR8 TBR7 TBR6 TBR5 TBR4 TBR3 TBR2 TBR1 TRO TRE TBRL TBRE MR August 1996 CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © Harris Corporation 1996 CDP6402, CDP6402C CMOS Universal Asynchronous Receiver/Transmitter (UART) File Number 1328.2

FIGURE 1. FUNCTIONAL BLOCK DIAGRAM

Absolute Maximum Ratings Thermal Information DC Supply-Voltage Range, (VDD ) DD +0.5V Device Dissipation Per Output Transistor For TA = Full Package-Temperature Range Operating-Temperature Range (TA) Thermal Resistance (Typical, Note 1)θJA (oC/W) θJC (oC/W) Maximum Storage Temperature Range (T STG ) . . .-65oC to +150oC Maximum Lead Temperature (Soldering 10s): CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on an evaluation PC board in free air. Operating ConditionsAt TA = Full Package-Temperature Range. For maximum reliability, operating conditions should be selected so that operatIon is always within the following ranges: PARAMETER LIMITS UNITS CDP6402 CDP6402C MIN MAX MIN MAX DC Operating Voltage Range 4 10.5 4 6.5 V Input Voltage Range V SS VDD VSS VDD V Static Electrical Specificationsat TA = -40oC to +85oC, VDD ±10%, Except as noted PARAMETER CONDITIONS LIMITS UNITS VO (V) VIN (V) VDD (V) CDP6402 CDP6402C MIN (NOTE 1) TYP MAX MIN (NOTE 1) TYP MAX Quiescent Device Current IDD - 0, 5 5 - 0.01 50 - 0.02 200 µA - 0,10 10 - 1 200 - - - µA Output Low Drive (Sink) Current IOL 0.4 0,5 5 2 4 - 1.2 2.4 - mA 0.5 0,10 10 5 7 - - - - mA Output High Drive (Source) Current Output Voltage Low- Level (Note 2) VOL - 0, 5 5 - 0 0.1 - 0 0.1 V Output Voltage High Level (Note 2) VOH - 0, 5 5 4.9 5 - 4.9 5 - V Input Low Voltage V IL 0.5, 4.5 - 5 - - 0.8 - - 0.8 V DD -- - V CDP6402, CDP6402C

Input High Voltage V IH 0.5, 4.5 - 5 V DD -2 - - V DD -2 - - V Input Leakage Current IIN Any Input Three-State Output Leakage Current IOUT 0, 5 0, 5 5 - ±10-4 ±1- ±10-4 ±1 µA Operating Current (Note 2) IDD1 - 0, 5 5 - 1.5 − - 1.5 - mA Input Capacitance C IN - - - - 5 7.5 - 5 7.5 pF Output Capacitance C OUT - - - - 10 15 - 10 15 pF NOTES: 1. Typical values are for TA = 25oC and nominal VDD 2. IOL = IOH = 1µA. 3. Operating current is measured at 200kHz or VDD = 5V and 400kHz for VDD = 10V, with open outputs (worst-case frequencies for CDP1802A system operating at maximum speed of 3.2MHz). Static Electrical Specificationsat TA = -40oC to +85oC, VDD ±10%, Except as noted (Continued) PARAMETER CONDITIONS LIMITS UNITS VO (V) VIN (V) VDD (V) CDP6402 CDP6402C MIN (NOTE 1) TYP MAX MIN (NOTE 1) TYP MAX CDP6402, CDP6402C

and CHARACTER LENGTH SELECTS (CLS1 and CLS2). for receiver and/or transmitter operations. transmits it in serial form (Figure 2) on the TRO terminal. transferred to the transmitter register and TRE is cleared. TBRE is set to a logic High one cycle after that. data rate. Receiver timing is shown in Figure 4. at 9 clocks into the first stop bit. FIGURE 2. SERIAL DATA FORMAT

2 STOP BITSSTART

FIGURE 3. TRANSMITTER TIMING WAVEFORMS

1 TO 2 CYCLES

FIGURE 4. RECEIVER TIMING WAVEFORMS FIGURE 5. START BIT TIMING WAVEFORMS

TABLE 1. CONTROL WORD FUNCTION

TABLE 2. FUNCTION PIN DEFINITION

2 N/C No Connection

3 GND Ground (V

than 8 characters are right justified to RBR1.

6 RBR7

7 RBR6

8 RBR5

9 RBR4

10 RBR3

11 RBR2

12 RBR1

character’s stop bit is received. performed (i.e., DRR; active low).

16 SFD A high level on STATUS FLAGS DISABLE forces the outputs PE, FE, OE, DR, TBRE to a high impedance

17 RRC The RECEIVER REGISTER CLOCK is 16X the receiver data rate. DRR A low level on DATA RECEIVED RESET clears the data received output (DR), to a low level. 20 RRl Serial data on RECEIVER REGISTER INPUT is clocked into the receiver register. actually set on the first rising edge of TRC after MR goes high. MR should be strobed after power-up.

22 TBRE A high level on TRANSMITTER BUFFER REGISTER EMPTY indicates the transmitter buffer register has

transferred its data to the transmitter register and is ready for new data.

25 TRO Character data, start data and stop bits appear serially at the TRANSMITTER REGISTER OUTPUT. formats less than 8 bits, the TBR8, 7, and 6 Inputs are ignored corresponding to the programmed word length.

27 TBR2

28 TBR3

29 TBR4

30 TBR5

31 TBR6

32 TBR7

33 TBR8

34 CRL A high level on CONTROL REGISTER LOAD loads the control register. 35 PI † A high level on PARITY INHIBIT inhibits parity generation, parity checking and forces PE output low. low 6 bits) (CLS1 low CLS2 high 7 bits) (CLS1 high CLS2 high 8 bits).

38 CLSl † See Pin 37 - CLS2

40 TRC The TRANSMITTER REGISTER CLOCK is 16X the transmit data rate. TABLE 2. FUNCTION PIN DEFINITION (Continued)

  1. All measurements are made at the 50% point of the transition except three-state measurements.
  2. Maximum limits of minimum characteristics are the values above which all devices function.

FIGURE 6. SYSTEM TIMING WAVEFORMS

Dynamic Electrical Specificationsat TA = -40oC to +85oC, VDD ±5%, tR , tF = 20ns, VIH = 0.7 VDD , VIL = 0.3 VDD , CL = 100pF (NOTE 1) PARAMETER VDD (V) LIMITS UNITS CDP6402 CDP6402C (NOTE 2) TYP (NOTE 3) MAX (NOTE 2) TYP (NOTE 3) MAX TRANSMITTER TIMING (See Figure 7) Minimum Clock Period (TRC) t CC 5 250 310 250 310 ns 10 125 155 - - ns Minimum Pulse Width Clock Low Level t CL 5 100 125 100 125 ns 10 75 100 - - ns Clock High Level t CH 5 100 125 100 125 ns 10 75 100 - - ns TBRL t THTH 5 80 200 80 200 ns 10 40 100 - - ns Minimum Setup Time TBRL to Clock t THC 5 175 275 175 275 ns 10 90 150 - - ns Data toTBRL t DT 5 2 05 02 05 0n s 10 0 40 - - ns Minimum Hold-Time Data after TBRL t TD 5 4 06 04 06 0n s 10 20 30 - - ns Propagation Delay Time Clock to Data Start Bit t CD 5 300 450 300 450 ns 10 150 225 - - ns Clock to TBRE t CT 5 330 400 330 400 ns 10 100 150 - - ns TBRL to TBRE t TTHR 5 200 300 200 300 ns 10 100 150 - - ns Clock to TRE t TTS 5 330 400 330 400 ns 10 100 150 - - ns NOTES: 1. All measurements are made at the 50% point of the transition except three-state measurements. 2. Typical values for T A = 25oC and nominal VDD . 3. Maximum limits of minimum characteristics are the values above which all devices function. CDP6402, CDP6402C

Dynamic Electrical Specificationsat TA = -40oC to +85oC, VDD ±5%, tR , tF = 20ns, VIH = 0.7 VDD , VIL = 0.3 VDD , CL = 100pF (NOTE 1) PARAMETERS VDD (V) LIMITS UNITS CDP6402 CDP6402C (NOTE 2) TYP (NOTE 3) MAX (NOTE 2) TYP (NOTE 3) MAX RECEIVER TIMING (See Figure 8) Minimum Clock Period (RRC) t CC 5 250 310 250 310 ns 10 125 155 - - ns Minimum Pulse Width Clock Low Level t CL 5 100 125 100 125 ns 10 75 100 - - ns Clock High Level t CH 5 100 125 100 125 ns 10 75 100 - - ns Data Received Reset t DD 5 5 07 55 07 5n s 10 25 40 - - ns Minimum Setup Time Data Start Bit to Clock t DC 5 100 150 100 150 ns 10 50 75 - - ns Propagation Delay Time Data Received Reset to Data Received tDDA 5 150 250 150 250 ns 10 75 125 - - ns Clock to Data Valid t CDV 5 275 400 275 400 ns 10 110 175 - - ns Clock to DR t CDA 5 275 400 275 400 ns 10 110 175 - - ns Clock to Overrun Error t COE 5 275 400 275 400 ns 10 100 150 - - ns Clock to Parity Error t CPE 5 240 375 240 375 ns 10 120 17 - - ns Clock to Framing Error t CFE 5 200 300 200 300 ns 10 100 150 - - ns NOTES: 1. All measurements are made at the 50% point of the transition except three-state measurements. 2. Typical values for T A = 25oC and nominal VDD . 3. Maximum limits of minimum characteristics are the values above which all devices function. CDP6402, CDP6402C