CDK2000-CLK

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Technical content

Features

 Clock Multiplier / Jitter Reduction – Generates a Low Jitter 6 - 75 MHz Clock from a Jittery or Intermittent 50 Hz to 30 MHz Clock Source  Highly Accurate PLL Multiplication Factor – Maximum Error Less Than 1 PPM in High- Resolution Mode  One-Time Programmability – Configurable Hardware Control Pins – Configurable Auxiliary Output  Flexible Sourcing of Reference Clock – External Oscillator or Clock Source – Supports Inexpensive Local Crystal  Minimal Board Space Required – No External Analog Loop-filter Components General Description The CS2100-OTP is an extremely versatile system clocking device that utilizes a programmable phase lock loop. The CS2100-OTP is based on a hybrid analog- digital PLL architecture comprised of a unique combina- tion of a Delta-Sigma Fractional-N Frequency Synthesizer and a Digital PLL. This architecture allows for generation of a low-jitter clock relative to an external noisy synchronization clock with frequencies as low as 50 Hz. The CS2100-OTP ha s many configuration op- tions which are set once prior to runtime. At runtime there are three hardware configuration pins available for mode and feature selection. The CS2100-OTP is available in a 10-pin MSOP pack- age in Commercial (-10°C to +70°C) grade. Customer development kits are also available for custom device prototyping, small production programming, and device evaluation. Please see “Ordering Information” on page 26 for complete details. Hardware Configuration Auxiliary Output 6 to 75 MHz PLL Output Frequency Reference 3.3 V Hardware Control

8 MHz to 75 MHz

Digital PLL & Fractional N LogicOutput to Input Clock Ratio N Timing Reference PLL Output Lock Indicator

50 Hz to 30 MHz

AUG '09 DS841F1 CS2100-OTP

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1. PIN DESCRIPTION Pin Name # Pin Description VD 1 Digital Power (Input) - Positive power supply for the digital and analog sections. GND 2 Ground (Input) - Ground reference. CLK_OUT 3 PLL Clock Output (Output) - PLL clock output. AUX_OUT 4 Auxiliary Output (Output) - This pin outputs a buffered version of one of the input or output clocks, or a status signal, depending on configuration. CLK_IN 5 Frequency Reference Clock Input (Input) - Clock input for the Digital PLL frequency reference. XTO XTI/REF_CLK Crystal Connections (XTI/XTO) / Timing Reference Clock Input (REF_CLK) (Input/Output) - XTI/XTO are I/O pins for an external crystal which may be used to generate the low-jitter PLL input clock. REF_CLK is an input for an externally generated low-jitter reference clock. M2 8 Mode Select (Input) - M2 is a configurable mode selection pin. M1 9 Mode Select (Input) - M1 is a configurable mode selection pin. M0 10 Mode Select (Input) - M0 is a configurable mode selection pin. 5 6 XTO CLK_OUT GND VD XTI/REF_CLK AUX_OUT CLK_IN

1. TYPICAL CONN ECTION DIAGRAM

Figure 1. Typical Connection Diagram

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1. CHARACTERISTICS AN D SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS GND = 0 V; all voltages with respect to ground. (Note 1) Notes: 1. Device functionality is not guaranteed or implied outside of these limits. Operation outside of these limits may adversely affect device reliability. 2. CLK_IN must not be applied when these conditions are not met, including during power up. See section 5.9 on page 19 for required power up procedure. ABSOLUTE MAXIMUM RATINGS GND = 0 V; all voltages with respect to ground. WARNING: Operation at or beyond these limits may result in permanent damage to the device. Notes: 3. The maximum over/under voltage is limited by the input current except on the power supply pin. DC ELECTRICAL CHARACTERISTICS Test Conditions (unless otherwise specified): VD = 3.1 V to 3.5 V; TA = -10°C to +70°C (Commercial Grade). Notes: 4. To calculate the additional curr ent consumption due to loading (per output pin), multiply clock output frequency by load capacitance and power supply voltage. For example, fCLK_OUT (49.152 MHz) * C L (15 pF) * VD (3.3 V) = 2.4 mA of additional current due to these loading conditions on CLK_OUT. Parameters Symbol Min Typ Max Units DC Power Supply ( Note 2) VD 3.1 3.3 3.5 V Ambient Operating Temperature (Power Applied) Commercial Grade T AC -10 - +70 °C Parameters Symb ol Min Max Units DC Power Supply VD -0.3 6.0 V Input Current I IN -± 1 0 m A Digital Input Voltage (Note 3)V IN -0.3 VD + 0.4 V Ambient Operating Temperature (Power Applied) T A -55 125 °C Storage Temperature T stg -65 150 °C Parameters Symbol Min Typ Max Units Power Supply Current - Unloaded ( Note 4)I D -1 2 1 8 m A Power Dissipation - Unloaded ( Note 4)P D -4 0 6 0 m W Input Leakage Current I IN -- ± 1 0 µ A Input Capacitance I C -8-p F High-Level Input Voltage V IH 70% - - VD Low-Level Input Voltage V IL -- 3 0 % V D High-Level Output Voltage (IOH = -1.2 mA) V OH 80% - - VD Low-Level Output Voltage (IOH = 1.2 mA) V OL -- 2 0 % V D

AC ELECTRICAL CHARACTERISTICS Test Conditions (unless otherwise specified): VD = 3.1 V to 3.5 V; TA = -10°C to +70°C (Commercial Grade); CL =1 5p F . Notes: 5. 1 UI (unit interval) corresponds to t SYS_CLK or 1/fSYS_CLK. 6. fCLK_OUT = 24.576 MHz; Sample size = 10,000 points; AuxOutSrc[1:0] =1 1 . 7. In accordance with AES-12id-2006 section 3.4.2. Measurements are Time Interval Error taken with 3rd order 100 Hz to 40 kHz bandpass filter. 8. In accordance with AES-12id-2006 section 3.4.1. Measurements are Time Interval Error taken with 3rd order 100 Hz Highpass filter. 9. 1 UI (unit interval) corresponds to t CLK_IN or 1/fCLK_IN. 10. The frequency accuracy of the PLL clock output is directly proportional to the frequency accuracy of the reference clock. Parameters Symbol Conditions Min Typ Max Units Crystal Frequency Fundamental Mode XTAL fXTAL RefClkDiv[1:0] = 10 RefClkDiv[1:0] = 01 RefClkDiv[1:0] = 00 18.75 37.5 MHz MHz MHz Reference Clock Input Frequency f REF_CLK RefClkDiv[1:0] = 10 RefClkDiv[1:0] = 01 RefClkDiv[1:0] = 00 18.75 37.5 MHz MHz MHz Reference Clock Input Duty Cycle D REF_CLK 45 - 55 % Internal System Clock Frequency f SYS_CLK 8 18.75 MHz Clock Input Frequency f CLK_IN 50 Hz - 30 MHz Clock Input Pulse Width (Note 5)p w CLK_IN fCLK_IN < fSYS_CLK/96 fCLK_IN > fSYS_CLK/96 UI ns PLL Clock Output Frequency f CLK_OUT 6- 7 5 M H z PLL Clock Output Duty Cycle t OD Measured at VD/2 45 50 55 % Clock Output Rise Time t OR 20% to 80% of VD - 1.7 3.0 ns Clock Output Fall Time t OF 80% to 20% of VD - 1.7 3.0 ns Period Jitter t JIT (Note 6) - 70 - ps rms Base Band Jitter (100 Hz to 40 kHz) (Notes 6, 7) - 50 - ps rms Wide Band JItter (100 Hz Corner) (Notes 6, 8) - 175 - ps rms PLL Lock Time - CLK_IN (Note 9)t LC fCLK_IN < 200 kHz fCLK_IN > 200 kHz 100 200 UI ms PLL Lock Time - REF_CLK t LR fREF_CLK = 8 to 75 MHz - 1 3 ms Output Frequency Synthesis Resolution (Note 10)f err High Resolution High Multiplication ±0.5 ±112 ppm ppm

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1 Hz Bandwidth

128 Hz Bandwidth

Figure 2. CLK_IN Sinusoidal Jitter Tolerance Figure 3. CLK_IN Sinusoidal Jitter Transfer Samples size = 2.5M points; Base Band Jitter (10Hz to 40kHz). Samples size = 2.5M points; Base Band Jitter (10Hz to 40kHz). Figure 4. CLK_IN Random Jitter Rejection and Tolerance

4.1 Delta-Sigma Fractional- N Frequency Synthesizer

clock ratio is the value of N that is applied to the delta-sigma modulator (see Figure 5). clock should be stable and jitter-free. Figure 5. Delta-Sigma Fractional-N Frequency Synthesizer

4.2 Hybrid Analog-Digital Phase Locked Loop

achieve lock and then reduced for optimal jitter rejection.

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Figure 6. Hybrid Analog-Digital PLL

5.1 One Time Programmability

Please see “Programming Information” on page 24 for more details. Table 1. Modal and Global Configuration

5.2 Timing Reference Clock Input

directly affects the performance of the PLL and hence the quality of the PLL output.

5.2.1 Internal Timing Reference Clock Divider

acteristics” on page 7 for more details. where N is an integer. Figure 8 shows the effect of varying the RefClk frequency around f CLK_OUT*N/32. Global Configuration settings set once for all modes. Figure 7. Internal Timing Reference Clock Divider

50 MHz (XTI)

75 MHz (REF_CLK)

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5.2.2 Crystal Connections (XTI and XTO)

to the “AC Electrical Characteristics” on page 7 for the allowed crystal frequency range.

5.2.3 External Reference Clock (REF_CLK)

5.3 Frequency Reference Clock Input, CLK_IN

Figure 8. REF_CLK Frequency vs a Fixed CLK_OUT

11.919 MHz=

12.288 MHz 11 5 kHz+×=

12.273 MHz=

Figure 9. External Component Requirements for Crystal Circuit

PLL. The allowable frequency range for CLK_IN is found in the “AC Electrical Characteristics” on page 7.

5.3.1 Adjusting the Minimum Loop Bandwidth for CLK_IN

der to pass through the PLL without attenuation. the lowest PLL bandwidth setting. See Figure 10. those synchronous to the PLL_OUT domain. Figure 10. Low bandwidth and new clock domain Figure 11. High bandwidth with CLK_IN domain re-use

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While acquiring lock, the digital lo op bandwidth is automatically se t to a large valu e. Once lock is achieved, the digital loop bandwidth will settl e to the minimum valu e selected by the ClkIn_BW[2:0] pa- rameter.

5.4 Output to Input Freque ncy Ratio Configuration

5.4.1 User Defined Ratio (R UD)

The User Defined Ratio, RUD, is a 32-bit un-signed fixed-point number which determines the basis for the desired input to output clock ratio. Up to four different ratios, Ratio0-3, can be stored in the CS2100’s one time programmable memory. Selection between the four ratios is achieved by the M[1:0] mode select pins. The 32-bit R UD can be expressed in either a high resolu tion (12.20) or high multiplication (20.12) format selectable by the LFRatioCfg global parameter. The RUD for high resolution (12.20) format is encoded with 12 MSBs representing the integer binary por- tion with the remaining 20 LSBs representing the frac tional binary portion. The maximum multiplication factor is approximately 4096 with a resolution of 0.954 PPM in this configuration. See “Calculating the User Defined Ratio” on page 23 for more information. The RUD for high multiplication (20.12) format is encod ed with 20 MSBs representing the integer binary portion with the remaining 12 LSBs representing the frac tional binary portion. In this configuration, the maximum multiplication factor is approximately 1,048,575 with a resolution of 244 PPM. It is recommend- ed that the 12.20 High-Reso lution format be utilized whenever the desired ratio is less than 4096 since the output frequency accuracy of the PLL is directly proportional to the accuracy of the timing reference clock and the resolution of the RUD. The status of internal dividers, such as the internal timing reference clock divider, are automatically taken into account. Therefore RUD is simply the desired ratio of the output to input clock frequencies. Referenced Control Parameter Definition Referenced Control Parameter Definition

5.4.2 Ratio Modifier (R-Mod)

global parameter (see Section 5.7.2 on page 18). Table 2. Ratio Modifier

5.4.3 Effective Ratio (R EFF)

to be altered to account for internal dividers. input and output clocks as shown in the “AC Electrical Characteristics” on page 7. Selection of the user defined ratio from the four stored ratios is made by using the M[1:0] pins.

5.4.4 Ratio Configuration Summary

modal configuration set. The resolution/format for the R UD is selectable. R-Mod is applied accordingly.

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er. The subscript ‘4’ indicates the modal parameters. Figure 12. Ratio Feature Summary

5.5 PLL Clock Output

The PLL clock output pin (CLK_OUT) provides a buffered version of the output of the frequency synthesizer. parameter, however the state CLK_OUT may then be unreliable during an unlock condition. Figure 13. PLL Clock Output Options

5.6 Auxiliary Output

M2 pin when the M2Config[1:0] global parameter is set to either 001 or 010. Figure 14. Auxiliary Output Selection

5.7 Mode Pin Functionality

5.7.1 M1 and M0 Mode Pin Functionality

configuration. Figure 16 on page 20 provides a summary of all parameters used by the device.

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5.7.2 M2 Mode Pin Functionality

Figure 15. M2 Mapping Options

5.7.2.1 M2 Configured as Output Disable

‘high’, the corresponding output(s) will be disabled.

5.7.2.2 M2 Configured as R-Mod Enable

R-Mod will be disabled, if M2 is driven ‘high’ R-Mod will be enabled.

5.7.2.3 M2 Configured as AuxOutSrc Override

will function according to AuxOutSrc[1:0].

5.8 Clock Output Stability Considerations

5.8.1 Output Switching

The CS2100-OTP is designed such that re-configuratio n of the clock routing func tions do not result in a partial clock period on any of the active outputs (CLK_OUT and/or AUX_OUT). In particular, enabling or disabling an output, changing the auxiliary output source between REF_CLK and CLK_OUT, and the au- tomatic disabling of the output(s) during unlock will not cause a runt or partial clock period. The following exceptions/limitations exist:

• Enabling/disabling AUX_OUT when AuxOutSrc[1:0] = 11 (unlock indicator).
• Switching AuxOutSrc[1:0] to or from 01 (CLK_IN) and to or from 11 (unlock indicator) (Transitions between AuxOutSrc[1:0] = [00,10] will not produce a glitch). When any of these exceptions occur, a partial clock period on the output may result.

5.8.2 PLL Unlock Conditions

Certain changes to the clock inputs and mode pins can cause the PLL to lose lock which will affect the presence of a clock signal on CLK_OUT. The following outlines which conditions cause the PLL to go un- locked:

• Any change in the state of the M1 and M0 pins will cause the PLL to temporarily lose lock as the new setting takes affect.
• Changes made to the state of the M2 when the M2Config[2:0] global parameter is set to 011, 100, 101, or 110 can cause the PLL to temporarily lose lock as the new setting takes affect.
• Any discontinuities on the Ti ming Reference Clock, REF_CLK.
• Discontinuities on the Frequency Reference Clock, CLK_IN.
• Gradual changes in CLK_IN frequency great er than ±30% from the starting frequency.
• Step changes in CLK_IN frequency.

5.9 Required Power Up Seque ncing for Programmed Devices

• Apply power. All input pins, except XTI/REF_CLK, should be held in a static logic hi or lo state until the ‘DC Power Supply’ specification in the “Recommended Operating Conditions” table on page 6 are met.
• Apply input clock(s) if required.
• For CDK programmed devices, toggle the state of the M0, M1, or both pins at least 3 times to initialize the device. This must be done after the power supply is stable and before normal operation is expected. Note: This operation is not required for factory programmed devices.
• After the specified PLL lock time on page 7 has passed, the device will output the desired clock as con- figured by the M0-M2 pins.

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programmed at the factory. Please see “Programming Information” on page 24 for more details. Figure 16. Parameter Configuration Sets

6.1 Modal Configuration Sets

is made using the M[1:0] pins.

6.1.1 R-Mod Selection (RModSel[1:0])

Selects the R-Mod value, which is used as a factor in determining the PLL’s Fractional N. 00 Right-shift R-value by 1 (÷ 2). 01 Right-shift R-value by 2 (÷ 4). 10 Right-shift R-value by 3 (÷ 8). 11 Right-shift R-value by 4 (÷ 16).

6.1.2 Auxiliary Output Sour ce Selection (AuxOutSrc[1:0])

Selects the source of the AUX_OUT signal. Note: When set to 11, the AuxLockCfg global parameter sets the polarity and driver type ( “AUX PLL Lock Output Configuration (AuxLockCfg)” on page 21).

6.2 Ratio 0 - 3

The four 32-bit User Defined Ratios are stored in the CS2100’s one time programmable memory. See “Out- put to Input Frequency Ratio Configuration” on page 14 and “Calculating the User Defined Ratio” on page 23 for more details.

6.3 Global Configuration Parameters

6.3.1 AUX PLL Lock Output Configuration (AuxLockCfg)

When the AUX_OUT pin is configured as a lock indicator ( AuxOutSrc[1:0] modal parameter = ‘11’), this global parameter configures the AUX_OUT driver to either push-pull or open drain. It also determines the polarity of the lock signal. If AUX_OUT is configured as a clock output, the state of this parameter is dis- regarded. Note: AUX_OUT is an unlock indicator, signalling an error condition when the PLL is unlocked. There- fore, the pin polarity is defined relative to the unlock condition.

6.3.2 Reference Clock Input Divider (RefClkDiv[1:0])

Selects the input divider for the timing reference clock. AuxOutSrc[1:0] Auxiliary Output Source 00 RefClk. 01 CLK_IN. 10 CLK_OUT. 11 PLL Lock Status Indicator. Application: “Auxiliary Output” on page 17 AuxLockCfg AUX_OUT Driver Configuration 0 Push-Pull, Active High (output ‘high’ for unlocked condition, ‘low’ for locked condition). 1 Open Drain, Active Low (output ‘low’ for unl ocked condition, high-Z for locked condition). Application: “Auxiliary Output” on page 17 RefClkDiv[1:0] Reference Clock Input Divider REF_CLK Frequency Range 00 ÷ 4. 32 MHz to 75 MHz (50 MHz with XTI) 01 ÷ 2. 16 MHz to 37.5 MHz 10 ÷ 1. 8 MHz to 18.75 MHz 11 Reserved. Application: “Internal Timing Reference Clock Divider” on page 11

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6.3.3 Enable PLL Clock Out put on Unlock (ClkOutUnl)

Defines the state of the PLL output during the PLL unlock condition.

6.3.4 Low-Frequency Ratio Configuration (LFRatioCfg)

Determines how to interpret the currently indexed 32-bit User Defined Ratio .

6.3.5 M2 Pin Configur ation (M2Config[2:0])

Controls which special function is mapped to the M2 pin.

6.3.6 Clock Input Bandwidth (ClkIn_BW[2:0])

Sets the minimum loop bandwidth when locked to CLK_IN. ClkOutUnl Clock Output Enable Status 0 Clock outputs are driven ‘low’ when PLL is unlocked. 1 Clock outputs are always enabled (results in unpredictable output when PLL is unlocked). Application: “PLL Clock Output” on page 16 LFRatioCfg Ratio Bit Encoding Interpretation 0 20.12 - High Multiplier. 1 12.20 - High Accuracy. Application: “User Defined Ratio (RUD)” on page 14 M2Config[2:0] M2 pin function 000 Disable CLK_OUT pin. 001 Disable AUX_OUT pin. 010 Disable CLK_OUT and AUX_OUT. 011 RModSel[1:0] Modal Parameter Enable. 100 Reserved. 101 Reserved. 110 Reserved. 111 Force AuxOutSrc[1:0] = 10 (PLL Clock Out). Application: “M2 Mode Pin Functionality” on page 18 ClkIn_BW[2:0] Minimum Loop Bandwidth 000 1 Hz 001 2 Hz 010 4 Hz 011 8 Hz 100 16 Hz 101 32 Hz 110 64 Hz 111 128 Hz Application: “Adjusting the Minimum Loop Bandwidth for CLK_IN” on page 13

1. CALCULATING THE US ER DEFINED RATIO

ming Information” on page 24 for more details on programming. write to the register. A few examples have been provided in Table 3. Table 3. Example 12.20 R-Values write to the register. A few examples have been provided in Table 4. Table 4. Example 20.12 R-Values

12.288 MHz/60 Hz=204,800 838860800 32 00 00 00

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1. PROGRAMMING INFORMATION Field programming of the CS2100-OTP is achieved using the hardware and software tools included with the CDK2000. The software tools can be downloaded from www.cirrus.com for evaluation prior to ordering a CDK. The CDK2000 is designed with built-in features to ease the process of programming small quantities of devices for pro- totype and small production builds. In addition to its field programming capabilities, the CDK2000 can also be used for the complete evaluation of programmed CS2100-OTP devices. The CS2100-OTP can also be factory programmed for la rge quantity orders. When ordering factory programmed devices, the CDK should first be used to program and evaluate the desired configuration. When evaluation is com- plete, the CS2000 Configuration Wizard is used to genera te a file containing all device configuration information; this file is conveyed to Cirrus Logic as a complete sp ecification for the factory prog ramming configuration. Please contact your local Cirrus Logic sales representative for more information regarding factory programmed parts. See the CDK2000 datasheet, available at www.cirrus.com, for detailed information on the use of the CDK2000 pro- gramming and evaluation tools. Below is a form which represents the information required for programming a device (noted in gray). The “Parameter Descriptions” section beginning on page 20 describes the functions of each parameter. This form may be used ei- ther for personal notation for device configuration or it can be filled out and given to a Cirrus representative in con- junction with the programming file from the CDK2000 as an additional check. The User Defined Ratio may be filled out in decimal or it may be entered as hex as outlined in “Calculating the User Defined Ratio” on page 23. For all other parameters mark a ‘0’ or ‘1’ below the parameter name. OTP Modal and Global Configuration Parameters Form Modal Configuration Set #0 Ratio 0 (dec) RModSel1 RModSel0 AuxOutSrc1 AuxOutSrc0 Modal Configuration Set #1 Ratio 1 (dec) RModSel1 RModSel0 AuxOutSrc1 AuxOutSrc0 Modal Configuration Set #2 Ratio 2 (dec) RModSel1 RModSel0 AuxOutSrc1 AuxOutSrc0 Modal Configuration Set #3 Ratio 3 (dec) RModSel1 RModSel0 AuxOutSrc1 AuxOutSrc0 Global Configuration Set AuxLockCfg RefClkDiv1 RefClkDiv0 ClkOut Unl LFRatioCfg M2Cfg2 M2Cfg1 M2Cfg0 ClkIn_BW2 ClkIn_BW1 ClkIn_BW0

1. PACKAGE DIMENSIONS Notes: 1. Reference document: JEDEC MO-187 2. D does not include mold flash or prot rusions which is 0.15 mm max. per side. 3. E1 does not include inter-lead flash or protrusions which is 0.15 mm max per side. 4. Dimension b does not include a total allo wable dambar protrusion of 0.08 mm max. 5. Exceptions to JEDEC dimension. THERMAL CHARACTERISTICS INCHES MILLIMETERS NOTE DIM MIN NOM MAX MIN NOM MAX A1 0 -- 0.0059 0 -- 0.15 A2 0.0295 -- 0.0374 0.75 -- 0.95 b 0.0059 -- 0.0118 0.15 -- 0.30 4, 5 Parameter Symbol Min Typ Max Units Junction to Ambient Thermal Impedance JEDEC 2-Layer JEDEC 4-Layer θJA θJA 170 100 °C/W °C/W 10L MSOP (3 mm BODY) PACKAGE DRAWING (Note 1) E N 1 23 e b A1 A2 A D SEATING PLANE E11 L SIDE VIEW END VIEW TOP VIEW c

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10.ORDERING INFORMATION The CS2100-OTP is ordered as an un-programmed device. The CS2100-OTP can also be factory programmed for large quantity orders. Please see “Programming Information” on page 24 for more details. 11.REVISION HISTORY Product Description Package Pb-Free Grade Temp Range Container Order# CS2100-OTP Clocking Device 10L-MSOP Yes Commercial -10° to +70°C Rail CS2100P-CZZ CS2100-OTP Clocking Device 10L-MSOP Yes -10° to +70°C Tape and Reel CS2100P-CZZR CDK2000 Evaluation Platform - Yes - - - CDK2000-CLK Release Changes F1 Updated Period Jitter specification in “AC Electrical Characteristics” on page 7. Updated Crystal and Ref Clock Frequency specifications in “AC Electrical Characteristics” on page 7. Added “PLL Performance Plots” section on page 8. Updated “Internal Timing Reference Clock Divider” on page 11 and added Figure 8 on page 12. Removed CLK_IN Skipping Mode. Removed Auto R-Mod. Added Mode pin toggle requirement to startup for CDK programmed devices to “Required Power Up Sequencing for Programmed Devices” on page 19. Contacting Cirrus Logic Support For all product questions and inquiries, contact a Cirrus Logic Sales Representative. To find one nearest you, go to www.cirrus.com. IMPORTANT NOTICE Cirrus Logic, Inc. and its subsidiaries (“Cirrus”) believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives con- sent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROP- ERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRIT- ICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK AND CIR- RUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOM- ER’S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING AT- TORNEYS’ FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners.