CDK2000

DATASHEET SEARCH SITE | WWW.ALLDATASHEET.COM

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 36

Technical content

Features

 Delta-Sigma Fractional-N Frequency Synthesis – Generates a Low Jitter 6 - 75 MHz Clock from an 8 - 75 MHz Reference Clock  Clock Multiplier / Jitter Reduction – Generates a Low Jitter 6 - 75 MHz Clock from a Jittery or Intermittent 50 Hz to

30 MHz Clock Source

 Highly Accurate PLL Multiplication Factor – Maximum Error Less Than 1 PPM in High- Resolution Mode  I²C™ / SPI™ Control Port  Configurable Auxiliary Output  Flexible Sourcing of Reference Clock – External Oscillator or Clock Source – Supports Inexpensive Local Crystal  Minimal Board Space Required – No External Analog Loop-filter Components General Description The CS2000-CP is an extremely versatile system clocking device that utilizes a programmable phase lock loop. The CS2000-CP is based on a hybrid ana- log-digital PLL architecture comprised of a unique combination of a Delta-Sigma Fractional-N Frequency Synthesizer and a Digital PLL. This architecture allows for both frequency synthesis/clock generation from a stable reference clock as well as generation of a low- jitter clock relative to an external noisy synchronization clock. The design is also unique in that it can generate low-jitter clocks relative to noisy external synchroniza- tion clocks at frequencies as low as 50 Hz. The CS2000-CP supports both I²C and SPI for full software control. The CS2000-CP is available in a 10-pin MSOP pack- age in Commercial (-10°C to +70°C) grade. Customer development kits are also available for device evalua- tion. Please see “Ordering Information” on page 36 for complete details. I²C / SPI Auxiliary Output 6 to 75 MHz PLL Output 3.3 V I²C/SPI Software Control

8 MHz to 75 MHz

Digital PLL & Fractional N Logic Output to Input Clock Ratio N Timing Reference PLL Output Lock Indicator

50 Hz to 30 MHz

AUG '09 DS761F1 CS2000-CP

2 DS761F1

4 DS761F1

1. PIN DESCRIPTION Pin Name # Pin Description VD 1 Digital Power (Input) - Positive power supply for the digital and analog sections. GND 2 Ground (Input) - Ground reference. CLK_OUT 3 PLL Clock Output (Output) - PLL clock output. AUX_OUT 4 Auxiliary Output (Output) - This pin outputs a buffered version of one of the input or output clocks, or a status signal, depending on register configuration. CLK_IN 5 Frequency Reference Clock Input (Input) - Clock input for the Digital PLL frequency reference. XTO XTI/REF_CLK Crystal Connections (XTI/XTO) / Timing Reference Clock Input (REF_CLK) (Input/Output) - XTI/XTO are I/O pins for an external crystal which may be used to generate the low-jitter PLL input clock. REF_CLK is an input for an externally generated low-jitter reference clock. AD0/CS 8 Address Bit 0 (I²C) / Control Port Chip Select (SPI) (Input) - AD0 is a chip address pin in I²C Mode. CS is the chip select signal in SPI Mode. SCL/CCLK 9 Control Port Clock (Input) - SCL/CCLK is the serial clock for the serial control port in I²C and SPI mode. SDA/CDIN 10 Serial Control Data (Input/Output) - SDA is the data I/O line in I²C Mode. CDIN is the input data line for the control port interface in SPI Mode. 5 6 XTO CLK_OUT GND VD XTI/REF_CLK AD0/CS SCL/CCLK SDA/CDIN AUX_OUT CLK_IN

6 DS761F1

1. TYPICAL CONNEC TION DIAGRAM

Figure 1. Typical Connection Diagram

1. CHARACTERISTICS AN D SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS GND = 0 V; all voltages with respect to ground. (Note 1) Notes: 1. Device functionality is not guaranteed or implied outside of these limits. Operation outside of these limits may adversely affect device reliability. ABSOLUTE MAXIMUM RATINGS GND = 0 V; all voltages with respect to ground. WARNING: Operation at or beyond these limits may result in permanent damage to the device. Notes: 2. The maximum over/under voltage is limited by the input current except on the power supply pin. DC ELECTRICAL CHARACTERISTICS Test Conditions (unless otherwise specified): VD = 3.1 V to 3.5 V; TA = -10°C to +70°C (Commercial Grade). Notes: 3. To calculate the additional curr ent consumption due to loading (per output pin), multiply clock output frequency by load capacitance and power supply voltage. For example, fCLK_OUT (49.152 MHz) * C L (15 pF) * VD (3.3 V) = 2.4 mA of additional current due to these loading conditions on CLK_OUT. Parameters Symbol Min Typ Max Units DC Power Supply VD 3.1 3.3 3.5 V Ambient Operating Temperature (Power Applied) Commercial Grade T AC -10 - +70 °C Parameters Symb ol Min Max Units DC Power Supply VD -0.3 6.0 V Input Current I IN -± 1 0 m A Digital Input Voltage (Note 2)V IN -0.3 VD + 0.4 V Ambient Operating Temperature (Power Applied) T A -55 125 °C Storage Temperature T stg -65 150 °C Parameters Symbol Min Typ Max Units Power Supply Current - Unloaded ( Note 3)I D -1 2 1 8 m A Power Dissipation - Unloaded ( Note 3)P D -4 0 6 0 m W Input Leakage Current I IN -- ± 1 0 µ A Input Capacitance I C -8-p F High-Level Input Voltage V IH 70% - - VD Low-Level Input Voltage V IL -- 3 0 % V D High-Level Output Voltage (IOH = -1.2 mA) V OH 80% - - VD Low-Level Output Voltage (IOH = 1.2 mA) V OL -- 2 0 % V D

8 DS761F1

AC ELECTRICAL CHARACTERISTICS Test Conditions (unless otherwise specified): VD = 3.1 V to 3.5 V; TA = -10°C to +70°C (Commercial Grade); CL =1 5p F . Notes: 4. 1 UI (unit interval) corresponds to t SYS_CLK or 1/fSYS_CLK. 5. t CS represents the time from the removal of CLK_IN by which CLK_IN must be re-applied to ensure that PLL_OUT continues while the PLL re-acquires lock. This timeout is based on the internal VCO frequen- cy, with the minimum timeout occurring at the maximum VCO frequency. Lower VCO frequencies will result in larger values of tCS. 6. Only valid in cloc k skipping mode; See “CLK_IN Skipping Mode” on page 15 for more information. 7. fCLK_OUT = 24.576 MHz; Sample size = 10,000 points; AuxOutSrc[1:0] =1 1 . 8. In accordance with AES-12id-2006 section 3.4.2. Measurements are Time Interval Error taken with 3rd order 100 Hz to 40 kHz bandpass filter. 9. In accordance with AES-12id-2006 section 3.4.1. Measurements are Time Interval Error taken with 3rd order 100 Hz Highpass filter. 10. 1 UI (unit interval) corresponds to t CLK_IN or 1/fCLK_IN. 11. The frequency accuracy of the PLL clock output is directly proportional to the frequency accuracy of the reference clock. Parameters Symbol Conditions Min Typ Max Units Crystal Frequency Fundamental Mode XTAL fXTAL RefClkDiv[1:0] = 10 RefClkDiv[1:0] = 01 RefClkDiv[1:0] = 00 MHz MHz MHz Reference Clock Input Frequency f REF_CLK RefClkDiv[1:0] = 10 RefClkDiv[1:0] = 01 RefClkDiv[1:0] = 00 MHz MHz MHz Reference Clock Input Duty Cycle D REF_CLK 45 - 55 % Internal System Clock Frequency f SYS_CLK 81 4 M H z Clock Input Frequency f CLK_IN 50 Hz - 30 MHz Clock Input Pulse Width (Note 4)p w CLK_IN fCLK_IN < fSYS_CLK/96 fCLK_IN > fSYS_CLK/96 UI ns Clock Skipping Timeout t CS (Notes 5, 6)2 0 - - m s Clock Skipping Input Frequency f CLK_SKIP (Note 6) 50 Hz - 80 kHz PLL Clock Output Frequency f CLK_OUT 6- 7 5 M H z PLL Clock Output Duty Cycle t OD Measured at VD/2 45 50 55 % Clock Output Rise Time t OR 20% to 80% of VD - 1.7 3.0 ns Clock Output Fall Time t OF 80% to 20% of VD - 1.7 3.0 ns Period Jitter t JIT (Note 7) - 70 - ps rms Base Band Jitter (100 Hz to 40 kHz) (Notes 7, 8) - 50 - ps rms Wide Band JItter (100 Hz Corner) (Notes 7, 9) - 175 - ps rms PLL Lock Time - CLK_IN (Note 10)t LC fCLK_IN < 200 kHz fCLK_IN > 200 kHz 100 200 UI ms PLL Lock Time - REF_CLK t LR fREF_CLK = 8 to 75 MHz - 1 3 ms Output Frequency Synthesis Resolution (Note 11)f err High Resolution High Multiplication ±0.5 ±112 ppm ppm

1 Hz Bandwidth

128 Hz Bandwidth

Figure 2. CLK_IN Sinusoidal Jitter Tolerance Figure 3. CLK_IN Sinusoidal Jitter Transfer Samples size = 2.5M points; Base Band Jitter (10Hz to 40kHz). Samples size = 2.5M points; Base Band Jitter (10Hz to 40kHz). Figure 4. CLK_IN Random Jitter Rejection and Tolerance

10 DS761F1

Inputs: Logic 0 = GND; Logic 1 = VD; CL =2 0p F . Notes: 12. Data must be held for sufficient ti me to bridge the transition time, tf, of SCL. Figure 5. Control Port Timing - I²C Format

Inputs: Logic 0 = GND; Logic 1 = VD; CL =2 0p F . Notes: 13. tspi is only needed before first falling edge of CS after power is applied. tspi = 0 at all other times.

1. Data must be held for sufficient time to bridge the transition time of CCLK.

Figure 6. Control Port Timing - SPI Format (Write Only)

12 DS761F1

4.1 Delta-Sigma Fractional- N Frequency Synthesizer

clock ratio is the value of N that is applied to the delta-sigma modulator (see Figure 7). clock should be stable and jitter-free. Figure 7. Delta-Sigma Fractional-N Frequency Synthesizer

4.2 Hybrid Analog-Digital Phase Locked Loop

to quickly achieve lock and then reduced for optimal jitter rejection.

Figure 8. Hybrid Analog-Digital PLL

4.2.1 Fractional-N Source Selecti on for the Frequency Synthesizer

based on the presence of the Frequency Reference Clock or manually through register controls. Figure 9. Fractional-N Source Selection Overview

14 DS761F1

5.1 Timing Reference Clock Input

directly affects the performance of the PLL and hence the quality of the PLL output.

5.1.1 Internal Timing Reference Clock Divider

within the valid range as indicated in “AC Electrical Characteristics” on page 8. acteristics” on page 8 for more details. where N is an integer. Figure 11 shows the effect of varying the RefClk frequency around fCLK_OUT*N/32. Figure 10. Internal Timing Reference Clock Divider

8 MHz < SysClk < 14 MHz 8 MHz < RefClk <

50 MHz (XTI)

58 MHz (REF_CLK)

Figure 11. REF_CLK Frequency vs a Fixed CLK_OUT

11.919 MHz=

12.288 MHz 11 5 kHz+×=

12.273 MHz=

5.1.2 Crystal Connections (XTI and XTO)

to the “AC Electrical Characteristics” on page 8 for the allowed crystal frequency range.

5.1.3 External Reference Clock (REF_CLK)

5.2 Frequency Reference Clock Input, CLK_IN

5.2.1 CLK_IN Skipping Mode

within 20 ms of being removed. The ClkSkipEn bit enables this function. Figure 12. External Component Requirements for Crystal Circuit

16 DS761F1

without an indication of an unlock condition. Figure 13. CLK_IN removed for > 223 SysClk cycles

223 SysClk cycles 223 SysClk cycles

223 SysClk cycles

Figure 14. CLK_IN removed for < 223 SysClk cycles but > tCS

throughout the missing CLK_IN period including the time while the PLL re-acquires lock.

5.2.2 Adjusting the Minimum Loop Bandwidth for CLK_IN

Figure 15. CLK_IN removed for < tCS

18 DS761F1

the lowest PLL bandwidth setting. See Figure 16. those synchronous to the PLL_OUT domain. the minimum value selected by the ClkIn_BW[2:0] bits. Figure 16. Low bandwidth and new clock domain Figure 17. High bandwidth with CLK_IN domain re-use

5.3 Output to Input Freque ncy Ratio Configuration

5.3.1 User Defined Ratio (R UD), Frequency Synthesizer Mode

The User Defined Ratio, RUD, is a 32-bit un-signed fixed-point number which determines the basis for the desired input to output clock ratio. Up to four different ratios, Ratio0-3, can be stored in the CS2000 register space. The ratio pointed to by the RSel[1:0] bits is the currently selected ratio for the static ratio based Frequency Synthesizer Mode. The 32-bit RUD is represented in a high-resolution 12.20 format where the

12 MSBs represent the integer binary portion while the remaining 20 LSBs represent the fractional binary

portion. The maximum multiplication factor is approximately 4096 with a resolution of 0.954 PPM in this configuration. See “Calculating the User Defined Ratio” on page 34 for more information. The status of internal dividers, such as the internal timing reference clock divider, are automatically taken into account. Therefore R UD is simply the desired ratio of the output to input clock frequencies.

5.3.2 User Defined Ratio (R UD), Hybrid PLL Mode

The same four ratio locations, Ratio0-3, are used to store the User Defi ned Ratios for Hybrid PLL Mode. The User Defined Ratio pointed to by the LockClk[1:0] bits is the currently selected ratio for the dynamic ratio based Hybrid PLL Mode. In addition to the High-Resolution format, a High-Multiplication format is also available. In the High-Multi- plication Format Mode, the 32-bit RUD is represented in a 20.12 format where the 20 MSBs represent the integer binary portion while the remaining 12 LSBs repr esent the fractional binary portion. In this config- uration, the maximum multiplication factor is approximately 1,048,575 with a resolution of 244 PPM. The ratio format default is 20.12. The 20.12 ratio format is only available when both the LFRatioCfg bit is cleared (20.12) and the FracNSrc bit is set (dynamic ratio). In Auto Fractional-N Source Mode (see section 5.3.5.2 on page 21 ) when CLK_IN is not present the LFRatioCfg bit is ignored and the ratio format is 12.20. It is recommended that the 12.20 High-Resolution fo rmat be utilized whenever the desired ratio is less than 4096 since the output frequency accuracy of the PLL is directly proportional to the accuracy of the timing reference clock and the resolution of the RUD. Referenced Control Register Location Referenced Control Register Location

20 DS761F1

5.3.3 Ratio Modifier (R-Mod)

Table 1. Ratio Modifier

5.3.4 Effective Ratio (R EFF)

to be altered to account for internal dividers. tional-N Source Selection for the Frequency Synthesizer” on page 21).

5.3.5 Fractional-N Source Selection

To select between the static ratio based Frequency Synthesizer Mode and the dynamic ratio based Hybrid PLL Mode, the source for the fractional-N value for the Frequency Synthesizer must be changed. The Fractional-N value can either be sourced directly from the Effective Ratio (static ratio) or from the output of the Digital PLL (dynamic ratio) (see Figure 18 on page 22 ). The setting of this function can be made manual or automatically depending on the presence of CLK_IN.

5.3.5.1 Manual Fractional- N Source Selection for the Frequency Synthesizer

Manual selection of the fractional-N source for th e frequency synthesizer is made by setting the FracNSrc bit to select the desired ratio source. The LockClk[1:0] bits (even if unused) must be set to the same value as the RSel[1:0] bits in order to maintain manual selectability of this function (see Section 5.3.5.2 on page 21).

5.3.5.2 Automatic Fractional-N Source Se lection for the Frequency Synthesizer

Automatic source selection allows for the selection of the frequency synthesizer’s fractional-N value to be made dependent on the presence of the CLK_IN signal. When CLK_IN is present the device will use the dynamic ratio generated from the Digital PLL and CLK_IN for Hybrid PLL Mode. When CLK_IN is not present, the device will use RefClk and the static ratio fo r Frequency Synthesizer Mode. Before switching to SysClk and re-acquiring lock the CS2000 will wait for 223 SysClk cycles after losing CLK_IN (see “CLK_IN Skipping Mode” on page 15). The User Defined Ratio pointed to by RSel[1:0] should contain the desired CLK_OUT to RefClk ra- tio to be used when CLK_IN is not presen t. The User Defined Ratio pointed to by LockClk[1:0] should contain the desired CLK_OUT to CLK_IN ratio to be used when CL K_IN is present. Auto- matic source selection is enabled when the LockClk[1:0] bits are set to point to a different User De- fined Ratio from the one pointed to by the RSel[1:0] bits. When automatic source selection is enabled, the FracNSrc bit (used for manual clock selection) will be ignored. To disable the automatic source selection feature, set the LockClk[1:0] bits and the RSel[1:0] bits to the same value. The FracNSrc bit must then be used to select the desired clock used for the PLL’s frequency reference. Referenced Control Register Location Referenced Control Register Location

22 DS761F1

5.3.6 Ratio Configuration Summary

Figure 18. Ratio Feature Summary

5.4 PLL Clock Output

The PLL clock output pin (CLK_OUT) provides a buffered version of the output of the frequency synthesizer. The driver can be set to high-impedance with the ClkOutDis bit. CLK_OUT may then be unreliable during an unlock condition. Figure 19. PLL Clock Output Options

5.5 Auxiliary Output

then used to control the output driver ty pe and polarity of the LOCK signal (see section 8.7.2 on page 32). CLK_OUT pin. The driver for the pin can be set to high-impedance using the AuxOutDis bit. Figure 20. Auxiliary Output Selection

24 DS761F1

5.6 Clock Output Stability Considerations

5.6.1 Output Switching

CS2000 is designed such that re-configuration of the clock routing functions do not result in a partial clock period on any of the active outputs (CLK_OUT and/or AUX_OUT). In particular, enabling or disabling an output, changing the auxiliary output source between REF_CLK and CLK_OUT, changing between Fre- quency Synthesizer and Hybrid PLL Mode, and the automatic disabling of the output(s) during unlock will not cause a runt or partial clock period. The following exceptions/limitations exist:

• Enabling/disabling AUX_OUT when AuxOutSrc[1:0] = 11 (unlock indicator).
• Switching AuxOutSrc[1:0] to or from 01 (PLL clock input) and to or from 11 (unlock indicator) (Transitions between AuxOutSrc[1:0] = [00,10] will not produce a glitch).
• Changing the ClkOutUnl bit while the PLL is in operation. When any of these exceptions occur, a partial clock period on the output may result.

5.6.2 PLL Unlock Conditions

Certain changes to the clock inputs and registers can cause the PLL to lose lock which will affect the pres- ence the clock signal on CLK_OUT. The following outlines which conditions cause the PLL to go un- locked:

• Changes made to the registers which affect the Fr action-N value that is used by the Frequency Syn- thesizer. This includes all the bits shown in Figure 18 on page 22.
• Any discontinuities on the Ti ming Reference Clock, REF_CLK.
• Discontinuities on the Frequency Reference Clock, CLK_IN, except when the Clock Skipping feature is enabled and the requirements of Clock Skipping are satisfied (see “CLK_IN Skipping Mode” on page 15).
• Gradual changes in CLK_IN frequency great er than ±30% from the starting frequency.
• Step changes in CLK_IN frequency.

5.7 Required Power Up Sequencing

• Apply power to the device. The output pins will remain low until the device is configured with a valid ratio via the control port.
• Write the desired operational configurations. The EnDevCfg1 and EnDevCfg2 bits must be set to 1 dur- ing the initialization register writes; the order does not matter. – The Freeze bit may be set prior to this step and cleared afterward to ensure all settings take effect at the same time. 6. SPI / I²C CONTROL PORT The control port is used to access the registers and allows the device to be configured for the desired operational modes and formats. The operation of the control port may be completely asynchronous with respect to device inputs and outputs. However, to avoid potential interference problems, the control port pins should remain static if no op- eration is required.

the AD0/CS pin through a resistor to VD or GND, thereby permanently selecting the desired AD0 bit address state. In both modes the EnDevCfg1 and EnDevCfg2 bits must be set to 1 for normal operation. WARNING: All “Reserved” registers must maintain their default state to ensure proper functional operation.

6.1 SPI Control

device only supports write operations. the data which will be placed into the register designated by the MAP. ment after each byte is read or written, allowing block writes of successive registers.

6.2 I²C Control

In I²C Mode, SDA is a bidirectional dat a line. Data is clocked into and ou t of the device by the clock, SCL. the CS2000 after each input byte is read and is input from the microcontroller after each transmitted byte. Figure 21. Control Port Timing in SPI Mode

26 DS761F1

dition. The following pseudocode illustrates an aborted write operation followed by a read operation. Send 100111x0 (chip address & write operation). Send MAP byte, auto increment off. Send stop condition, aborting write. Send 100111x1(chip address & read operation). Receive byte, contents of selected register. byte is separated by an acknowledge bit. Figure 22. Control Port Timing, I²C Write Figure 23. Control Port Timing, I²C Aborted Write + Read

6.3 Memory Address Pointer

The Memory Address Pointer (MAP) byte comes after the address byte and selects the register to be read or written. Refer to the pseudocode above for implementation details.

6.3.1 Map Auto Increment

The device has MAP auto increment capability enabled by the INCR bit (the MSB) of the MAP. If INCR is set to 0, MAP will stay constant for successive I²C writes or reads and SPI writes. If INCR is set to 1, MAP will auto increment after each byte is read or written, allowing block reads or writes of successive regis- ters. 7. REGISTER QU ICK REFERENCE This table shows the register and bit names with their associated default values. EnDevCfg1 and EnDevCfg2 bits must be set to 1 for normal operation. WARNING: All “Reserved” registers must maintain their default state to ensure proper functional operation. Adr Name 7 6 5 4 3 2 1 0 01h Device ID Device4 Device3 Device2 Devic e1 Device0 Revision2 Revision1 Revision0 p2 8 00000 x xx 02h Device Ctrl Unlock Reserved Reserved Rese rved Reserved Reserved AuxOutDis ClkOutDis p2 8 xxx00000 03h Device Cfg 1 RModSel2 RModSel1 RModSel0 RSe l1 RSel0 AuxOutSrc1 AuxOutSrc0 EnDevCfg1 p2 9 00000 0 00 04h Device Cfg 2 Reserved Reserved Reserved Re served Reserved LockClk1 LockClk0 FracNSrc p3 0 00000 0 00 05h Global Cfg Reserved Reserved Reserved Res erved Freeze Reserved Reserved EnDevCfg2 p3 0 00000 0 00 06h 09h 32-Bit Ratio 0 0Ah 0Dh 32-Bit Ratio 1 0Eh 11h 32-Bit Ratio 2 12h 15h 32-Bit Ratio 3 16h Funct Cfg 1 ClkSkipEn AuxLockCfg Reserved Ref ClkDiv1 RefClkDiv0 Reserved Reserved Reserved p3 1 00000 0 00 17h Funct Cfg 2 Reserved Reserved Reserved ClkOutUnl LFRatioCfg Reserved Reserved Reserved p3 2 00000 0 00 1Eh Funct Cfg 3 Reserved ClkIn_BW2 ClkIn_BW1 Clk In_BW0 Reserved Reserved Reserved Reserved p3 2 00000 0 00

28 DS761F1

1. REGISTER DESCRIPTIONS In I²C Mode all registers are read/write unless otherwise stated. In SPI mode all registers are write only. All “Re- served” registers must maintain their default state to ensure proper functional operation. The default state of each bit after a power-up sequence or reset is indicated by the shaded row in the bit decode table and in the “Register Quick Reference” on page 27. Control port mode is entered when the device recognizes a valid chip address input on its I²C/SPI serial control pins and the EnDevCfg1 and EnDevCfg2 bits are set to 1. 8.1 Device I.D. and R evision (Address 01h)

8.1.1 Device Identification (Device[4:0]) - Read Only

I.D. code for the CS2000.

8.1.2 Device Revision (Revision[2:0]) - Read Only

CS2000 revision level.

8.2 Device Control (Address 02h)

8.2.1 Unlock Indicator (Unlock) - Read Only

Indicates the lock state of the PLL.

8.2.2 Auxiliary Output Disable (AuxOutDis)

This bit controls the output driver for the AUX_OUT pin. 76543210 Device4 Device3 Device2 Device1 Device0 Revision2 Revision1 Revision0 Device[4:0] Device 00000 CS2000. REVID[2:0] Revision Level

100 B2 and B3

Unlock Reserved Reserved Reserved Reserved Reserved AuxOutDis ClkOutDis Unlock PLL Lock State 0 PLL is Locked. 1 PLL is Unlocked. AuxOutDis Output Driver State 0 AUX_OUT output driver enabled. 1 AUX_OUT output driver set to high-impedance. Application: “Auxiliary Output” on page 23

8.2.3 PLL Clock Output Disable (ClkOutDis)

This bit controls the output driver for the CLK_OUT pin.

8.3 Device Configuration 1 (Address 03h)

8.3.1 R-Mod Selection (RModSel[2:0])

Selects the R-Mod value, which is used as a factor in determining the PLL’s Fractional N.

8.3.2 Ratio Selection (RSel[1:0])

Selects one of the four stored User Defined Ratios for use in the static ratio based Frequency Synthesizer Mode.

8.3.3 Auxiliary Output Sour ce Selection (AuxOutSrc[1:0])

Selects the source of the AUX_OUT signal. Note: When set to 11, AuxLckCfg sets the polarity and driver type. See “AUX PLL Lock Output Config- uration (AuxLockCfg)” on page 32. ClkOutDis Output Driver State 0 CLK_OUT output driver enabled. 1 CLK_OUT output driver set to high-impedance. Application: “PLL Clock Output” on page 23 76543210 RModSel2 RModSel1 RModSel0 RSel1 RSe l0 AuxOutSrc1 AuxOutSrc0 EnDevCfg1 RModSel[2:0] R-Mod Selection 000 Left-shift R-value by 0 (x 1). 001 Left-shift R-value by 1 (x 2). 010 Left-shift R-value by 2 (x 4). 011 Left-shift R-value by 3 (x 8). 100 Right-shift R-value by 1 (÷ 2). 101 Right-shift R-value by 2 (÷ 4). 110 Right-shift R-value by 3 (÷ 8). 111 Right-shift R-value by 4 (÷ 16). Application: “Ratio Modifier (R-Mod)” on page 20 RSel[1:0] Ratio Selection 00 Ratio 0. 01 Ratio 1. 10 Ratio 2. 11 Ratio 3. Application: “User Defined Ratio (RUD), Frequency Synthesizer Mode” on page 19 AuxOutSrc[1:0] Auxiliary Output Source 00 RefClk. 01 CLK_IN. 10 CLK_OUT. 11 PLL Lock Status Indicator. Application: “Auxiliary Output” on page 23

30 DS761F1

8.3.4 Enable Device Configurat ion Registers 1 (EnDevCfg1)

This bit, in conjunction with EnDevCfg2, configures the device for control port mode. These EnDevCfg bits can be set in any order and at any time during the control port access sequence, however they must both be set before normal operation can occur. Note: EnDevCfg2 must also be set to enable control port mode. See “SPI / I²C Co ntrol Port” on page 24.

8.4 Device Configuration 2 (Address 04h)

8.4.1 Lock Clock Ratio (LockClk[1:0])

Selects one of the four stored User Defined Ratios for use in the dynamic ratio based Hybrid PLL Mode.

8.4.2 Fractional-N Source for Fr equency Synthesizer (FracNSrc)

Selects static or dynamic ratio mode when auto clock switching is disabled.

8.5 Global Configur ation (Address 05h)

8.5.1 Device Configuration Freeze (Freeze)

Setting this bit allows writes to the Device Control and Device Configuration registers (address 02h - 04h) but keeps them from taking effect until this bit is cleared. EnDevCfg1 Register State 0 Disabled. 1 Enabled. Application: “SPI / I²C Control Port” on page 24 76543210 Reserved Reserved Reserved Reserved Reserved LockClk1 LockClk0 FracNSrc LockClk[1:0] CLK_IN Ratio Selection 00 Ratio 0. 01 Ratio 1. 10 Ratio 2. 11 Ratio 3. Application: Section 5.3.2 on page 19 FracNSrc Fractional-N Source Selection

0 Static Ratio directly from REFF for Frequency Synthesizer Mode

1 Dynamic Ratio from Digital PLL for Hybrid PLL Mode

Application: “Fractional-N Source Selection” on page 21 76543210 Reserved Reserved Reserved Reserved Freeze Reserved Reserved EnDevCfg2 FREEZE Device Control and Configuration Registers 0 Register changes take effect immediately. 1 Modifications may be made to Device Control and Device Configuration registers (registers 02h-04h) without the changes taking effect until after the FREEZE bit is cleared.

8.5.2 Enable Device Configurat ion Registers 2 (EnDevCfg2)

This bit, in conjunction with EnDevCfg1, configures the device for control port mode. These EnDevCfg bits can be set in any order and at any time during the control port access sequence, however they must both be set before normal operation can occur. Note: EnDevCfg1 must also be set to enable control port mode. See “SPI / I²C Co ntrol Port” on page 24.

8.6 Ratio 0 - 3 (Address 06h - 15h)

These registers contain the User Defined Ratios as shown in the “Register Quick Reference” section on page 27. Each group of 4 registers forms a single 32-bit ratio value as shown above. See “Output to Input Frequency Ratio Configuration” on page 19 and “Calculating the User Defined Ratio” on page 34 for more details.

8.7 Function Configuration 1 (Address 16h)

8.7.1 Clock Skip Enable (ClkSkipEn)

This bit enables clock skipping mode for the PLL and allows the PLL to mainta in lock even when the CLK_IN has missing pulses. Note: fCLK_IN must be < 80 kHz and re-applied within 20 ms to use this feature. EnDevCfg2 Register State 0 Disabled. 1 Enabled. Application: “SPI / I²C Control Port” on page 24 76543210 76543210 ClkSkipEn AuxLockCfg Reserved RefClkDiv 1 RefClkDiv0 Reserved Reserved Reserved ClkSkipEn PLL Clock Skipping Mode 0 Disabled. 1 Enabled. Application: “CLK_IN Skipping Mode” on page 15

32 DS761F1

8.7.2 AUX PLL Lock Output Configuration (AuxLockCfg)

When the AUX_OUT pin is configured as a lock indicator ( AuxOutSrc[1:0] = 11), this bit configures the AUX_OUT driver to either push-pull or open drain. It also determines the polarity of the lock signal. If AUX_OUT is configured as a clock output, the state of this bit is disregarded. Note: AUX_OUT is an unlock indicator, signalling an error condition when the PLL is unlocked. There- fore, the pin polarity is defined relative to the unlock condition.

8.7.3 Reference Clock Input Divider (RefClkDiv[1:0])

Selects the input divider for the timing reference clock.

8.8 Function Configuration 2 (Address 17h)

8.8.1 Enable PLL Clock Out put on Unlock (ClkOutUnl)

Defines the state of the PLL output during the PLL unlock condition.

8.8.2 Low-Frequency Ratio Configuration (LFRatioCfg)

Determines how to interpret the currently indexed 32-bit User Defined Ratio when the dynamic ratio based Hybrid PLL Mode is selected (either manually or automatically, see section 5.3.5 on page 21). Note: When the static ratio based Fr equency Synthesizer Mode is sele cted (either manually or auto- matically), the currently indexed User Defined Ratio will always be interpreted as a 12.20 fixed point value, regardless of the state of this bit. AuxLockCfg AUX_OUT Driver Configuration 0 Push-Pull, Active High (output ‘high’ for unlocked condition, ‘low’ for locked condition). 1 Open Drain, Active Low (output ‘low’ for unl ocked condition, high-Z for locked condition). Application: “Auxiliary Output” on page 23 RefClkDiv[1:0] Reference Clock Input Divider REF_CLK Frequency Range 00 ÷4 . 32 MHz to 56 MHz (50 MHz with XTI) 01 ÷ 2. 16 MHz to 28 MHz 10 ÷ 1. 8 MHz to 14 MHz 11 Reserved. Application: “Internal Timing Reference Clock Divider” on page 14 76543210 Reserved Reserved Reserved ClkOutUnl LFRatioCfg Reserved Reserved Reserved ClkOutUnl Clock Output Enable Status 0 Clock outputs are driven ‘low’ when PLL is unlocked. 1 Clock outputs are always enabled (results in unpredictable output when PLL is unlocked). Application: “PLL Clock Output” on page 23 LFRatioCfg Ratio Bit Encoding Interpretation when Input Clock Source is CLK_IN 0 20.12 - High Multiplier. 1 12.20 - High Accuracy. Application: “User Defined Ratio (RUD), Hybrid PLL Mode” on page 19

8.9 Function Configuration 3 (Address 1Eh)

8.9.1 Clock Input Bandwidth (ClkIn_BW[2:0])

Sets the minimum loop bandwidth when locked to CLK_IN. Note: In order to guarantee that a change in minimum bandwidth takes effect, these bits must be set prior to acquiring lock (removing and re-applying CLK_IN can provide the unlock condition necessary to initiate the setting change). In production systems these bits should be configured with the desired values prior to setting the EnDevCfg bits; this guarantees that the setting takes effect prior to acquiring lock. 76543210 Reserved ClkIn_BW2 ClkIn_BW1 ClkIn_BW0 Reserved Reserved Reserved Reserved ClkIn_BW[2:0] Minimum Loop Bandwidth 000 1 Hz 001 2 Hz 010 4 Hz 011 8 Hz 100 16 Hz 101 32 Hz 110 64 Hz 111 128 Hz Application: “Adjusting the Minimum Loop Bandwidth for CLK_IN” on page 17

34 DS761F1

1. CALCULATING THE US ER DEFINED RATIO

systems without the aid of the evaluation kit. generate a binary or hex value which can be written to the Ratio0-3 registers. culator and write to the register. A few examples have been provided in Table 2. Table 2. Example 12.20 R-Values write to the register. A few examples have been provided in Table 3. Table 3. Example 20.12 R-Values

12.288 MHz/60 Hz=204,800 838860800 32 00 00 00

10.PACKAGE DIMENSIONS Notes: 1. Reference document: JEDEC MO-187 2. D does not include mold flash or prot rusions which is 0.15 mm max. per side. 3. E1 does not include inter-lead flash or protrusions which is 0.15 mm max per side. 4. Dimension b does not include a total allo wable dambar protrusion of 0.08 mm max. 5. Exceptions to JEDEC dimension. THERMAL CHARACTERISTICS INCHES MILLIMETERS NOTE DIM MIN NOM MAX MIN NOM MAX A1 0 -- 0.0059 0 -- 0.15 A2 0.0295 -- 0.0374 0.75 -- 0.95 b 0.0059 -- 0.0118 0.15 -- 0.30 4, 5 Parameter Symbol Min Typ Max Units Junction to Ambient Thermal Impedance JEDEC 2-Layer JEDEC 4-Layer θJA θJA 170 100 °C/W °C/W 10L MSOP (3 mm BODY) PACKAGE DRAWING (Note 1) E N 1 23 e b A1 A2 A D SEATING PLANE E11 L SIDE VIEW END VIEW TOP VIEW c

36 DS761F1

11.ORDERING INFORMATION 12.REFERENCES 1. Audio Engineering Society AES-12id-2006: “AES Information Document for digital audio measurements - Jitter performance specifications,” May 2007. 2. Philips Semiconductor, “ The I²C-Bus Specification: Version 2,” Dec. 1998. http://www.semiconductors.philips.com 13.REVISION HISTORY Product Description Package Pb-Free Grade Temp Range Container Order# CS2000-CP Clocking Device 10L-MSOP Yes Commercial -10° to +70°C Rail CS2000CP-CZZ CS2000-CP Clocking Device 10L-MSOP Yes -10° to +70°C Tape and Reel CS2000CP-CZZR CDK2000 Evaluation Platform - Yes - - - CDK2000-CLK Release Changes F1 Updated Period Jitter specification in “AC Electrical Characteristics” on page 8. Updated Crystal and Ref Clock Frequency specifications in “AC Electrical Characteristics” on page 8. Added “PLL Performance Plots” section on page 9. Updated “Internal Timing Reference Clock Divider” on page 14 and added Figure 11 on page 14. Updated use conditions for “CLK_IN Skipping Mode” section on page 15 and page 31. Updated Figure 13 on page 16. Removed FsDetect and Auto R-Mod features per ER758rev2. Contacting Cirrus Logic Support For all product questions and inquiries, contact a Cirrus Logic Sales Representative. To find one nearest you, go to www.cirrus.com IMPORTANT NOTICE Cirrus Logic, Inc. and its subsidiaries (“Cirrus”) believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives con- sent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROP- ERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRIT- ICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK AND CIR- RUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOM- ER’S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING AT- TORNEYS’ FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. I²C is a trademark of Philips Semiconductor. SPI is a trademark of Motorola, Inc.