CDC3207G MICRONAS | Alldatasheet

Document overview

  • Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
  • PDF pages: 2

Technical content

Features

◆ 512 KB Flash ◆ 32 KB SRAM ◆ 8 KB boot ROM ◆ Four CPU operation modes (Deep Slow, Slow, Fast, PLL) ◆ Three low-power modes (Idle, Wake, Standby) ◆ RTC delivering hours, minutes, seconds ◆ Polling/Flash timer output ◆ PLL circuitry delivering up to 50 MHz ◆ 4- to 5-MHz oscillator ◆ EMI reduction module (ERM) ◆ Digital watchdog ◆ Central clock divider ◆ Interrupt controller with 40 inputs and 16 priority levels ◆ Six port interrupts ◆ Regulator input supervision for reset/ alarm (alarm comparator) ◆ Clock and supply supervision ◆ 16-channel 10-bit ADC ◆ Two comparators ◆ ADC reference (1 internal, 3 external) ◆ 48×4 LCD module ◆ Three DMA channels ◆ Two UARTs, two SPIs ◆ DigitBus master module ◆ Four CAN modules with 512 Bytes each of object RAM according to Bosch speci- fication V2.0B (32 message objects) ◆ Two I2C master modules ◆ Seven stepper motor drivers ◆ Six PWM modules (configurable as 2 ×8 bit or 1×16 bit) ◆ Pulse frequency modulator ◆ Sound generator with auto decay ◆ Two SW-selectable clock outputs ◆ 16-bit free-running counter with six cap- ture/compare modules ◆ Patch module (up to 10 cells) ◆ Device lock module (DLM) inhibiting Flash access ◆ 1×16-bit timer and 4 ×8-bit timer ◆ JTAG interface ◆ −40 to +105 °C case temperature range ◆ Single 3.5 V to 5.5 V supply voltage (limited I/O performance below 4.5 V) ◆ Up to 102 GPIOs ◆ 128-pin PQFP package, 0.5 mm pin pitch

All information and data contained in this product information are without any commitment, are not to be consid- ered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our respective order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH ⋅ Hans-Bunte-Strasse 19 ⋅ D-79108 Freiburg (Germany) ⋅ P.O. Box 840 ⋅ D-79008 Freiburg (Germany) Tel. +49-761-517-0 ⋅ Fax +49-761-517-2174 ⋅ E-mail: docservice@micronas.com ⋅ www.micronas.com No part of this publication may be reproduced, photo- copied, stored on a retrieval system, or transmitted without the express written consent of Micronas GmbH. Edition May 18, 2005; Order No. 6251-596-3PI JTAG Probe EVB JTAG JTAG ETM Trace Probe Logic Analyzer Development Tools ◆ Evaluation chip CDC 3205G featuring – ETM via embedded emulation JTAG – ROM/Flash emulation with external SRAM (up to 8 MBytes) ◆ Evaluation Board (EVB) including the CDC 3205G for evaluation and debug- ging of embedded systems ◆ Application Board (APB) for Flash mem- ory programming ◆ Probe for PQFP128 ◆ Software environment (compiler, linker, assembler) from 3 rd party vendors ◆ RTOS from 3rd party vendors ◆ CAN protocol stacks System Architecture The Car Dashboard Controller CDC 3207G contains an embedded ARM7TDMI proces- sor which operates at a maximum clock fre- quency of 50 MHz. The internal high-speed bus connects the following peripherals to the ARM7TDMI pro- cessor: ◆ ICU (Interrupt Control Unit) ◆ SRAM ◆ DMA The 16/32-bit bus connects to Flash and boot ROM. All other peripherals are con- nected to the I/O bus. All I/O ports have multiple functions to obtain utmost flexibility. A total of 102 GPIOs can be selected. The built-in ERM delivers superb EMI results reducing the peak values by up to 10 dBµV. The CDC 3207G is fully pin- and software- compatible with all other members of the CDC 32xxG family. Fig. 2: Block diagram of the CDC 3207G VREFINT VREF AVDD AVSS BVDD HPorts UPorts PPorts UARTS2 × UART UARTS2 × SPI UARTS4 × CAN UARTSDIGITBus UARTS2 × I²C Bus UARTSLCD Control UARTSAudio Module UARTSClock Out 0,1 UARTS16- Bit CCC 0 UARTS UARTS16- Bit CCC 1 UARTS 10-Bit ADC ARM7TDMI CPU DMA Contr. 40-Input Interrupt Controller

32 KB SRAM

512 KB Flash

8 KB Boot ROM

P0.6 Comp Wait Comp VDD VSS UVDD UVSS FVDD FVSS 3.3-V Reg. 2.5-V Reg. 2.5-V Reg. 7 × Stepper Motor Module UARTS1 × 16-Bit Timer UARTS4 × 8-Bit TimerUARTS6 × 8/ 16-B it PWM 5232 CAPCOM 0,1,2,3 CAPCOM 4, 5 Bandgap Ref. PFM 0/1 Patch Module JTAG Interface Test / Debug Reset Test Watchdog Clock PLL/ERM RTC Power Saving Fig. 1: Development tool setup