CDBS61880 CIRRUS | Alldatasheet
Document overview
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Technical content
Features
zSocketed CS61880 Octal Line Interface Unit zBinding post connectors for power and line interface connections zComponents supplied for all operational modes E1 75 Ω and E1 120 Ω zSocketed termination circuitry for easy testing zConnector for IEEE 1149.1 JTAG Boundary Scan zLED Indicators for Loss of Signal (LOS) and power zSupports Hardware, Serial, and Parallel Host Modes zEasy-to-use evaluation software zOn-board socketed reference clock oscillator
Description
The CS61880 evaluation board is used to demonstrate the functions of a CS61880 Octal Line Interface Unit in either E1 75 Ω or E1 120 Ω. The evaluation board can be operated in either Hard- ware mode or Host mode. In Hardware mode, switches and bed stake headers are used to control the line con- figuration and channel operations for all eight channels. In Host mode (Serial or Parallel), the evaluation soft- ware, switches, and bed stake headers are used to control the line configuration and operating mode set- tings for each channel. In both Hardware and Host modes, the board may be configured for E1 75 Ω or E1 120 Ω operating modes. In both modes binding post connectors provide easy con- nections between the line interface connections of the CS61880 and any E1 analyzing equipment, which may be used to evaluate the CS61880 device. Bed stake headers allow easy access to each channel’s clock and data I/O digital interface. Eight LED indictors display the Loss of Signal (LOS) conditions for each channel during Hardware and Host modes. An LED indictor is used on the Interrupt pin to in- dicate a change of state. Note: Click on any text in blue to go to cross-references
ORDERING INFORMATION
CS61880-IQ -40° to 85° C 144-pin LQFP CDB61880 Evaluation Board MAR ‘02 DS450DB1
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Contacting Cirrus Logic Support For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at: http://www.cirrus.com/corporate/contacts/sales.cfm IMPORTANT NOTICE “Preliminary” product information describes products that are in production, but for which full characterization data is not ye t available. “Advance” product infor- mation describes products that are in development and subject to development changes. Cirrus Logic, Inc. and its subsidiaries ( “Cirrus”) believe that the infor- mation contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of or der acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liab ility. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyright s, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights of the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other parts of Cirrus. This consent does not ext end to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. An export permit needs to be obtained from the competent authorities of the Japanese Government if any of the products or techn ologies described in this ma- terial and controlled under the “Foreign Exchange and Foreign Trade Law” is to be exported or taken out of Japan. An export lic ense and/or quota needs to be obtained from the competent authorities of the Chinese Government if any of the products or technologies described in this mate rial is subject to the PRC Foreign Trade Law and is to be exported or taken out of the PRC. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANT- ED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trade- marks or service marks of their respective owners.
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- CDB61880 EVALUATION BOARD LAYOUT
Figure 1. CDB61880 Board Layout
- BOARD COMPONENT DESCRIPTIONS
2.1 Power Connections
connected to either +3 V or +5 V binding post. to be made at the +3 V binding post.
2.2 Master Clock Selection
the different positions of the J1 bed stake header. connection for an external clock source. Figure 2. On-board Logic Power Selection Figure 3. Master Clock Selections
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2.3 Operating Mode Selection
2.4 Line Interface Connections
device through two octal transformers (T1 and T9). odes or chokes are recommended for protection.
2.5 TXOE Selection
Table 1. External Impedance Resistor Values Figure 4. Hardware/Host Mode Selection Table 2. Protection Resistor Selection
2.6 Clock Edge Selection
2.7 Jitter Attenuator Selection
shows the settings for switch S10.
2.8 Loopback Mode Selection
Figure 5. Transmitter Enable Selection Figure 6. Clock Edge Selection Figure 7. Jitter Attenuator Selection Figure 8. Loopback Mode Selection
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2.9 Line Length/Impedance Selection
2.10 Coder/Motorola/Intel Selection
closed (low) position enables HDB3 coding. in Hardware and Parallel Host mode. the CS61880 Data Sheet for more address settings. dress signals during Parallel Host modes.
2.12 Mux/Non-Mux/BITS Clock Selection
tion disables this function. the closed “LOW” position selects Non-multiplex. Figure 9. Switch S9 Settings
2.13 Digital Signal Connections
LOS signals, in both Hardware And Host mode. tings for the TCLK/TNEG pins.
2.14 LOS Indicators
2.15 JTAG Connection
Scan signals from the device.
2.16 Host Interface Connection
standard 25 pin male to female parallel port cable. both serial and parallel interface. on page 6 for switch S15 settings. Figure 10. Digital Signal Control/Access Table 3. Switch Settings for Host Mode
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4.1 Starting the Software
ware is used to evaluate the CS61880 device. after you have launched the software.
4.2 Software Interface Buttons
tion screens in the CS61880 software.
4.2.1 Bit Indicator Description
4.3 Set All Button Description
Figure 11. CS61884 Software Opening Screen Figure 12. Register Bit Box Figure 13. Set All Button
4.3.1 Clear All Button Description
4.3.2 Write All Button Description
corner of each register screen.
4.3.3 Read All Button Description
ner of each register screen.
4.4 Write Button Description
4.5 Read Button Description
to the right of every register.
4.6 Program Exit Function
Figure 14. Clear All Button Figure 15. Write All Button Figure 16. Read All Button Figure 17. Write Button Figure 18. Read Button
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- CS61880 CONFIGURATION SCREENS
5.1 Choose Parallel Port Settings
erational modes you wish to use.
- If the mode of operation does not match the
- If the parallel port address does not match
5.2 Access and Configure the Read / Write
5.2.1 Access Configuration Screens
opening screen to start configuring these registers.
5.2.2 Select Register to Configure
Figure 19. Opening Screen for Port and Address Selection Screen
5.3 Loopback /Bits Clock Screen
Figure 20. Loopback/G.703 Bits Clock Selection Screen
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5.4 LOS/AIS/DFM/JA Register Screen
- JA Error Interrupt Status.
Figure 21. LOS/AIS/DFM/JA ERR Status/Enable Selection Screen
5.5 Transmitter Register Screen
means that these bits can not be accessed. Figure 22. Transmitter Register Screen
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5.6 AWG Register Screen
section of the CS61880 Data Sheet. Figure 23. AWG Registers Screen
5.7 Global Control Register Screen
Figure 24. Global Control Screen
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6.1 E1 75 ΩΩΩΩ Mode Setup
bold should be set to the position stated.
- Connect a standard 25-pin male to female parallel port cable to connector J12 and the control PC.
- Set “HIGH” to enable BITS Clock Recovery function for only Channel #0 in Hardware Mode.
- Other settings may be used to enter G.772 Non-Intrusive Monitoring in Hardware Mode. Refer to the
CS61880 Data Sheet for other settings.
- Set “LOW” to disable receiver Internal line impedance matching function. The external resistors for all
eight receivers must be changed to 9.31 Ω to properly match the input line impedance. Table 4. E1 75 ΩΩΩΩ Operational Mode Switch/Jumper Position
6.2 E1 120 ΩΩΩΩ Mode Setup
bold should be set to the position stated.
- Set to “NC” to disable receiver Internal line impedance matching function. The external resistors for all
eight receivers must be changed to 15 Ω to properly match the input line impedance. Table 5. E1 120 ΩΩΩΩ Operational Mode Switch/Jumper Position
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- EVALUATION HINTS - Pin #1 of the socket is indicated by an arrow with U1 below it. - A short in the desired position must be placed on Jumper J13 to connect the CS61880 to one of the power supply binding post. LED D3 will illuminate when jumper J13 is connected to a power supply. - Before selecting any Host mode place the CBLSEL, LOOP, ADDRESS and JASEL switches in the open or none position. - When using the CS61880 device in Internal Match Impedance mode, be sure that the 1 KΩ resistors are not in series with the receivers.
- Notes