CDB8422

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Technical content

Features

 Complete EIAJ CP1201, IEC-60958, AES3, S/PDIF Compatible Receiver  28 kHz to 216 kHz Sample Rate Range  2:1 Differential AES3 or 4:1 S/PDIF Input Mux  De-emphasis Filtering for 32 kHz, 44.1 kHz, and 48 kHz  Recovered Master Clock Output: 64 x Fs, 96 x Fs, 128 x Fs, 192 x Fs, 256 x Fs, 384 x Fs, 512 x Fs, 768 x Fs, 1024 x Fs  49.152 MHz Maximum Recovered Master Clock Frequency  Ultra-low-jitter Clock Recovery  High Input Jitter Tolerance  No External PLL Filter Components Required  Selectable and Automatic Clock Switching  AES3 Direct Output and AES3 TX Pass- through  On-chip Channel Status Data Buffering  Automatic Detection of Compressed Audio Streams  Decodes CD Q Sub-Code Serial Audio Input 4:1 MUX RX0/RXP0 RX1/RXN0 RX2/RXP1 RX3/RXN1 Receiver Clock & Data Recovery (PLL) ILRCK ISCLK SDIN Sample Rate Converter C or U Data Buffer (First 5 Bytes) Control Port & Registers 2:1 MUX Serial Audio Output3:1 MUX XTI Clock Generator SDA/ CDOUT SCL/ CCLK AD1/ CDIN AD0/ CS RMCK General Purpose Outputs GPO0Format Detect GPO1 GPO2 GPO3 OLRCK1 OSCLK1 SDOUT1 TDM_IN Serial Audio Output 3:1 MUX OLRCK2 OSCLK2 SDOUT2 VL VA AGND XTO Level Translators Level Translators DGND V_REG MAY '09 DS692PP2 CS8422

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 SPI™ or I²C® Software Mode and Stand-alone Hardware Mode  Flexible 3-wire Digital Serial Audio Input Port  Dual Serial Audio Output Ports with Independently Selectable Data Paths  Master or Slave Mode Operation for all Serial Audio Ports  Time Division Multiplexing (TDM) Mode  Integrated Oscillator for use with External Crystal  Four General-purpose Output Pins (GPO)  +3.3 V Analog Supply (VA)  +1.8 V to 5.0 V Digital Interface (VL)  Space-saving 32-pin QFN Package General Description The CS8422 is a 24-bit, high-performance, monolithic CMOS stereo asynchronous sample rate converter with an integrated digital audio in terface receiver that de- codes audio data according to the EIAJ CP1201, IEC- 60958, AES3, and S/PDIF interface standards. Audio data is input through the digital interface receiver or a 3-wire serial audio input port. Audio is output through one of two 3-wire serial audio output ports. Se- rial audio data outputs can be set to 24-, 20-, 18-, or 16- bit word-lengths. Data into the digital interface receiver and serial audio input port can be up to 24-bits long. In- put and output data can be completely asynchronous, synchronous to an external clock through XTI, or syn- chronous to the recovered master clock. The CS8422 can be controlled through the control port in Software Mode or in a Stand-Alone Hardware Mode. In Software Mode, the user can control the device through an SPI or I²C control port. Target applications inclu de digital recording systems (DVD-R/RW, CD-R/RW, PVR, DAT, MD, and VTR), dig- ital mixing consoles, high-quality D/A, effects processors, computer audio systems, and automotive audio systems. The CS8422 is available in a space-saving QFN pack- age in both Commercial (-40° C to +85° C) and Automotive (-40° C to +105° C) grades. The CDB4822 is also available for device evaluation and implementa- tion suggestions. Please refer to “Ordering Information” on page 80 for complete details.

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Figure 28.S/PDIF MUX Input Circuit, Single-Ended Receiver Mode 1 Single-Ended Input Circuit –

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1. PIN DESCRIPTION

1.1 Software Mode

Pin Name Pin # Pin Description RX[3:0], RXP/RXN[1:0] AES3/SPDIF Input (Input) - Single-ended or differential receiver inputs carrying AES3 or S/PDIF encoded digital data. RX[3:0] comprise the single-ended input multiplexer. RXP[1:0] comprise the non-inverting inputs of the differential input multiplexer and RXN[1:0] comprise the inverting inputs of the differential input multiplexer. Unused inputs should be tied to AGND/DGND. VA 3 Analog Power (Input) - Analog power supply, nominally +3.3 V. Care should be taken to ensure that this supply is as noise-free as possible, as noise on this pin will directly affect the jitter perfor- mance of the recovered clock. AGND 4 Analog Ground (Input) - Ground for the analog circuitry in the chip. AGND and DGND should be connected to a common ground area under the chip. AD0/CS Address Bit 0 (I²C) / Software Chip Select (SPI) (Input) - A falling edge on this pin puts the CS8422 into SPI Control Port Mode. With no falling edge, the CS8422 defaults to I²C Mode. In I²C Mode, AD0 is a chip address pin. In SPI Mode, CS is used to enable the control port interface on the CS8422. See “Control Port Description” on page 42. AD1/CDIN 8 Address Bit 1 (I²C) / Serial Control Data in (SPI) (Input) - In I²C Mode, AD1 is a chip address pin. In SPI Mode, CDIN is the input data line to the control port interface. See “Control Port Description” on page 42. SCL/CCLK 9 Software Clock (Input) - Serial control interface clock used to clock control data bits into and out of the CS8422. SDA/CDOUT 10 Serial Control Data I/O (I²C) / Data Out (SPI) (Input/Output) - In I²C Mode, SDA is the control I/O data line. In SPI Mode, CDOUT is the output data from the control port interface on the CS8422. 109 11 12 13 14 15 16 2526272829303132 Top-Down View 32-Pin QFN Package Thermal Pad XTO ILRCK GPO3 OLRCK1 OSCLK1 SDOUT1 OSCLK2 VA AGND AD0/CS RX0/RXP0 SDOUT2 VL TDM_IN OLRCK2 RX1/RXN0 RX2/RXP1 RX3/RXN1 RMCK GPO2 VD_FILT V_REG XTI AD1/CDIN SDA/CDOUT SCL/CCLK ISCLK GPO1 GPO0 SDIN DGND RST

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XTI 11 Crystal/Oscillator In (Input) - Crystal or digital clock input for Master clock. See “SRC Master Clock” on page 38 for more details. XTO 12 Crystal Out (Output) - Crystal output for Master clock. See “SRC Master Clock” on page 38 for more details. ILRCK 13 Serial Audio Input Left/Right Clock (Input/Output) - Word rate clock for the audio data on the SDIN pin. ISCLK 14 Serial Audio Input Bit Clock (Input/Output) - Serial bit clock for audio data on the SDIN pin. SDIN 15 Serial Audio Input Data Port (Input) - Audio data serial input pin. GPO[3:0] General Purpose Outputs (Output) - See page 50 for details. In I²C Mode, a 20 kΩ pull-up resistor to VL on GPO2 will set AD2 chip address bit to 1, otherwise AD2 will be 0. V_REG 19 Voltage Regulator In (Input) - Regulator power supply input, nominally +3.3 V. VD_FILT 20 Digital Voltage Regulator (Output) - Digital core voltage regulator output. Should be connected to digital ground through a 10 µF capacitor. Typically +2.5 V. Cannot be used as an external voltage source. DGND 21 Digital & I/O Ground (Input) - Ground for the I/O and core logic. AGND and DGND should be con- nected to a common ground area under the chip. SDOUT2 23 Serial Audio Output 2 Data Port (Output) - Audio data serial output 2 pin. OSCLK2 24 Serial Audio Output 2 Bit Clock (Input/Output) - Serial bit clock for audio data on the SDOUT2 pin. OLRCK2 25 Serial Audio Output 2 Left/Right Clock (Input/Output) - Word rate clock for the audio data on the SDOUT2 pin. TDM_IN 26 Serial Audio Output 1 TDM Input (Input) - Time Division Multiplexing serial audio data input. Should remain grounded when not used. See “Time Division Multiplexing (TDM) Mode” on page 27 SDOUT1 27 Serial Audio Output 1 Data Port (Output) - Audio data serial output 1 pin. OSCLK1 28 Serial Audio Output 1 Bit Clock (Input/Output) - Serial bit clock for audio data on the SDOUT 1 pin. OLRCK1 29 Serial Audio Output 1 Left/Right Clock (Input/Output) - Word rate clock for the audio data on the SDOUT 1 pin. RMCK 31 Recovered Master Clock (Output) - Recovered master clock from the PLL. Frequency is 128x, 192x, 256x, 384x, 512x, 768x, or 1024x Fs, where Fs is the sample rate of the incoming AES3- compatible data, or ISCLK/64. RST 32 Reset (Input) - When RST is low the CS8422 enters a low power mode and all internal states are reset. On initial power up RST must be held low until the power supply is stable and all input clocks are stable in frequency and phase. THERMAL PAD - Thermal Pad - Thermal relief pad. Should be connected to the ground plane for optimized heat dis- sipation. Pin Name Pin # Pin Description

1.2 Hardware Mode

Pin Name Pin # Pin Description RXP/RXN[1:0] AES3/SPDIF Input (Input) - Differential receiver inputs carrying AES3 or S/PDIF encoded digital data. RXP[1:0] comprise the non-inverting inputs of the differential input multiplexer; and RXN[1:0] comprise the inverting inputs of the input multiplexer. Unused inputs should be tied to AGND. VA 3 Analog Power (Input) - Analog power supply, nominally +3.3 V. Care should be taken to ensure that this supply is as noise-free as possible, as noise on this pin will directly affect the jitter performance of the recovered clock. AGND 4 Analog Ground (Input) - Ground for the analog circuitry in the chip. AGND and DGND should be connected to a common ground area under the chip. SAOF 7 Serial Audio Output Format Select (Input) - Used to select the serial audio output format after reset. See Table 4 on page 41 for format settings. MS_SEL 8 Master/Slave Select (Input) - Used to select Master or Slave settings for the input and output serial audio ports after reset. See Table 5 on page 41 for format settings. NV/RERR 9 Non-Validity Receiver Error/Receiver Error (Output) - Receiver error indicator. NVERR is output by default, RERR is selected by a 20 kΩ resistor to VL. V/AUDIO 10 Validity Data/AUDIO (Output) - If a 20 kΩ pull-down is present on this pin, it will output serial Validity data from the AES3 receiver, clocked by the rising and falling edges of OLRCK2 in master mode. If a 20 kΩ pull-up is present, the pin will be low when valid linear PCM data is present at the AES3 input. XTI 11 Crystal/Oscillator In (Input) - Crystal or digital clock input for Master clock. See “SRC Master Clock” on page 38. XTO 12 Crystal Out (Output) - Crystal output for Master clock. See “SRC Master Clock” on page 38. 109 11 12 13 14 15 16 2526272829303132 Top-Down View 32-Pin QFN Package Thermal Pad XTO MCLK_OUT SRC_UNLOCK SDOUT1 OSCLK2 VA AGND SAOF RXP0 SDOUT2 VL TDM_IN OLRCK2 RXN0 RXP1 RXN1 RMCK TX/U VD_FILT V_REG XTI MS_SEL V/AUDIO NV/RERR TX_SEL C RCBL RX_SEL DGND RST OSCLK1 OLRCK1

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MCLK_OUT 13 Buffered MCLK (Output) - Buffered output of XTI clock. If a 20 kΩ pull-up resistor to VL is present on this pin, the SRC MCLK source will be the PLL clock, otherwise it will be the ring oscillator. TX_SEL 14 TX Pin MUX Selection (Input) - Used to select the AES3-compatible receiver input for pass-through to the TX pin. RX_SEL 15 Receiver MUX Selection (Input) - Used to select the active AES3-compatible receiver input. RCBL 16 Receiver Channel Status Block (Output) -Indicates the beginning of a received channel status block. Will go high for one subframe during each Z preamble following the first detected Z preamble. If no Z preamble is detected, output is indeterminate. See Figure 19 on page 36 for more detail. C1 7 Channel Status Data (Output) - Serial channel status data output from the AES3-compatible receiver, clocked by the rising and falling edges of OLRCK2 in master mode. A 20 kΩ pull-up resistor to VL must be present on this pin to put the part in Hardware Mode. TX/U 18 Receiver MUX Pass-through/User Data (Output) - If no 20 kΩ pull-up resistor is present on this pin it will output a copy of the receiver mux input selected by the TX_SEL pin. If a 20 kΩ pull-up resistor to VL is present on this pin, it will output serial User data from the AES3 receiver, clocked by the rising and falling edges of OLRCK2 in master mode. V_REG 19 Voltage Regulator In (Input) - Regulator power supply input, nominally +3.3 V. VD_FILT 20 Digital Voltage Regulator Out (Output) - Digital core voltage regulator output. Should be connected to digital ground through a 10 µF capacitor. Cannot be used as an external voltage source. DGND 21 Digital & I/O Ground (Input) - Ground for the I/O and core logic. AGND and DGND should be con- nected to a common ground area under the chip. SDOUT2 23 Serial Audio Output 2 Data Port (Output) - Audio data serial output 2 pin. OSCLK2 24 Serial Audio Output 2 Bit Clock (Input/Output) - Serial bit clock for audio data on the SDOUT2 pin. OLRCK2 25 Serial Audio Output 2 Left/Right Clock (Input/Output) - Word rate clock for the audio data on the SDOUT2 pin. TDM_IN 26 Serial Audio Output 1 TDM Input (Input) - Time Division Multiplexing serial audio data input. Grounded when not used. See “Time Division Multiplexing (TDM) Mode” on page 27 for details. SDOUT1 27 Serial Audio Output 1 Data Port (Output) - Audio data serial output 1 pin. A 20 kΩ pull-up to VL present on this pin will disable de-emphasis auto detect. OSCLK1 28 Serial Audio Output 1 Bit Clock (Input/Output) - Serial bit clock for audio data on the SDOUT1 pin. OLRCK1 29 Serial Audio Output 1 Left/Right Clock (Input/Output) - Word rate clock for the audio data on the SDOUT1 pin. SRC_UNLOCK 30 SRC Unlock Indicator (Output) - Indicates when the SRC is unlocked. See “SRC Locking” on page 37 for more details. RMCK 31 Recovered Master Clock (Output) - Recovered master clock from the PLL. Frequency is 128 x, 256 x, or 512 x Fs, where Fs is the sample rate of the incoming AES3-compatible data or ISCLK/64. If a 20 kΩ pull-up to VL is present on this pin, the SDOUT2 MCLK source will be RMCK, otherwise it will be the clock input through XTI-XTO. RST 32 Reset (Input) - When RST is low the CS8422 enters a low power mode and all internal states are reset. On initial power up RST must be held low until the power supply is stable and all input clocks are stable in frequency and phase. THERMAL PAD - Thermal Pad - Thermal relief pad. Should be connected to the ground plane for optimized heat dissi- pation. Pin Name Pin # Pin Description

1. CHARACTERISTICS AND SPECIFICATIONS (All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical per- formance characteristics and specifications are derived from measurements taken at nominal supply voltages and TA = 25° C.) RECOMMENDED OPERATING CONDITIONS GND = 0 V, all voltages with respect to 0 V. ABSOLUTE MAXIMUM RATINGS DGND = AGND = 0 V; all voltages with respect to 0 V. Operation beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. Notes: 1. Transient currents of up to 100 mA will not cause SCR latch-up. Parameter Symbol Min Nominal Max Units Power Supply Voltage VL VA V_REG 1.71 3.135 3.135 3.3 3.30 3.30 5.25 3.465 3.465 V V V Ambient Operating Temperature: Commercial Grade Automotive Grade T A -40 -40 +85 +105 Parameter Symbol Min Max Units Power Supply Voltage VL VA V_REG -0.3 -0.3 -0.3 6.0 4.3 4.3 V V V Input Current, Any Pin Except Supplies (Note 1) I in -± 1 0 m A Input Voltage, Any Pin Except RXP[1:0], RXN[1:0], or RX[3:0] Vin -0.3 VL+0.4 V Input Voltage, RXP[1:0], RXN[1:0], or RX[3:0] V in -0.3 VA+0.4 V Ambient Operating Temperature (power applied) T A -55 +125 °C Storage Temperature T stg -65 +150 °C

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PERFORMANCE SPECIFICATIONS - SAMPLE RATE CONVERTER XTI-XTO = 24.576 MHz; Input signal = 1.000 kHz, Measurement Bandwidth = 20 to Fso/2 Hz, and Word Width = 24-Bits. (Note 2) Notes: 2. Fsi indicates the input sample rate . Fso indicates the output sample rate. Numbers separated by a colon indicate the ratio of Fsi to Fso. DIGITAL FILTER CHARACTERISTICS Parameter Min Typ Max Units Resolution 16 - 24 bits Sample Rate Slave Master XTI/2048 XTI/512 XTI/128 XTI/128 kHz kHz Sample Rate Ratio - Upsampling - - 1:6 Fsi:Fso Sample Rate Ratio - Downsampling - - 6:1 Fsi:Fso Interchannel Gain Mismatch - 0.0 - dB Interchannel Phase Deviation - 0.0 - Degrees Gain Error -0.2 - 0 dB Peak Idle Channel Noise Component - - -144 dBFS Dynamic Range - Unweighted (20 Hz to Fso/2, -60 dBFS Input) 32 kHz:48 kHz - 140 - dB 44.1 kHz:48 kHz - 141 - dB 44.1 kHz:192 kHz - 138 - dB 48 kHz:44.1 kHz - 140 - dB 48 kHz:96 kHz - 141 - dB 96 kHz:48 kHz - 140 - dB 1 9 2k H z : 3 2k H z - 1 4 1 - d B Total Harmonic Distortion + Noise (20 Hz to Fso/2, 0 dBFS Input) 32 kHz:48 kHz - -134 - dB 44.1 kHz:48 kHz - -134 - dB 44.1 kHz:192 kHz - -133 - dB 48 kHz:44.1 kHz - -131 - dB 48 kHz:96 kHz - -135 - dB 96 kHz:48 kHz - -136 - dB 1 9 2k H z : 3 2k H z - - 1 3 7 - d B Parameter Min Typ Max Units Passband (Upsampling or Downsampling) -- 0.4535* min(Fsi,Fso) Fs Passband Ripple - - ± 0.05 dB Stopband (Downsampling) 0.5465*Fso --F s Stopband Attenuation 125 - - dB Group Delay See “Group Delay” on page 69

DC ELECTRICAL CHARACTERISTICS AGND = DGND = 0 V; all voltages with respect to 0 V. Notes: 3. Power-Down Mode is defined as RST = LOW with all clocks and data lines held static and no crystal attached across XTI - XTO. 4. Normal operation is defined as RST = HIGH. The typical values shown were measured with the digital interface receiver in differential mode, serial au dio output port 1 in master mode sourced by the SRC, and serial audio output port 2 in master mode sourced by the AES3 receiver output. Parameter Min Typ Max Units Power-Down Mode (Note 3) Supply Current in power down VA V_REG VL = 1.8 V VL = 2.5 V VL = 3.3 V VL = 5.0 V 4.7 0.3 7.1 16.9 102.6 µA µA µA µA µA µA Normal Operation (Note 4) Supply Current at 48 kHz Fsi and Fso VA V_REG VL = 1.8 V VL = 2.5 V VL = 3.3 V VL = 5.0 V 7.6 9.4 2.7 3.8 5.2 mA mA mA mA mA mA Supply Current at 192 kHz Fsi and Fso VA V_REG VL = 1.8 V VL = 2.5 V VL = 3.3 V VL = 5.0 V 32.4 18.9 6.2 8.8 50.4 mA mA mA mA mA mA

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DIGITAL INTERFACE SPECIFICATIONS AGND = DGND = 0 V; all voltages with respect to 0 V. Notes: 5. When a digital signal is sent to the AES RX pins, the pins will draw approximately 730 µA from the digital signal’s supply from the time reset is de-asserted until the RX_MODE, RX_SEL, and INPUT_TYPE bits in register 03h are properly configured to allow a digital input signal on the driven pins, see Section 11.3 on page 48. 6. Maximum sensitivity in accord ance with AES3-2003 section 8.3.3. Measured with eye diagram height at the specified voltage and width of at least 50% of one-half the biphase symbol period. Parameter Symbol Min Typ Max Units Input Leakage Current (Note 5) Iin -- + 3 2 μA Input Capacitance I in -8 - p F Digital Interface Receiver - RXP[1:0], RXN[1:0], RX[3:0] Differential Input Sensitivity, RXP to RXN (Note 6) -- 2 0 0 m V p p Differential Input Impedance, RXP and RXN to GND - 11 - k Ω Single-Ended Input Sensitivity, RX pins, Receiver Input Mode 1 (Note 6) -- 2 0 0 m V p p Single-Ended Input Impedance, RX pins, Receiver Input Mode 1 - 11 - k Ω High-Level Input Voltage, RX pins in Digital mode V IH 0.55xVA - VA+0.3 V Low-Level Input Voltage, RX pins in Digital mode V IL -0.3 - 0.8 V Digital I/O High-Level Output Voltage (IOH = -4 mA) VOH .77xVL - -V Low-Level Output Voltage (IOL = 4 mA) VOL - - 0.6 V High-Level Input Voltage V IH 0.65xVL - -V Low-Level Input Voltage V IL - - 0.3xVL V Input Hysteresis - 0.2 - V

Inputs: Logic 0 = 0 V, Logic 1 = VL; CL = 20 pF. Parameter Symbol Min Typ Max Units RST pin Low Pulse Width (Note 7) 1-- m s PLL Clock Recovery Sample Rate Range (Note 8) 28 - 216 kHz RMCK Output Jitter (Note 9) Differential RX Mode Single-Ended RX Mode 200 475 ps RMS ps RMS RMCK Output Duty Cycle 45 50 55 % XTI Frequency Crystal 12 - 27.000 MHz Digital Clock Source 1.024 - 49.152 MHz XTI Pulse Width High/Low 9-- n s MCLK_OUT Duty Cycle 45 - 55 % V L = 3 . 3V , 5V RMCK Output Frequency - - 49.152 MHz MCLK_OUT Frequency - - 49.152 MHz Slave Mode ISCLK Frequency - - 49.152 MHz ISCLK High Time tsckh 9.2 - - ns ISCLK Low Time tsckl 9.2 - - ns OSCLK Frequency -- 2 6 . 9 M H z OSCLK High Time tsckh 16.7 - - ns OSCLK Low Time tsckl 16.7 - - ns I/OLRCK Edge to I/OSCLK Rising Edge tlcks 5.7 - - ns I/OSCLK Rising Edge to I/OLRCK Edge tlckd 4.2 - - ns OSCLK Falling Edge/OLRCK Edge to SDOUT Output Valid tdpd -- 1 3 . 7 n s SDIN/TDM_IN Setup Time Before I/OSCLK Rising Edge tds 2.2 - - ns SDIN/TDM_IN Hold Time After I/OSCLK Rising Edge tdh 5.5 - - ns TDM Mode OLRCK High Time (Note 10) tlrckh 20 - - ns TDM Mode OLRCK Rising Edge to OSCLK Rising Edge tfss 5.3 - - ns TDM Mode OSCLK Rising Edge to OLRCK Falling Edge tfsh 4.2 - - ns Master Mode I/OSCLK Frequency (non-TDM Mode) 48*Fsi/o - 128*Fsi/o MHz I/OLRCK Duty Cycle 49.5 - 50.5 % I/OSCLK Duty Cycle 45 - 55 % I/OSCLK Falling Edge to I/OLRCK Edge t lcks -- 4 . 2 n s OSCLK Falling Edge to SDOUT Output Valid t dpd -- 4 . 6 n s

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Notes: 7. After powering up the CS8422, RST should be held low until the power supplies and clocks are settled. 8. If ISCLK is selected as the clock source fo r the PLL, then the Sample Rate = ISCLK/64. SDIN/TDM_IN Setup Time Before I/OSCLK Rising Edge tds 2.2 - - ns SDIN/TDM_IN Hold Time After I/OSCLK Rising Edge tdh 5.5 - - ns TDM Mode OSCLK Frequency (Note 11) - - 49.152 MHz TDM Mode OSCLK Falling Edge to OLRCK Edge t fsm -- 4 . 2 n s VL = 1.8 V, 2.5 V RMCK Output Frequency -- 3 1 M H z MCLK_OUT Frequency -- 3 1 M H z Slave Mode ISCLK Frequency - - 49.152 MHz ISCLK High Time tsckh 9.2 - - ns ISCLK Low Time tsckl 9.2 - - ns OSCLK Frequency -- 1 5 . 7 M H z OSCLK High Time tsckh 28.7 - - ns OSCLK Low Time tsckl 28.7 - - ns I/OLRCK Edge to I/OSCLK Rising Edge tlcks 7.4 - - ns I/OSCLK Rising Edge to I/OLRCK Edge tlckd 6.2 - - ns OSCLK Falling Edge/OLRCK Edge to SDOUT Output Valid tdpd -- 2 5 . 6 n s SDIN/TDM_IN Setup Time Before I/OSCLK Rising Edge tds 4.7 - - ns SDIN/TDM_IN Hold Time After I/OSCLK Rising Edge tdh 7.3 - - ns TDM Mode OLRCK High Time (Note 10) tlrckh 20 - - ns TDM Mode OLRCK Rising Edge to OSCLK Rising Edge tfss 7.0 - - ns TDM Mode OSCLK Rising Edge to OLRCK Falling Edge tfsh 6.2 - - ns Master Mode I/OSCLK Frequency (non-TDM Mode) 48*Fsi/o - 128*Fsi/o MHz I/OLRCK Duty Cycle 45 - 55 % I/OSCLK Duty Cycle 45 - 55 % I/OSCLK Falling Edge to I/OLRCK Edge t lcks -- 5 . 7 n s OSCLK Falling Edge to SDOUT Output Valid t dpd -- 5 . 4 n s SDIN/TDM_IN Setup Time Before I/OSCLK Rising Edge tds 4.7 - - ns SDIN/TDM_IN Hold Time After I/OSCLK Rising Edge tdh 7.3 - - ns TDM Mode OSCLK Frequency (Note 11) -- 3 1 M H z TDM Mode OSCLK Falling Edge to OLRCK Edge t fsm -- 5 . 7 n s Parameter Symbol Min Typ Max Units

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Inputs: Logic 0 = 0 V, Logic 1 = VL; CL = 20 pF.

1. t spi only needed before first falling edge of CS after RST rising edge. tspi = 0 at all other times.
2. Data must be held for sufficient time to bridge the transition time of CCLK.
3. CDOUT should not be sampled during this time.

Figure 5. SPI Mode Timing

Inputs: Logic 0 = 0 V, Logic 1 = VL; CL = 20 pF.

1. Data must be held for sufficient ti me to bridge the transition time, tfc, of SCL.

Figure 6. I²C Mode Timing

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1. TYPICAL CONNECTION DIAGRAMS

3.1 Software Mode

Figure 7. Typical Connection Diagram, Software Mode See section 12.3 for details.

3.2 Hardware Mode

Figure 8. Typical Connection Diagram, Hardware Mode See section 12.3 for details.

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1. OVERVIEW The CS8422 is a 24-bit, high performance, monolithic CMOS stereo asynchronous sample rate converter with inte- grated digital audio interface receiv er that decodes audio data according to EIAJ CP1201, IEC-60958, AES3, and S/PDIF interface standards. Audio data is input through either a 3-wire serial audio port or the AES3-compatible digital interface receiver. Audio data is output through one of two 3-wire serial audio output ports. The serial audio ports are capable of 24-, 20-, 18- , or 16-bit word lengths. Data in to the digital interface receiver can be up to 24-bit. Input and output data can be completely asynchronous, synchronous to an external dat a clock through XTI, or synchronous to the master clock recovered from the incoming S/PDIF or AES3 data. CS8422 can be controlled either in Software Mode or in a stand-alone Hardware Mode. In Software Mode, the user can control the device through either a SPI or I²C control port. Target applications include digital recording systems (DVD-R/RW, CD-R/RW, PVR, DAT, MD, and VTR), digital mix- ing consoles, high quality D/A, effects processors, computer audio systems, and automotive audio systems. Figure 7 and Figure 8 show typical connections to the CS8422. 5. THREE-WIRE SERIAL IN PUT/OUTPUT AUDIO PORT The CS8422 provides two independent 3-wire serial audio output ports, and a 3-wire serial audio input (only avail- able in Software Mode). The interface format should be chosen to suit the attached device either through the control port in Software Mode, or through the MS_SEL and SAOF pins in Hardware Mode. The following parameters are adjustable: Hardware Mode

• Master or slave mode operation
• Master-mode MCLK-to-OLRCK (OLRCK1 and OLRCK2) ratios: 128, 256, and 512
• Audio data resolution of 16, 20, or 24 bits
• Left-justified, I²S, or Righ t-justified serial data formats
• Multi-channel TDM serial audio format (Serial Audio Output 1 only) Software Mode
• Master or slave mode operation
• Master-mode MCLK-to-ILRCK and MCLK-to-OLRCK (OLRCK1 and OLRCK2) ratios: 64, 128, 192, 256, 384, 512, 768, and 1024
• Audio data resolution of 16, 18, 20, or 24 bits
• Left-justified, I²S, or Righ t-justified serial data formats
• Multi-channel TDM serial audio format
• AES3 Direct Output format Figures 9, 10, 11, and 12 show the standard input/output formats ava ilable. The TDM serial audio format is de- scribed in Section 5.1.5 on page 27. For more information about serial audio formats, refer to the Cirrus Logic ap- plications note AN282, “The 2-Channel Serial Audio Interface: A Tutorial”, available at www.cirrus.com

5.1 Serial Port Clock Operation

5.1.1 Master Mode

When a serial port is set to master mode, its left/right clock (ILRCK, OLRCK1, or OLRCK2), and its serial bit-clock (ISCLK, OSCLK1, or OSCLK2) are outputs. If a serial output is sourced directly by the AES3 re- ceiver, then that serial port’s left/right clock and serial bit-clock will be synchronous with RMCK. If a serial port is routed to or from the sample rate converter (SRC), then that serial port’s left/right clock and serial bit-clock can be synchronous with either the XTI-XTO or RMCK when it is in master mode. If a serial output is source directly by the serial input port without the use of the SRC, then all associated clocks must be synchronous, so both serial ports must use the same master clock source. It is for this reason that, when in this mode, the serial output clock control is done through the Serial Audio Input Clock Control (07h) register.

5.1.2 Slave Mode

When a serial port is in slave mode, its left/right clock (ILRCK, OLRCK1, or OLRCK2), and its serial bit- clock (ISCLK, OSCLK1, or OSCLK2) are inputs. If the serial input or a serial output has the SRC in its data path, then the serial port’s LRCK and SCLK may be asynchronous to all other serial ports. The left/right clock should be continuous, but the duty cycle can be less than 50% if enough serial clocks are present in each associated LRCK phase to clock all of the data bits. If there are fewer SCLK periods than required to clock all the bits present in one half LRCK period in Left- Justified and I²S Modes, data will be truncated beginning with the LSB. In Right-Justified Modes, the data will be invalid. If a serial audio output is operated in slave mode and sourced directly by the AES3 receiver or the serial input port without the use of the sample rate converter, then the OLRCK supplied to the serial audio output should be synchronous to Fsi or ILRCK to avoid skipped or repeated samples. The OSLIP bit ( “Interrupt Status (14h)” on page 59) is provided to indicate when skipped or repeated samples occur. If the input sample rate, Fsi or ILRCK, is greater than the slave-mode OLRCK frequency, then dropped samples will occur. If Fsi or ILRCK is less than the slave-mode OLRCK frequency, then samples will be repeated. In either case the OSLIP bit will be set to 1 and will not be cleared until read through the control port.

5.1.3 Hardware Mode Control

In Hardware Mode, the serial audio input port is not available. SDOUT1 is the serial data output from the sample rate converter, and SDOUT2 is the serial audio output directly from the AES3-compatible receiver. Because there is no serial audio input available in Hardware Mode, all audio data input is done through the AES3-compatible receiver. In Hardware Mode, the serial output ports are controlled through the SAOF and MS_SEL pins. See “Hardware Mode Serial Audio Port Control” on page 40 for more details. In Hardware Mode, there are always 64 SCLK periods per LRCK period when a serial port is set to master mode.

5.1.4 Software Mode Control

In Software Mode, the CS8422 provides a serial audio input port and two serial audio output ports. Each serial port’s clocking and data routing options are fully configurable as shown in Serial Audio Input Data Format (0Bh), Serial Audio Output Data Format - SDOUT1 (0Ch) , and Serial Audio Output Data Format - SDOUT2 (0Dh) registers, found on pages 53, 54, and 55.

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Figure 9. Serial Audio Interface Format – I²S Figure 10. Serial Audio Interface Format – Left-Justified Figure 11. Serial Audio Interface Format – Right-Justified (Master Mode only) Figure 12. Serial Audio Interface Format – AES3 Direct Output

5.1.5 Time Division Multiplexing (TDM) Mode

TDM Mode allows several TDM-compat ible devices to be serially connected together allowing their cor- responding serial output data to be multiplexed onto one line for input into a DSP or other TDM capable input device. In TDM Mode, the TDM_IN pin is used to input TDM-formatted data while the SDOUT1 or SDOUT2 (Soft- ware Mode only) pin is used to output TDM data. If the CS8422 is the first TDM device in the chain, it should have its TDM_IN connected to GND. Data is transmitted from SDOUTx (SDOUT1 or SDOUT2) most significant bit first on the first falling OSCLKx edge after an OLRCKx rising edge and is valid on the rising edge of OSCLKx.

5.1.5.1 TDM Master Mode

In TDM master mode, OSCLKx frequency is fixe d at 256*OLRCKx (where x = 1 or x = 2 depending on which serial output port is selected as being in TDM Mode). Each sample time slot is 32 bit-clock periods long; providing 8 channels of digital audio multiplexed together, with the first two channels being supplied by the CS8422 which has been placed in master mode. An OSCLKx-wide OLRCKx pulse identifies the start of a new frame, with the valid data sample beginning one OSCLKx after the OLRCKx rising edge. In TDM master mode, the master clock source for the TDM serial port must be 256, 512, or 1024*Fso. Valid data lengths are 16, 18, 20, or 24 bits. Figure 13 shows the interface format for TDM master mode.

5.1.5.2 TDM Slave Mode

In TDM slave mode, the number of channels that can by multiplexed to one serial data line depends on the output sample rate. For slave mode, OSCLKx mu st operate at N*64*Fso, where N is the number of CS8422’s in the TDM chain. For example, if Fso = 96 kHz, N = 4 (8 channels of serial audio data), OSCLKx frequency must be 24.576 MHz. Note that the maximum OSCLKx frequency in slave mode is a function of the VL supply voltage, as shown in “Switching Specifications” on page 17. Figure 14 shows the interface format for TDM slave mode.

5.1.5.3 Hardware Mode Control

In Hardware Mode, TDM Mode is selected through the SAOF pin. See Section 8.1 on page 40 for more details.

5.1.5.4 Software Mode Control

In Software Mode, TDM Mode is selected through the Serial Audio Output Data Format - SDOUT1 (0Ch) register, found on page 54.

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32 OSCLKs

Figure 13. TDM Master Mode Timing Diagram Figure 14. TDM Slave Mode Timing Diagram Figure 15. TDM Mode Configuration (All CS8422 outputs are slave) Figure 16. TDM Mode Configuration (First CS8422 output is master, all others are slave)

1. DIGITAL INTERFACE RECEIVER The CS8422 includes a digital interface receiver that can receive and decode audio data ac cording to the AES3, IEC60958, S/PDIF, and EIJ CP1201 interface standards. The CS8422 uses either a 4:1 single-ended or 2:1 different ial input mux to select the input pin(s) that will receive input data to be decoded. A low-jitter clock (RMCK) is re covered using a PLL, which provides the digital interface receiver with a master clock. The decoded audio data c an either be routed through the SRC for sample rate con- version, or can be an output on one of two serial audio output ports. The channel status and Q-subcode data portion of the user data are assembled and buffered in Channel Status Registers (23h - 2Ch) and Q-Channel Subcode (19h - 22h), and may be accessed through the control port in either SPI or I²C Mode.

6.1 AES3 and S/PDIF Standards

This document assumes that the user is familiar with the AES3 and S/PDIF data formats. It is advisable to have current copies of the AES3, IEC60958, IEC619 37, and EIJ CP1201 specifications on hand for easy reference. The latest AES3 standard is available from the Audio Engineering Society at www.aes.org. The latest IEC60958/61937 standard is available from th e International Electrotechnical Commission at www.iec.ch. The latest EIAJ CP-1201 standard is avail able from the Japanese Electronics Bureau at www.jei- ta.or.jp/eiaj/. Application Note 22: Overview of Digital Audio Interface Data Structures, available at www.cirrus.com, con- tains a useful tutorial on digital audio specifications, but it should not be considered a substitute for the stan- dards. The paper titled An Understanding and Implementation of the SCMS Serial Copy Management System for Digital Audio Transmission, by Clifton Sanchez, is an excellent tuto rial on SCMS. It is available from the AES as reprint 3518.

6.2 Receiver Input Multiplexer

The CS8422’s receiver input multiplexer allows input of data compatible with AES3, S/PDIF, IEC60958, and EIAJ CP-1201 standards. For information about recommended receiver input circuits, see “External Receiv- er Components” on page 64.

6.2.1 Hardware Mode Control

In Hardware Mode, the receiver input multiplexer is limited to a selection between two differential inputs, RXP0/RXN0 and RXP1/RXN1. The receiver input mult iplexer will decode data present at the differential input selected by the RX_SEL pin. See Section 8. “Hardware Mode Control” on page 39 for more details. Multiplexer inputs are floating when not selected. Unused inputs should be tied to AGND/DGND

6.2.2 Software Mode Control

In Software Mode, CS8422 offers either a 4:1 single-e nded, or a 2:1 differential input multiplexer to ac- commodate switching between up to four channels of AES3 or S/PDIF-compatible data input. In Single- Ended Mode, the CS8422 can switch between four single-ended signals present at RX[3:0]. In differential mode, the CS8422 can switch between two differential signals, present on RXP0/RXN0 and RXP1/RXN1. Multiplexer inputs are floating when not selected. Unused inputs should be tied to AGND/DGND In Software Mode, the receiver input multiplexer is controlled through the register described in Section 11.3 “Receiver Input Control (03h)” on page 48.

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6.2.2.1 Single-Ended Input Mode

tween operation as comparator inputs or digital inputs. the AC coupling capacitors are C0G or X7R. receiver in Single-Ended Mode. Figure 17. Single-Ended Receiver Input Structure, Receiver Mode 1 (as with the use of a typical optical receiver output). ifications” on page 17 for more details).

6.2.2.2 Differential Input Mode

of the receiver in differential mode.

1. If RX[3:0] is selected by either the rece iver MUX or the TX pass-through MUX, N=1.
2. If RX[3:0] is selected by both the receiv er MUX and the TX pass-through MUX, N=2.
3. If RX[3:0] is not selected at all, N=0 (i.e. high impedance).

Figure 18. Differential Receiver Input Structure

6.3 Recovered Master Clock - RMCK

pin. In addition, the user can set the RMCK as the master clock of either of the two remaining serial ports.

6.3.1 Hardware Mode Control

6.3.2 Software Mode Control

6.4 XTI System Clock Mode

1. If RXP/N[1:0] is selected by either the receiver MUX or the TX pass-through MUX, N=1.
2. If RXP/N[1:0] is selected by both the re ceiver MUX and the TX pass-through MUX, N=2.
3. If RXP/N[1:0] is not selected at all, N=0 (i.e. high impedance).

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frequencies will be derived from the XTI-XTO clock wh en clock switching has taken place and the RMCK- to-LRCK ratio will be maintained. When clock switching is not enabled and the PLL has lost lock, RMCK will be derived from the VCO idle frequency. The frequency of the RMCK output will be still be determined by the ratio selected by the RM- CK[2:0] bits in register 09h, or the MS_SEL pin in Hardware Mode. When the PLL has lost lock, the VCO idle frequency is equivalent to AES3 input data with Fs ≅ 54 kHz ± 5% (or ISCLK ≅ 3.456 MHz ± 5%).

6.4.1 Hardware Mode Control

In Hardware Mode, XTI System Clock Mode is always enabled.

6.4.2 Software Mode Control

In Software Mode, XTI System Clock Mode is controlled through the register described in Section 11.2 “Clock Control (02h)” on page 47.

6.5 AES11 Behavior

When an AES3-derived OLRCK is configured as a master, the rising or falling edge of OLRCK (depending on the serial port interface format setting) will be within -1.5%(1/Fs) to 1.5%(1/Fs) from the start of the pre- amble X/Z. In master mode, the latency through t he receiver depends on the input sample frequency. In master mode the latency of the audio data will be 3 frames in AES3 direct mode, and 4 frames in all other cases. When an AES3-derived OLRCK is configured as a slave, any synchronized input within +/-25% of an AES3 frame from the positive or negative edge of OLRCK (d epending on the serial port interface format setting) will be treated as being sampled at the same time. Since the CS8422 has no control of the OLRCK in slave mode, the latency of the data through the part will be a multiple of 1/Fs plus the intrinsic delay between OL- RCK and the preambles also present in master mode. Both of these conditions are within the tolerance range set forth in the AES11 standard.

6.6 Error and Status Reporting

While decoding the incoming bi-phase encoded data stream, the CS8422 has the ability to identify various

6.6.1 Software Mode

Software Mode allows the most flex ibility in reading errors. When unma sked, bits in the Receiver Error register (0Ch) indicate the following errors: 1. QCRC – CRC error in Q subcode data. 2. CCRC – CRC error in channel status data. 3. UNLOCK – PLL is not locked to incoming bi-phase data stream, or 2 valid Z preambles have not yet been detected. 4. V – Data Validity bit is set. 5. CONF – The input data stream may be near error condition due to jitter degradation. 6. BIP – Bi-phase encoding error. 7. PAR – Parity error in incoming data.

The error bits are “sticky”, meaning that they are set on the first occurrence of the associated error and will remain set until the user reads the register through the control port. This enables the register to log all unmasked errors that occurred since the last time the register was read. As a result of the bits “stickiness”, it is necessary to perform two reads on these registers to see if the error condition still exists. The Receiver Error Mask register (0Eh) allows masking of individual errors. The bits in this register default to 00h and serve as masks for the corresponding bits of the Receiver Error register. If a mask bit is set to 1, the error is unmasked, which implies the following: its occurrence will be reported in the receiver error register, induce a pulse on RERR, invoke the occurrence of a RERR interrupt, and affect the current audio sample according to the status of the HOLD bits. The exceptions are the QCRC and CCRC errors, which do not affect the current audio sample, even if unmasked. The HOLD bits allow a choice of: – Holding the previous sample – Replacing the current sample with zero (mute) – Not changing the current audio sample For more details, refer to “Receiver Error Unmasking (0Eh)” on page 56, “Interrupt Unmasking (0Fh)” on page 56, “Interrupt Mode (10h)” on page 57, “Receiver Error (13h)” on page 58, and “Interrupt Status (14h)” on page 59.

6.6.2 Hardware Mode Control

In Hardware Mode, the user may choose to output either the Non-Validity Receiver Error (NVERR) or the Receiver Error (RERR) on the NV/RERR pin. By default the pin will output the NRERR signal. If upon star- tup a 20 kΩ resistor is connected between the pin and VL, the NV/RERR pin will output the RERR error signal. Both RERR and NVERR are updated on AES3 subframe boundaries. See “Hardware Mode Con- trol” on page 39 for more details. NVERR – The previous audio sample is held and passed to the serial audio output port if a parity, bi- phase, confidence or PLL lock error occurs during the current sample. RERR – The previous audio sample is held and passed to the serial audio output port if the validity bit is high, or a parity, bi-phase, confidence or PLL lock error occurs during the current sample.

6.7 Non-Audio Detection

An AES3 data stream may be used to convey non-audio data, thus it is important to know whether the in- coming AES3 data stream is digital audio or not. This information is typically conveyed in channel status bit 1, which is extracted automatically by the CS8422. However, certain non-audio sources, such as AC-3® or MPEG encoders, may not adhere to this convention and the bit may not be properly set. The CS8422 AES3 receiver can detect such non-audio data through the use of an auto-detect module. The auto-detect module is similar to auto-detect software used in Cirrus Logic DSPs. If the AES3 stream contains sync codes in the proper format for IEC61937 or DTS® data transmission, an internal AUTODETECT signal will be asserted. If the sync codes no longer appear after a certain amount of time, auto-detection will time-out and AUTODETECT will be de-asserted until another format is detected. The AUDIO signal is the logical OR of AUTODETECT and the received channel status bit 1. In Software Mode AUDIO is available through the GPO pins. If no n-audio data is detected, the data is still processed exactly as if it were no rmal audio. The exception is the use of de-emphasis auto-select feature which will bypass the de-emphasis filter if the input stream is detected to be non-audio. It is up to the user to mute the outputs as required.

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6.7.1 Hardware Mode Control

In Hardware Mode, AUDIO is output on the V/AUDIO pin when a 20 k Ω resistor is connected from the V/AUDIO pin to VL.

6.7.2 Software Mode Control

In Software Mode, the AUDIO signal is available through the GPO pins. See “GPO Control 1 (05h)” on page 50 for more details.

6.8 Format Detection (Software Mode Only)

In Software Mode, the CS8422 can automatically detect various serial audio input formats. The Format De- tect Status register (12h) is used to indicate a de tected format. The register will indicate if uncompressed PCM data, IEC61937 data, DTS_LD data, DTS_CD data, or digital silence was detected. Additionally, the IEC61937 Pc/Pd burst preambles are available in registers 2Dh-30h. See the register descriptions for more information.

6.9 Interrupts (Software Mode Only)

The INT signal, available in Software Mode, indicates when an interrupt condition has occurred and may be output on one of the GPOs. It can be set through bits INT[1:0] in the Control1 register (02h) to be active low, active high, or open-drain active low. This last mode is used for active low, wired-OR hook-ups, with multiple peripherals connected to the microcontroller interrupt input pin. Many conditions can cause an interrupt, as listed in t he interrupt status register descriptions. Each source may be masked off through mask register bits. In addition, some sources may be set to rising edge, falling edge, or level sensitive. Combined with the option of level sensitive or edge sensitive modes within the mi- crocontroller, many different configurations are possible, depending on the needs of the equipment design- er. Refer to the register descriptions for the Interrupt Unmasking (0Fh), Interrupt Mode (10h), and Interrupt Status (14h) registers

6.10 Channel Status and User Data Handling

“Channel Status Buffer Management” on page 66 describes the overall handling of Channel Status and User data.

6.10.1 Hardware Mode Control

In Hardware Mode, Received Channel Status (C), and User (U) bits are output on the C and TX/U pins (U data output must be selected on the TX/U pin, see “Hardware Mode Control” on page 39 for details). OLRCK2 and RCBL are made available to qualify the C and U data output. Figure 19 illustrates timing of the C and U data and their related signals.

6.10.2 Software Mode Control

In Software Mode, several options are available for accessing the Channel Status and User data that is encoded in the received AES3 or SPDIF data. The first option allows access directly through registers. The first 5 bytes of the Channel Status block are decoded into the “Channel Status Registers (23h - 2Ch)”. Registers 23h-27h contain the A channel status data. Registers 28h-2Ch contain the B channel status data. Received Channel Status (C), User (U), and EMPH bits may also be serial outputs to the GPO pins by appropriately setting the GPOxSEL bits in the “GPO Control 1 (05h)” registers. OLRCK and RCBL can be

by the AES3 receiver (not the SRC). used to clock the recovered receiver data. are sourced from the SRC, then VLRCK will equal the recovered AES frame rate, not OLRCK. serial port in question is directly sourced by the AES3 receiver (not the SRC). and presented in 10 consecutive register locations located in “Q-Channel Subcode (19h - 22h)” register. through the “Interrupt Status (14h)” register. Table 1. VLRCK Behavior

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192 AES3 Frames

Figure 19. C/U Data Outputs

1. RCBL will go high on the transition of the first output C/U data bit (C/U[0]) and will remain high until the C/U[0] - C/U[1] transition.
2. VLRCK is a virtual word clock that is available through the GPO pins, and can be used to frame the C/U output.
3. VLRCK frequency is always equal to the incoming frame rate of the AES3-compatible data. If there are an even number of OSCLK

periods per OLRCK, then the VLRCK duty cycle is 50%, otherwise it is 50% ± one OSCLK period.

1. If a serial audio output port is sourced direct ly by the AES3-compatible receiver VLRCK = OLRCK in I²S Mode, and

VLRCK = OLRCK in left-justified and Right-Justified Modes.

1. If a serial port is sourced directly by the AES3-compatible receiver, the data will transition on the fourth OSCLK falling edge after a

VLRCK edge and will be valid on VLRCK edges (t = 4 OSCLK period).

1. If a serial port is not sourced directly by the AES3-compatible receiver (as in a sample rate conversion application), the da ta will

transition 1/64*Fsi after a VLRCK edge, and will be valid on VLRCK edges (t = 1/64*Fsi).

1. SAMPLE RATE CONVERTER (SRC) Multirate digital signal processing techniques are used to conceptually upsample the incoming data to a very high rate and then downsample to the outgoing rate. Internal filtering is designed so that a full input audio bandwidth of 20 kHz is preserved if the input sample and output sample rates are greater than or equal to 44.1 kHz. When the output sample rate becomes less than the input sample rate, the input is automatically band limited to avoid aliasing artifacts in the output signal. Any jitter in the incoming signal has little impact on the dynamic performance of the rate converter and has no influence on the output clock.

7.1 SRC Data Resolution and Dither

When using the serial audio input port in left justified and I²S Modes, all input data is treated as 24-bits wide. Any truncation that has been done prior to the CS8422 to less than 24-bits should have been done using an appropriate dithering process. If the serial audio input port is in Right-Justified Mode, the input data will be truncated to the bit depth set through the “Serial Audio Input Data Format (0Bh)” register. If the bit depth is set to 16 bits, and the input data is 24-bits wide, then truncation distortion will occur. Similarly, in any serial audio input port mode, if an inadequate number of bit clocks are entered (i.e. 16 clocks instead of 20 clocks), then the input words will be truncate d, causing truncation distortion at low levels. In summary, there is no dithering mechanism on the input side of the CS8422, and care must be taken to ensure that no truncation occurs. The output side of the SRC can be set to 16, 18, 20, or 24. Dithering is applied and is automatically scaled to the selected output word length. This dither is not correlated between left and right channel.

7.1.1 Hardware Mode Control

In Hardware Mode, the SRC is the da ta source for SDOUT1, and its serial output port data resolution is controlled through the SAOF pin. See Section 8.1 on page 40 for more details.

7.1.2 Software Mode Control

In Software Mode, the serial port data resolution is controlled through the “Serial Audio Input Data Format (0Bh)”, “Serial Audio Output Data Format - SDOUT1 (0Ch)” , and “Serial Audio Output Data Format - SDOUT2 (0Dh)” registers.

7.2 SRC Locking

The SRC calculates the ratio between the input sample rate and the output sample rate, and uses this in- formation to set up various parameters inside the S RC block. The SRC takes some time to make this cal- culation (approximately ~100 ms when Fso = 48 kHz). The SRC_UNLOCK signal is used to indicate when the SRC is not locked. When RST is asserted, or if there is a change in Fsi or Fso, SRC_UNLOCK will be set high. The SRC_UNLOCK pin will continue to be high until the SRC has reacquired lock and settled, at which point it will transition low. When the SRC_UNLOCK pin is set low, SDOUT is outputting valid audio data. This can be used to signal a DAC to unmute its output. The SRC_UNLOCK signal is available through the control port register 15h, or through the SRC_UNLOCK pin in Hardware Mode.

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7.3 SRC Muting

the SRC becomes valid, SDOUT will be unmuted over a period of approximately 4096/Fso (soft unmuted). all invalid states have been cleared, the SRC will soft unmute SDOUT.

7.4 SRC Master Clock

lator, XTO should be left unconnected or pulled low through a 20 kΩ resistor to GND. tion of how the SRC MCLK can be selected. Table 2. PLL Clock Ratios Figure 20. Typical Connection Diagram for Crystal Circuit

7.4.1 Hardware Mode Control

clock as the SRC MCLK source by connecting a 20 kΩ pull-up resistor between MCLK_OUT and VL.

7.4.2 Software Mode Control

Clock Control (08h)” on page 51 for more details. Figure 21. The part will be in Hardware Mode if there is a 20 k Ω pull-up resistor connected between the C pin and (TX_SEL and RX_SEL) can be changed during operation whereas pull-up resistor controls are sensed on startup. Figure 21. Hardware Mode Clock Routing

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Table 3. Hardware Mode Control Settings

8.1 Hardware Mode Serial Audio Port Control

are stable, SRC_UNLOCK will be brought low when audio output is valid and normal operation will begin. GND to minimize noise. Table 4 and Table 5 show the pin functions and their corresponding settings. serial format). For a more detailed description of serial formats, refer to Section 5. on page 24.

Table 4. Hardware Mode Serial Audio Format Control Table 5. Hardware Mode Serial Audio Port Clock Control

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9.1 Control Port Description

remain static if no operation is required. selecting the desired AD0 bit address state.

9.1.1 SPI Mode

line to the microcontroller. Data is clocked in on the rising edge of CCLK and out on the falling edge. the Hi-Z state. It may be externally pulled high or low with a 20 kΩ resistor, if desired. data for successive registers will appear consecutively. Figure 22. Control Port Timing in SPI Mode

9.1.2 I²C Mode

In I²C Mode, SDA is a bidirectional da ta line. Data is clocked into and out of the part by the clock, SCL. AD2 = 0). The states of the pins are sensed while the CS8422 is being reset. after a Start condition consists of a 7-bit chip address field and a R/W bit (high for a read, low for a write). The upper 4 bits of the 7-bit address field are fixed at 0010. Note that the read operation can not set the MAP so an aborted write operation is used as a preamble.

9.1.3 Memory Address Pointer (MAP)

port read or write. If INC = 0, MAP[6:0] will not automatically increment after each control port read or write. Figure 23. Control Port Timing, I²C Slave Mode Write Figure 24. Control Port Timing, I²C Slave Mode Read

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This table shows the register names and default values for read-write registers. Table 6. Summary of Software Register Bits

1 FS_XT15 FS_XT14 FS_XT13 FS_XT12 FS_XT11 FS_XT10 FS_XT9 FS_XT8

2 FS_XT7 FS_XT6 FS_XT5 FS_XT4 FS_XT3 FS_XT2 FS_XT1 FS_XT0

Table 6. Summary of Software Register Bits (Continued)

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11.SOFTWARE REGISTER BIT DEFINITIONS The table row beneath the row that contains the register-bit name shows the register bit default value. Bits labeled ‘Reserved’ must remain at their default value. 11.1 CS8422 I.D. and Version Register (01h) ID[4:0] - ID code for the CS8422. Permanently set to 00010 REV[2:0] = 000 (revision A) REV[2:0] = 010 (revision B1)

11.2 Clock Control (02h)

PDN - Controls the internal clocks, allowing the CS8422 to be placed in a “powered down”, low current con- sumption state. This bit must be written to the 0 state to allow the CS8422 to begin operation. All input clocks should be stable in frequency and phase when PDN is set to 0. 0- Normal part operation. 1- Internal clocks are stopped. Internal state machines are reset. The fully static control port is operational, allowing registers to be read or changed. Power consumption is low. FSWCLK – Forces the clock signal on XTI to be output on RMCK regardless of the SWCLK bit functionality or PLL lock. 0 – Clock signal on XTI is output on RMCK according to the SWCLK bit functionality. 1 – Forces the clock signal on XTI to be output on RMCK regardless of the SWCLK bit functionality. SWCLK - Outputs XTI clock signal on RMCK pin when PLL loses lock. Any OSCLK or OLRCK derived from RMCK under normal conditions will be derived from XTI in this case. 0 - Disable automatic clock switching. 1 - Enable automatic clock switching on PLL unlock. Clock signal selected on XTI is automatically output on RMCK on PLL Unlock. RMCK_CTL[1:0] - RMCK Control 00 - RMCK is an output and is derived from the frame rate of incoming AES3 data. 01 - RMCK is an output and is derived from the ISCL K input frequency divided by 64. Only valid if serial audio input port is in slave mode (SIMS = 0 in “Serial Audio Input Data Format (0Bh)” on page 53). 10 - RMCK is high-impedance. 11 - Reserved INT[1:0] - Interrupt output pin (INT) control 00 - Active high; high output indicates interrupt condition has occurred. 76543210 ID4 ID3 ID2 ID1 ID0 REV2 REV1 REV0 00010000 76543210 PDN FSWCLK SWCLK RMCK_CTL1 RMCK_CTL0 INT1 INT0 Reserved 10000000

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01 - Active low, low output indicates an interrupt condition has occurred. 10 - Open drain, active low. Requires an external pull-up resistor on the INT pin. 11 - Reserved.

11.3 Receiver Input Control (03h)

RX_MODE - Selects the input mode (single-ended or differential) of the RX pins 0 - Receiver inputs are differential-pair inputs RXP1/RXN1 and RXP0/RXN0. 1 - Receiver inputs are single-ended inputs RX[3:0]. RX_SEL[1:0] – Input multiplexer to the receiver 00 - RX0 or RXP0/RXN0 01 - RX1 (Only valid if RX_MODE = 1) 10 - RX2 or RXP1/RXN1 11 - RX3 (Only valid if RX_MODE = 1) TX_SEL[1:0] – Selects receiver input for GPO TX source 00 - RX0 or RXP0/RXN0 01 - RX1 (Only valid if RX_MODE = 1) 10 - RX2 or RXP1/RXN1 11 - RX3 (Only valid if RX_MODE = 1) INPUT_TYPE – Selects receiver input type 0 - Mode 1, receiver multiplexer inputs are comparator inputs biased at VA/2. 1 - Mode 2, receiver multiplexer inputs are digital inputs, referenced to VA. Valid only if RX_MODE = 1.

11.4 Receiver Data Control (04h)

TRUNC – Determines if the audio word length is set acco rding to the incoming channel status data as de- coded by the AUX[3:0] bits. The resulting word length in bits is 24 minus AUX[3:0]. 0 – Incoming data is not truncated. 1 – Incoming data is truncated according to the length specified in the channel status data. Truncation occurs before the de-emphasis filter. TRUNC has no effect on output data is detected as being non-audio. HOLD[1:0] – Determine how received AES3 audio sample is affected when a receive error occurs 00 - hold last audio sample. 76543210 RX_MODE RXSEL1 RXSEL0 TXSEL1 TXSEL0 INPUT_TYPE Reserved Reserved 00010000 76543210 TRUNC HOLD1 HOLD0 CHS DETCI EMPH_CNTL2 EMPH_CNTL1 EMPH_CNTL0 00000100

01 - replace the current audio sample with all zeros (mute). 10 - do not change the received audio sample. in the channel B Channel Status data. DEM_CNTL[2:0] – De-emphasis filter control. See Figure 25 for De-emphasis filter response. 000 - De-emphasis filter off. be enabled. If data is detected as being non-audio, the de-emphasis filter will not be enabled. Figure 25. De-Emphasis Filter Response

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11.5 GPO Control 1 (05h)

11.6 GPO Control 2 (06h)

11.7 Serial Audio Input Clock Control (07h)

MCLK/LRCK ratio for both serial ports if they are set to master mode. 96KHZ 1001 Defined in “PLL Status (15h)” on page 60. 192KHZ 1010 Defined in “PLL Status (15h)” on page 60. VLRCK 1100 Virtual LRCK, can be used to frame the C and U output data. “Receiver Input Control (03h)” on page 48. Table 7. GPO Pin Configurations

0001 - ILRCK = MCLK/96 0010 - ILRCK = MCLK/128 0011 - ILRCK = MCLK/192 0100 - ILRCK = MCLK/256 0101 - ILRCK = MCLK/384 0110 - ILRCK = MCLK/512 0111 - ILRCK = MCLK/768 1000 - ILRCK = MCLK/1024 SAI_MCLK – Selects the master clock (MCL K) source for the serial audio input when set to master mode (SIMS = 1, as shown in “Serial Audio Input Data Format (0Bh)” on page 53). When set to master, ILRCK and ISCLK are derived from the MCLK selected in this re gister. Note: if either serial audio output port is sourced directly by the serial audio input port, this bit determines the master clock source for the selected serial output port when it is in master mode. 0 - XTI-XTO 1 - RMCK

11.8 SRC Output Serial Po rt Clock Control (08h)

SAO_CLK[3:0] – Valid only for the serial port sourced by the SRC. Selects the serial audio input master clock-to-OLRCK ratio when the serial audio output port is set to master mode (SOMS = 1 as shown in “Serial Audio Output Data Format - SDOUT1 (0Ch)” on page 54 and “Serial Audio Output Data Format - SDOUT2 (0Dh)” on page 55). 0000 - OLRCK = MCLK/64 0001 - OLRCK = MCLK/96 0010 - OLRCK = MCLK/128 0011 - OLRCK = MCLK/192 0100 - OLRCK = MCLK/256 0101 - OLRCK = MCLK/384 0110 - OLRCK = MCLK/512 0111 - OLRCK = MCLK/768 1000 - OLRCK = MCLK/1024 SAO_MCLK – Selects the master clock (MCLK) source fo r the serial audio output, sourced by the SRC, when set to master mode (SOMS1 or SOMS 2 = 1, as shown in “Serial Audio Output Data Format - SDOUT1 (0Ch)” on page 54 and “Serial Audio Output Data Format - SDOUT2 (0Dh)” on page 55). When set to mas- ter, OLRCK and OSCLK are derived from the MCLK selected in this register. 0 - XTI-XTO 7 6543210 SAO_CLK3 SAO_CLK2 SAO_CLK1 SAO_CLK0 SAO _MCLK SRC_MCLK1 SRC_MCLK0 SRC_DIV 0 1000000

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SRC_MCLK[1:0] - Controls the master clock (MCLK) source for the sample rate converter. See “SRC Mas- ter Clock” on page 38 for details. 00 - XTI-XTO. If XTI is connected to GND or VL and XTO is left floating, the SRC MCLK will be the internal ring oscillator. 01 - PLL clock 10 - Internal Ring Oscillator 11 - Reserved SRC_DIV – Divide-by-two for the SRC MCLK source. Valid only if SRC_MCLK = 00. 0 - SRC MCLK is not divided. Maximum allowable SRC MCLK frequency is 33 MHz. 1 - SRC MCLK is divided. Maximum allowable SRC MCLK frequency is 49.152 MHz. 11.9 Recovered Master Clock Ra tio Control & Misc. (09h) RMCK[3:0] – Selects the RMCK/Fsi ratio, where Fsi is th e sample rate of the incoming AES3-compatible data or ISCLK/64. Note: If a serial audio output port is in master mode and sourced di rectly by the AES3 receiver, then RMCK is the master clock source for the selected serial output port and RMCK[3:0] determine the MCLK/OLRCK ratio for the selected serial output port. 0000 - RMCK = 64 x Fsi 0001 - RMCK = 96 x Fsi 0010 - RMCK = 128 x Fsi 0011 - RMCK = 192 x Fsi 0100 - RMCK = 256 x Fsi 0101 - RMCK = 384 x Fsi 0110 - RMCK = 512 x Fsi 0111 - RMCK = 768 x Fsi 1000 - RMCK = 1024 x Fsi SRC_MUTE – When SRC_MUTE is set to ‘1’, the SRC will soft-mute when it loses lock and soft unmute when it regains lock. 0 - Soft mute disabled 1 - Soft mute enabled

11.10 Data Routing Control(0Ah)

SDOUT1[1:0] - Controls the data source for SDOUT1 7 6543210 RMCK3 RMCK2 RMCK1 RMCK0 SRC_MUTE Reserved Reserved Reserved 0 0001 7 6543210 SDOUT1(1) SDOUT1(0) SD OUT2(1) SDOUT2(0) MUTESAO1 MUTESAO2 SRCD Reserved 0 001000

1 - SDOUT2 muted (set to all zeros).

11.11 Serial Audio Input Data Format (0Bh)

0 - Serial audio input port is in slave mode. ISCLK and ILRCK are inputs. 1 - Serial audio input port is in master mode. ISCLK and ILRCK are outputs. Table 8. ISCLK/ILRCK Ratios and SISF Settings

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11.12 Serial Audio Output Da ta Format - SDOUT1 (0Ch)

0 - Serial audio output port is in slave mode. OSCLK and OLRCK are inputs. 1 - Serial audio output port is in master mode. OSCLK and OLRCK are outputs. SAI_CLK[3:0] determines the MCLK/OLRCK1 ratio. Table 9. OSCLK1/OLRCK1 Ratios and SOSF1 Settings

11 - AES3 Direct. Direct copy of the received NRZ data from the AES3 receiver including C, U, and V bits. sourced directly by the AES3-compatible receiver. TDM[1:0] - Enable the time-division multiplexing (TDM) through TDM_IN and either SDOUT1 or SDOUT2. See “Time Division Multiplexing (TDM) Mode” on page 27 for more details. 01 - TDM Mode enabled through TDM_IN and SDOUT1. SOFSEL1[1:0] has no effect in this mode. 10 - TDM Mode enabled through TDM_IN and SDOUT2. SOFSEL2[1:0] has no effect in this mode.

11.13 Serial Audio Output Da ta Format - SDOUT2 (0Dh)

0 - Serial audio output port is in slave mode. OSCLK and OLRCK are inputs. 1 - Serial audio output port is in master mode. OSCLK and OLRCK are outputs. then SAI_CLK[3:0] determine the MCLK/OLRCK1 ratio. Table 10. OSCLK2/OLRCK2 Ratios and SOSF1 Settings

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11 - AES3 Direct. Direct copy of the received NRZ data from the AES3 receiver including C, U, and V bits. source is the AES3-compatible receiver.

11.14 Receiver Error Unmasking (0Eh)

Edge Active” in the Interrupt Mode register (register 10h). This register defaults to 00h.

11.15 Interrupt Unmasking (0Fh)

to 0, the error is masked, meaning that its occurrence will not affect the internal INT signal or the status reg- ister. The bit positions align with the corresponding bits in Interrupt Status register. This register defaults to 00h. The INT signal may be selected to output on the GPO pins. See Section 11.5 on page 50 for more details.

11.16 Interrupt Mode (10h)

The interrupt mode control in the behavior of the INT pin to RERR and SRC_UNLOCK interrupts. There are three ways to set the INT pin active in accordance wi th the interrupt condition. In the Rising edge active mode, the INT pin becomes active on the arrival of the interrupt condition. In the Falling edge active mode, the INT pin becomes active on the removal of the interrupt condition. In Level active mode, the INT interrupt pin becomes active during the interrupt condition. Be aware that the active level (Active High or Low) only depends on the INT[1:0] bits. These registers default to 00h. The interrupts in the Interrupt Status register not represented here are all rising edge active. 00 - Rising edge active 01 - Falling edge active 10 - Level active 11 - Reserved

11.17 Receiver Channel Status (11h)

The bits in this register can be associated with either channel A or B of the received data. The desired chan- nel is selected with the CHS bit of “Receiver Data Control (04h)” on page 48. AUX3:0 - Incoming auxiliary data field width, as indicated by the incoming channel status bits, decoded ac- cording to IEC60958 and AES3. 0000 - Auxiliary data is not present. 0001 - Auxiliary data is 1 bit long. 0010 - Auxiliary data is 2 bits long. 0011 - Auxiliary data is 3 bits long. 0100 - Auxiliary data is 4 bits long. 0101 - Auxiliary data is 5 bits long. 0110 - Auxiliary data is 6 bits long. 0111 - Auxiliary data is 7 bits long. 1000 - Auxiliary data is 8 bits long. 1001 - 1111 Reserved PRO - Channel status block format indicator 0 - Received channel status block is in the consumer format. 765432 1 0 Reserved Reserved Reserved Reserve d RERR1 RERR0 SRC_UNLOCK1 SRC_UNLOCK0 00 0 0 76543210 AUX3 AUX2 AUX1 AUX0 PRO COPY ORIG EMPH

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1 - Received channel status block is in the professional format. COPY - SCMS copyright indicator 0 - Copyright asserted. 1 - Copyright not asserted. If the category code is set to General in the incoming AES3 stream, copyright will always be indicated by COPY, even when the stream indicates no copyright. ORIG - SCMS generation indicator, decoded from the category code and the L bit. 0 - Received data is 1st generation or higher. 1 - Received data is original. Note: COPY and ORIG will both be set to 1 if incoming da ta is flagged as professional or if the receiver is not in use. EMPH – Indicates if the input channel status data indicates that the incoming audio data has been pre-em- phasized. 0 – 50 μs/15 μs pre-emphasis indicated. 1 – 50 μs/15 μs pre-emphasis not indicated.

11.18 Format Detect Status (12h)

Note: PCM, DTS_LD, DTS_CD and IEC61937 are mutually exclusive. A ‘1’ indicated the condition was detected. PCM – Un-compressed PCM data was detected. IEC61937 – IEC61937 data was detected. DTS_LD – DTS_LD data was detected. DTS_CD – DTS_CD data was detected. HD_CD – HD_CD data was detected. DGTL_SIL – Digital Silence was detected: at least 2047 consecutive constant samples of the same 24-bit audio data on both channels.

11.19 Receiver Error (13h)

This register contains the AES3 receiver status bits. Unmasked bits will go high on occurrence of the error, and will stay high until the register is read. Reading th e register resets all bits to 0, unless the error source is still true. Bits that are masked off in the receiver error mask register will always be 0 in this register. QCRC - Q-subcode data CRC error indicator. Updated on Q-subcode block boundaries 0 - No error. 1 - Error. 76543210 PCM IEC61937 DTS_LD DTS_CD HD_CD DGTL_SIL Reserved Reserved 76543210 Reserved QCRC CCRC UNLOCK V CONF BIP PAR

CCRC - Channel Status Block Cyclic Redundancy Check bit. Updated on CS block boundaries, valid only in Pro mode. 0 - No error. 1 - Error. UNLOCK - Receiver lock status when sourced by incoming AES3-compati ble data. Updated on CS block boundaries. 0 - Receiver locked. 1 - Receiver out of lock. V - Received AES3 Validity bit status. Updated on sub-frame boundaries. 0 - Data is valid and is normally linear coded PCM audio. 1 - Data is invalid, or may be valid compressed audio. CONF - Confidence bit. Updated on sub-frame boundaries. 0 - No error. 1 - Confidence error. The input data stream may be near error condition due to jitter degradation. BIP - Bi-phase error bit. Updated on sub-frame boundaries. 0 - No error. 1 - Bi-phase error. This indicates an error in the received bi-phase coding. PAR - Parity bit. Updated on sub-frame boundaries. 0 - No error. 1 - Parity error.

11.20 Interrupt Status (14h)

For all bits in this register, a “1” means the associated interrupt condition has occurred at least once since the register was last read. A “0” means the associated interrupt condition has NOT occurred since the last reading of the register. Reading the register resets all bits to 0, unless the interrupt mode is set to level and the interrupt source is still true. Status bits that are masked off in the associated mask register will always be “0” in this register. PCCH – PC burst preamble change. Indicates that the PC byte has changed from its previous value. If the IEC61937 bit in the Format Detect Status register goes high, it will cause a PCCH interrupt even if the PC byte hasn’t changed since the last time the IEC61937 bit went high. OSLIP - Serial audio output port data slip interrupt When the serial audio output port is in slave mode, and OLRCK is asynchronous to the port data source, this bit will go high every time a data sample is dropped or repeated. See “Serial Port Clock Operation” on page 25 for more information. 76543210 PCCH OSLIP DETC CCH RERR QCH FCH SRC_UNLOCK

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DETC - D to E C-buffer transfer interrupt. Indicates the completion of a D to E C-buffer transfer. See “Channel Status Buffer Management” on page 53. CCH - C-Data change. Indicates that the current 10 bytes of channel status is different from the previous 10 bytes. (5 bytes per channel) RERR - A receiver error has occurred. The Receiver Error register may be read to determine the nature of the error which caused the interrupt. QCH – A new block of Q-subcode is available for reading. The data must be read within 588 AES3 frames after the interrupt occurs to avoid corruption of the data by the next block. FCH – Format Change Goes high when the PCM, IEC61937, DTS_LD, DTS_CD, or DGTL_SIL bits in the Format Detect Status register transition from 0 to 1. When these bits in the Format Detect Status register transition from 1 to 0, an interrupt will not be generated. SRC_UNLOCK - SRC Unlock condition. Indicates that the SRC has lost the ability to output valid data

11.21 PLL Status (15h)

RX_ACTIVE - Receiver Active This bit is a level-signal version of the ACTIVE bit in register 13h. ISCLK_ACTIVE- ISCLK Active 0 - There is no toggling on the ISCLK pin, or the fr equency of toggling is less than 36 kHz on the ISCLK pin. 1 - There is toggling at a frequency of at least 1.536 MHz on the ISCLK pin. PLL_LOCK - 0 - The PLL has not achieved lock. 1 - The PLL, driven by either an AES3 or ISCLK input, has achieved lock. 96KHZ – Indicates the frequency range of the sample rate of incoming AES3 data (Fsi). If Fsi ≤ 49 kHz or Fsi ≥ 120 kHz, this bit will output a “0”. If 60 kHz ≤ Fsi ≤ 98 kHz, this bit will output a “1”. Otherwise the output is indeterminate. 192KHZ – Indicates the frequency range of the sample rate of incoming AES3 data (Fsi). If Fsi ≤ 98 kHz, this bit will output a “0”. If Fsi≥120 kHz, this bit will output a “1”. Otherwise the output is indeterminate. 76543210 RX_ACTIVE ISCLK ACTIVE PLL_LOCK 96KHZ 192KHZ Reserved Reserved Reserved

11.22 Receiver Status (16h)

CS_UPDATE - Determines whether channel status registers and RCVR_RATE are updated in the presence of a receiver error (register 14h). 0 - The receiver channel status registers and RCVR_RATE are updated on each AES3 block boundary. 1 - The receiver channel status registers and RCVR_RATE are updated on each AES3 block boundary if no biphase, confidence, parity, or CRCC error has occurred during the reception of the channel status block. RCVR_RATE - Input sample rate represented in the channel status data of incoming AES3 data. 00 - Reserved 01 - 32 kHz 10 - 44.1 kHz 11 - 48 kHz RX_LOCK - AES3 Receiver PLL Lock 0 - The PLL has not achieved lock for more than 2 Z preambles or AES3 input is not driving PLL. 1 - Goes high 2 Z preambles after the PLL has achieved lock when an AES3 input has been selected to drive the PLL. BLK_VERR - Block Validity Error. Updated on DETC boundaries 0 - The Validity bit of the incoming AES3 data has remained low during the input of the last AES3 data block. 1 - The Validity bit of incoming AES3 data has gone high at some point during the input of the last AES3 data block. BLK_CERR - Block Confidence Error. Updated on DETC boundaries 0 - The Confidence bit associated with incoming AES3 data has remained high during the input of the last AES3 data block. 1 - The Confidence bit associated with incoming AES3 data has gone low at least once during the input of the last AES3 data block. BLK_BERR - Block Biphase Error. Updated on DETC boundaries 0 - There has been no biphase error associated with incoming AES3 data during the input of the last AES3 data block. 1 - There has been at least one biphase error associated with incoming AES3 data during the input of the last AES3 data block. BLK_PERR - Block Parity Error. Updated on DETC boundaries 0 - There has been no parity error associated with incoming AES3 data during the input of the last AES3 data block. 76543210 CS_UPDATE RCVR_RATE1 RCVR_RATE0 RX_LOCK BLK_VERR BLK_CERR BLK_BERR BLK_PERR

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1 - There has been at least one pa rity error associated with incoming AES3 data during the input of the last AES3 data block.

11.23 Fs/XTI Ratio (17h - 18h)

FS_XTI[15:0] - 256*Fs/XTI, where Fs is the sample rate of incoming AES3-compatible data. The integer part of FS_XT[15:0] is represented in bits [15:10] in register 17h, and the fractional part is rep- resented in bits [9:0] of registers 17h and 18h; wit h a precision of 300 Hz in Fs and is updated approxi- mately every 2048/(XTI fr equency). Reading register 17h will caus e the value of 18h to freeze until register 18h is read.

11.24 Q-Channel Subcode (19h - 22h)

Each byte is LSB first with respect to the 80 Q-subcode bits Q[79:0]. Thus bit 7 of address 19h is Q[0] while bit 0 of address 19h is Q[7]. Similarly bit 0 of address 22h corresponds to Q[79].

11.25 Channel Status Re gisters (23h - 2Ch)

Each byte is MSB first with respect to the 80 Channel Status bits. Thus bit 0 of address 23h, AC0[0], is the location of the Pro bit. For N = 0-79, Channel Status bit N (per AES specification) is mapped to bit N mod 8 (remainder of N divided by 8) at address 23h+floor(N /8) (23h + integer result of N divided by 8 rounded down). For example, Channel Status bit 35 is mapped to bit 3 (35/8 = 4 remainder 3) of address 27h (23h + 4h). 76543210 FS_XT15 FS_XT14 FS_XT13 FS_XT12 FS_XT11 FS_XT10 FS_XT9 FS_XT8 FS_XT7 FS_XT6 FS_XT5 FS_XT4 FS_XT3 FS_XT2 FS_XT1 FS_XT0 76543210 CONTROL CONTROL CONTROL CONTROL ADDRESS ADDRESS ADDRESS ADDRESS TRACK TRACK TRACK TRACK TRACK TRACK TRACK TRACK INDEX INDEX INDEX INDEX INDEX INDEX INDEX INDEX MINUTE MINUTE MINUTE MINUTE MINUTE MINUTE MINUTE MINUTE SECOND SECOND SECOND SECOND SECOND SECOND SECOND SECOND FRAME FRAME FRAME FRAME FRAME FRAME FRAME FRAME ZERO ZERO ZERO ZERO ZERO ZERO ZERO ZERO ABS MINUTE ABS MINUTE ABS MINUT E ABS MINUTE ABS MINUTE ABS MI NUTE ABS MINUTE ABS MINUTE ABS SECOND ABS SECOND ABS SECOND ABS SECOND ABS SECOND ABS SECOND ABS SECOND ABS SECOND ABS FRAME ABS FRAME ABS FRAME ABS FRAME ABS FRAME ABS FRAME ABS FRAME ABS FRAME Address Channel Status Byte Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 23h Channel A Status Byte 0 AC0[7] AC0[6] AC0[5] AC0[4] AC0[3] AC0[2] AC0[1] AC0[0] 24h Channel A Status Byte 1 AC1[7] AC1[6] AC1[5] AC1[4] AC1[3] AC1[2] AC1[1] AC1[0] 25h Channel A Status Byte 2 AC2[7] AC2[6] AC2[5] AC2[4] AC2[3] AC2[2] AC2[1] AC2[0] 26h Channel A Status Byte 3 AC3[7] AC3[6] AC3[5] AC3[4] AC3[3] AC3[2] AC3[1] AC3[0] 27h Channel A Status Byte 4 AC4[7] AC4[6] AC4[5] AC4[4] AC4[3] AC4[2] AC4[1] AC4[0] 28h Channel B Status Byte 0 BC0[7] BC0[6] BC0[5] BC0[4] BC0[3] BC0[2] BC0[1] BC0[0] 29h Channel B Status Byte 1 BC1[7] BC1[6] BC1[5] BC1[4] BC1[3] BC1[2] BC1[1] BC1[0] 2Ah Channel B Status Byte 2 BC2[7] BC2[6] BC2[5] BC2[4] BC2[3] BC2[2] BC2[1] BC2[0] 2Bh Channel B Status Byte 3 BC3[7] BC3[6] BC3[5] BC3[4] BC3[3] BC3[2] BC3[1] BC3[0] 2Ch Channel B Status Byte 4 BC4[7] BC4[6] BC4[5] BC4[4] BC4[3] BC4[2] BC4[1] BC4[0]

11.26 IEC61937 PC/PD Burs t preamble (2Dh - 30h)

Address Burst Preamble Byte Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 2Dh Burst Preamble PC Byte 0 PC0[7] PC0[6] PC0[5] PC0[4] PC0[3] PC0[2] PC0[1] PC0[0] 2Eh Burst Preamble PC Byte 1 PC1[7] PC1[6] PC1[5] PC0[4] PC1[3] PC1[2] PC1[1] PC1[0] 2Fh Burst Preamble PD Byte 0 PD0[7] PD0[6] PD0[5] PC0[4] PD0[3] PD0[2] PD0[1] PD0[0] 30h Burst Preamble PD Byte 1 PD1[7] PD1[6] PD1[5] PD1[4] PD1[3] PD1[2] PD1[1] PD1[0]

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12.APPLICATIONS

12.1 Reset, Power Down, and Start-Up

When RST is low the CS8422 enters a low power mode, all internal states are reset, and the outputs are disabled. After RST transitions from low to high the part senses the resistor value on the configuration pins (MS_SEL and SAOF) and sets the appropriate mode of operation. After the mode has been set (approxi- mately 4 μs) the part is set to normal operation and all outputs are functional.

12.2 Power Supply, Gr ounding, and PCB layout

The CS8422 operates from a VA = +3.3 V and VL = +1.8 V to +5.0 V supply. These supplies may be set independently. Follow normal supply decoupling practices, see Figure 7 and 8 for details. Extensive use of power and ground planes, ground plane fill in unused areas, and surface mount decoupling capacitors are recommended. Decoupling capacitors should be mounted on the same side of the board as the CS8422 to minimize inductance effects and all decoupling capacitors should be as close to the CS8422 as possible. The pin of the configuration resistors not connected to MS_SEL and SAOF should be connect- ed as close as possible to VL or DGND.

12.3 External Receiver Components

The CS8422 AES3 receiver is designed to accept both the professional and consumer interfaces. The dig- ital audio specifications for prof essional use call for a balanced re ceiver, using XLR connectors, with 110 Ω ± 20% impedance. The XLR connector on the receiver should have female pins with a male shell. Since the receiver has a very high input impedance, a 110 Ω resistor should be placed across the receiver terminals to match the line impedance, as shown in Figure 26 and Figure 27. Although transformers are not required by the AES specification, they are strongly recommended. If some isolation is desired without the use of transformers, a 0.01 μF capacitor should be placed in series with each input pin (RXP[3:0] and RXN[3:0]) as shown in Figure 27. However, if a transformer is not used, high frequency energy could be coupled into the receiver, causing degradation in analog performance. Figure 26 and Figure 27 show an optional (recommended) DC blocking capacitor (0.1 μF to 0.47 μF) in se- ries with the cable input. This improves the robustness of the receiver, preventing the saturation of the trans- former, or any DC current flow, if a DC voltage is present on the cable. The circuit in Figure 28 shows the input circuit for switching betwe en up to four single-ended signals in re- ceiver input Mode 1 (analog sensitivity mode). If the application requires switching between a single-ended consumer interface and a differential interface, the CS8422 must be in differential mode and the input circuit in Figure 28 should be used for the single ended source. Standards for the consumer interface call for an unbalanced circuit having a receiver impedance of 75 Ω ±5%. The connector for the consumer interface is an RCA phono socket. The circuit in Figure 29 shows the input circuit for switching between up to four single-ended TTL or CMOS signals, and should be used when the S/PDIF receiver is in Receiver Input Mode 2. If the application re- quires switching between a CMOS or TTL source and a differential source, the CS8422 must be in differ- ential mode and the input circuit in Figure 30 should be used for the single-ended digital source. If the application requires switching between a single ended source in Mode 1, and a TTL or CMOS source, the circuit in Figure 30 should be used for the CMOS/TTL source (no RXN connection is present in this case). When designing systems, it is im portant to avoid ground loops and DC current flowing down the shield of the cable that could result when boxes with different ground potentials are connected. Generally, it is good practice to ground the shield to the chassis of the transmitting unit, and connect the shield through a capac- itor to chassis ground at the receiver. However, in some cases it is advantageous to have the ground of two

12.3.1 Attenuating Input signals

gle-ended and differential inputs. In both cases, equations (1) and (2) must be satisfied simultaneously. Figure 26. Professional Input Circuit – Differential Figure 27. Transformerless Professional Input Cir- Figure 28. S/PDIF MUX Input Circuit – Single-Ended Receiver Mode 1 Single-Ended Input Circuit – Figure 29. S/PDIF MUX Input Circuit – Digital Mode Figure 30. TTL/CMOS Input Circuit – Differential

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12.3.2 Isolating Transformer Requirements

12.4 Channel Status Buffer Management

12.4.1 AES3 Channel Stat us (C) Bit Management

= 80 bits). The user may read from this buffer’s RAM through the control port. address 23h) is the consumer/professional bit for channel status block A. Figure 31. Receiver Input Attenuation – Single-ended Input Figure 32. Receiver Input Attenuation – Differential Input

12.4.2 Accessing the E buffer

the CS8422, through the control port. transfers occur. This allows determination of the allowable time periods to interact with the E buffer. “long” control port interactions are occurring or for debugging purposes. there is a substantial time interval until the next D to E transfer (approximately 192 frames worth of time). This is usually enough time to access the E data without having to inhibit the next transfer. Figure 33. Channel Status Data Buffer Structure Figure 34. Flowchart for Reading the E Buffer

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12.4.3 Serial Copy Mana gement System (SCMS)

Status and User Data Handling” on page 34 for more details.

12.5 Jitter Attenuation

ifications state a maximum of 2 dB jitter gain. Figure 35. CS8422 PLL Jitter Attenuation Characteristics

12.6 Jitter Tolerance

cation. CS8422 devices have been tested to pass this template.

12.7 Group Delay

delay will be equal to the interface delay. Figure 36. Jitter Tolerance Template

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24 bits; Serial Audio Input and Output ports set to slave; Input and output clocks and data are asynchronous. Figure 37. Wideband FFT – Figure 38. Wideband FFT – Figure 39. Wideband FFT – Figure 40. Wideband FFT – Figure 41. Wideband FFT – Figure 42. Wideband FFT –

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Figure 49. Wideband FFT – Figure 50. IMD – Figure 51. Wideband FFT – Figure 52. IMD – Figure 53. IMD – Figure 54. Wideband FFT –

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Figure 61. THD+N vs. Output Sample Rate – Figure 62. THD+N vs. Output Sample Rate – Figure 63. THD+N vs. Output Sample Rate – Figure 64. Dynamic Range vs. Output Sample Rate – Figure 65. THD+N vs. Output Sample Rate – Figure 66. Dynamic Range vs. Output Sample Rate –

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Figure 73. Linearity Error – Figure 74. Linearity Error – Figure 75. Linearity Error – Figure 76. Linearity Error – Figure 77. Linearity Error – Figure 78. Linearity Error –

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Figure 85. THD+N vs. Input Frequency – Figure 86. THD+N vs. Input Frequency – Figure 87. THD+N vs. Input Frequency – Figure 88. THD+N vs. Input Frequency – Figure 89. Total Power Supply Current vs. Differential

14.PACKAGE DIMENSIONS Notes: 1. Dimensioning and tolerance per ASME Y 14.5M-1995. 2. Dimensioning lead width applies to the plated terminal and is measured between 0.20 mm and 0.25 mm from the terminal tip 15.THERMAL CHARACTERISTICS AND SPECIFICATIONS Notes: 1. θJA is specified according to JEDEC specifications for multi-layer PCBs. INCHES MILLIMETERS NOTE DIM MIN NOM MAX MIN NOM MAX A1 0.0000 -- 0.0020 0.00 -- 0.05 1 D 0.1969 BSC 5.00 BSC 1 E 0.1969 BSC 5.00 BSC 1 e 0.0197 BSC 0.50 BSC 1 JEDEC #: MO-220 Controlling Dimension is Millimeters. Parameters Symbol Min Typ Max Units Package Thermal Resistance (Note 1) θJA -3 8- ° C / W a t t Allowable Junction Temperature - - 125 °C Side View Bottom ViewTop View A Pin #1 Corner D E D2L b e Pin #1 Corner 32L QFN (5 X 5 mm BODY) PACKAGE DRAWING

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16.ORDERING INFORMATION 17.REFERENCES 1. Audio Engineering Society AES3-2003: “AES standard for digital audio - Digital input-output interfacing - Serial transmission format for two-channel linearly represented digital audio data,” September 2003. 2. Audio Engineering Society AES-12id-2006: “AES Information Document for digital audio measurements - Jitter performance specifications,” May 2007. 3. Philips Semiconductor, “ The I²C-Bus Specification: Version 2,” Dec. 1998. http://www.semiconductors.philips.com Product Description Package Pb-Free Grade Temp Range Container Order# CS8422 24-bit, Asynchronous Sample Rate Converter with Integrated Digital Interface Receiver QFN YES Commercial -40° to +85°C Rail CS8422-CNZ Tape and Reel CS8422-CNZR Automotive -40° to +105°C Rail CS8422-DNZ Tape and Reel CS8422-DNZR CDB8422 Evaluation Board for CS8422 - YES - - - CDB8422

18.REVISION HISTORY Release Changes PP1 Added interchannel phase deviation to Performance Specifications - Sample Rate Converter table Added gain error to Performance Specifications - Sample Rate Converter table Added 32 kHz:48 kHz dynamic range to Performance Specifications - Sample Rate Converter table Updated (Note 2) in Performance Specifications - Sample Rate Converter table Updated values in DC Electrical Characteristics table Changed (Note 3) and (Note 4) in DC Electrical Characteristics table Updated RMCK jitter specification in Switching Specifications table Changed (Note 9) in Switching Specifications table Moved SDIN/TDM_IN setup and hold times in Switching Specifications table Changed master mode non-TDM I/OSCLK minimum frequency in Switching Specifications table Changed tsrs value in Switching Characteristics - Control Port - SPI mode Changed tirs value in Switching Characteristics - Control Port - I²C mode Fixed calculation error in Section 5.1.5.2 TDM Slave Mode Added note to Section 11.9 Recovered Master Clock Ratio Control & Misc. (09h) Added Section 12.6 Jitter Tolerance Added Section 13. Performance Plots Added Section 17. References Updated VIH minimum specification in Digital Interface Specifications table Updated VIL maximum specification in Digital Interface Specifications table Updated Input Hysteresis specification in Digital Interface Specifications table Added (Note 6) to Digital Interface Specifications table Removed VIH maximum specification in Digital Interface Specifications table Removed VIL minimum specification in Digital Interface Specifications table PP2 Updated package dimensions in Section 14. Package Dimensions

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Contacting Cirrus Logic Support For all product questions and inquiries, contact a Cirrus Logic Sales Representative. To find one nearest you, go to www.cirrus.com. IMPORTANT NOTICE “Preliminary” product information describes products that are in production, but for which full characterization data is not yet available. Cirrus Logic, Inc. and its sub- sidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of re levant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this informa- tion, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROP- ERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRIT- ICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK AND CIR- RUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOM- ER’S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING AT- TORNEYS’ FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. AC-3 is a registered trademark of Dolby Laboratories, Inc. DTS is a registered trademark of Digital Theater Systems, Inc. I²C is a registered trademark of Philips Semiconductor. SPI is a trademark of Motorola, Inc.