CS5368_07 CIRRUS | Alldatasheet
Document overview
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Technical content
Features
Advanced Multi-bit Delta-Sigma Architecture 24-Bit Conversion 114 dB Dynamic Range -105 dB THD+N Supports Audio Sample Rates up to 216 kHz Selectable Audio Interface Formats – Left-Justified, I²S, TDM – 8-Channel TDM Interface Formats Low Latency Digital Filter Less than 680 mW Power Consumption On-Chip Oscillator Driver Operation as System Clock Master or Slave Auto-Detect Speed in Slave Mode Differential Analog Architecture Separate 1.8 V to 5 V Logic Supplies for Control and Serial Ports High-Pass Filter for DC Offset Calibration Overflow Detection Footprint Compatible with the 4-Channel CS5364 and 6-Channel CS5366 Additional Control Port Features Supports Standard I²C® or SPI™ Control Interface Individual Channel HPF Disable Overflow Detection for Individual Channels Mute Control for Individual Channels Independent Power-Down Control per Channel Pair Digital Audio Voltage Reference Level Translator Level Translator Internal Oscillator VD 3.3 - 5V Control Interface I2C, SPI or Pins Configuration Registers VA VLC 1.8 - 5V VLS 1.8 - 5V
8 Differential
ΔΣ ADC CS5368 JULY '07 DS624F2
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Description
The CS5368 is a complete 8-channel analog-to-digital converter for digital audio systems. It performs sampling, an- alog-to-digital conversion, and anti-alias filtering, generating 24-bit values for all 8-chann el inputs in serial form at sample rates up to 216 kHz per channel. The CS5368 uses a 5th-order, multi-bit delta sigma modula tor followed by low latency di gital filtering and decima- tion, which removes the need for an external anti-aliasing filter. The ADC uses a differential input architecture which provides excellent noise rejection. Dedicated level translators for the Serial Port and Control Port allow seamless interfacing between the CS5368 and other devices operating over a wide range of logic levels. In addition, an on-chip oscillator driver provides clocking flexibility and simplifies design. The CS5368 is the industry’s first audio A/D to support a high-speed TDM interface which provides a serial output of 8 channels of audio data with sample rates up to 216 kHz within a single data stream . It further reduces layout complexity and relieves input/output constraints in digital signal processors. The CS5368 is available in 48-pin LQFP package in both Commercial (-40° to 85°C) and Automotive grades (-40° to +105°C). The CDB5368 Customer Demonstration board is also available for device evaluation and implementation suggestions. Please see “Ordering Information” on page 41 for complete ordering information. The CS5368 is ideal for high-end and pro-audio systems requiring unrivaled sound quality, transparent conversion, wide dynamic range and negligible distortion, such as A/V receivers, digital mixing consoles, multi-channel record- ers, outboard converters, digital effect processors, and automotive audio systems.
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Figure 1. CS5368 Pinout
Pin Name Pin # Pin Description AIN2+, AIN2- AIN4+, AIN4- AIN3+, AIN3- AIN7+, AIN7- AIN8+, AIN8- AIN6+, AIN6- AIN5+, AIN5- AIN1+, AIN1- 1,2 11,12 13,14 15,16 17,18 43,44 45,46 47,48 Differential Analog (Inputs) - Audio signals are presented differently to the delta sigma modula- tors via the AIN+/- pins. GND 3,8 10,19 29,32 Ground (Input) - Ground reference. Must be connected to analog ground. VA 4,9 Analog Power (Input) - Positive power supply for the analog section REF_GND 5 Reference Ground (Input) - For the internal sampling circuits. Must be connected to analog ground. FILT+ 6 Positive Voltage Reference (Output) - Reference voltage for internal sampling circuits. VQ 7 Quiescent Voltage (Output) - Filter connection for the internal quiescent reference voltage. VX 20 Crystal Oscillator Power (Input) - Also powers control logic to enable or disable oscillator cir- cuits. XTI XTO Crystal Oscillator Connections (Input/Output) - I/O pins for an external crystal which may be used to generate MCLK. MCLK 23 System Master Clock (Input/Output) - When a crystal is used, this pin acts as a buffered MCLK Source (Output). When the oscillator function is not used, this pin acts as an input for the system master clock. In this case, the XTI and XTO pins must be tied low. LRCK/FS 24 Serial Audio Channel Clock (Input/Output) In I²S Mode, Serial Audio Channel Select. When low, the odd channels are selected. In LJ Mode, Serial Audio Channel Select. When high, the odd channels are selected. In TDM Mode, a frame sync signal. When high, it marks the beginning of a new frame of serial audio samples. In Slave Mode, this pin acts as an input pin. SCLK 25 Main timing clock for the Serial Audio Interface (Input/Output) - During Master Mode, this pin acts as an output, and during Slave Mode it acts as an input pin. SDOUT4 26 Serial Audio Data (Output) - Channels 7,8. SDOUT2 27 Serial Audio Data ( Output) - Channels 3,4. VLS 28 Serial Audio Interface Power (Input) - Positive power for the serial audio interface. SDOUT1/TDM 30 Serial Audio Data (Output) - Channels 1,2. SDOUT3/TDM 31 Serial Audio Data (Output) - Channels 5,6. TDM is complementary TDM data. VD 33 Digital Power (Input) - Positive power supply for the digital section/ VLC 35 Control Port Interface Power(Input) - Positive power for the control port interface. OVFL 36 Overflow (Output, open drain) - Detects an overflow condition on both left and right channels. RST 41 Reset (Input) - The device enters a low power mode when low. Stand-Alone Mode CLKMODE 34 CLKMODE (Input) - Setting this pin HIGH places a divide-by-1.5 circuit in the MCLK path to the core device circuitry. DIF1 DIF0 38 DIF1, DIF0 (Input) - Inputs of the audio interface format. 40 Mode Selection (Input) - Determines the operational mode of the device. MDIV 42 MCLK Divider (Input) - Setting this pin HIGH places a divide-by-2 circuit in the MCLK path to the core device circuitry.
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CLKMODE (Input) - This pin is ignored in Control Port Mode and the same functionality is obtained from the corresponding bit in the Global Control Register. Note: Should be connected to GND when using the part in Control Port Mode. AD1/CDIN 37 I²C Format, AD1 (Input) - Forms the device address input AD[1]. SPI Format, CDIN (Input) - Becomes the input data pin. AD0/CS 38 I²C Format, AD0 (Input) - Forms the device address input AD[0]. SPI Format, CS (Input) - Acts as the active low chip select input. SCL/CCLK 39 I²C Format, SCL (Output) - Acts as the serial clock output from the CS5368. SPI Format, CCLK (Output) - Acts as the serial clock output from the CS5368. SDA/CDOUT 40 I²C Format SDA (Input/Output) - Acts as an input/output data pin. SPI Format CDOUT (Output) - Acts as an output only data pin. MDIV 42 MCLK Divider (Input) - This pin is ignored in Control Port Mode and the same functionality is obtained from the corresponding bit in the Global Control Register. Note: Should be connected to GND when using the part in Control Port Mode.
- TYPICAL CONNEC TION DIAGRAM
Figure 2. Typical Connection Diagram tial solution is provided on the Customer Evaluation Board.
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- CHARACTERISTICS AND SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS GND = 0 V, all voltages with respect to 0 V. 1. TDM Quad-Speed Mode specified to operate correctly at VLS ≥ 3.14 V. ABSOLUTE RATINGS Operation beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. Transient currents up to ±100 mA on the analog input pins will not cause SCR latch-up. SYSTEM CLOCKING Parameter Symbol Min Typ Max Unit DC Power Supplies: Positive Analog Positive Crystal Positive Digital Positive Serial Logic Positive Control Logic VA VX VD VLS VLC 4.75 4.75 3.14 1.711 1.71 5.0 5.0 3.3 3.3 3.3 5.25 V Ambient Operating Temperature (-CQZ) (-DQZ) TAC TAA -40 -40 105 °C Parameter Symbol Min Typ Max Units DC Power Supplies: Positive Analog Positive Crystal Positive Digital Positive Serial Logic Positive Control Logic VA VX VD VLS VLC -0.3 - +6.0 V Input Current Iin -10 +10 mA Analog Input Voltage VIN -0.3 VA+0.3 VDigital Input Voltage VIND VL+0.3 Ambient Operating Temperature (Power Applied) TA -50 +95 °CStorage Temperature T stg -65 +150 Parameter Symbol Min Typ Max Unit Input Master Clock Frequency MCLK 0.512 55.05 MHz Input Master Clock Duty Cycle t clkhl 40 60 %
MCLK = 12.288 MHz; Master Mode; GND = 0 V. 1. Power-Down is defined as RST = LOW with all clocks and data lines held static at a valid logic level. LOGIC LEVELS PSRR, VQ AND FILT+ CHARACTERISTICS MCLK = 12.288 MHz; Master Mode. Valid with the recommended capacitor values on FILT+ and VQ as shown in the “Typical Connection Diagram”. Parameter Symbol Min Typ Max Unit Power Supply Current VA = 5 V (Normal Operation) VX = 5 V VD = 5 V VD = 3.3 V VLS, VLC = 5 V VLS, VLC = 3.3 V IA IX ID ID IL IL 100 112 mA Power Supply Current VA = VX = 5 V (Power-Down) (Note 1) VLS, VLC, VD = 5 V IA ID+L - 50 500 - μA Power Consumption Normal Operation All Supplies = 5 V VA = VX = 5 V, VD = VLS = VLC = 3.3 V (Power-Down) (Note 1) -- 930 675 2.75 1115 792 mW Parameter Symbol Min Typ Max Units High-Level Input Voltage %VLS/VLC V IH 70 %Low-Level Input Voltage %VLS/VLC V IL 30 High-Level Output Voltage at 100 μA load %VLS/VLC V OH 85 - Low-Level Output Voltage at -100 μA load %VLS/VLC V OL -1 5 OVFL Current Sink -4 mA Input Leakage Current logic pins only I in -10 - 10 μA Parameter Symbol Min Typ Max Unit Power Supply Rejection Ratio at (1 kHz) PSRR - 65 - dB VQ Nominal Voltage Output Impedance Maximum allowable DC current source/sink VA/2 V kΩ μA Filt+ Nominal Voltage Output Impedance Maximum allowable DC current source/sink VA 4.4 V kΩ μA
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ANALOG CHARACTERISTICS (COMMERCIAL) Test Conditions (unless otherwise specified). VA = 5 V, VD = VLS = VLC 3.3 V, and TA = 25° C. Full-scale input sine wave. Measurement Bandwidth is 10 Hz to 20 kHz. Parameter Symbol Min Typ Max Unit Single-Speed Mode Fs = 48 kHz Dynamic Range A-weighted unweighted 108 105 114 111 - dB Total Harmonic Distortion + Noise -1 dB referred to typical full scale -20 dB -60 dB THD+N - -105 -91 -51 -99 -45 dB Double-Speed Mode Fs = 96 kHz Dynamic Range A-weighted unweighted 40 kHz bandwidth unweighted 108 105 114 111 108 -d B Total Harmonic Distortion + Noise -1 dB referred to typical full scale -20 dB -60 dB 40 kHz bandwidth -1dB THD+N - -105 -91 -51 -102 -99 -45 dB Quad-Speed Mode Fs = 192 kHz Dynamic Range A-weighted unweighted 40 kHz bandwidth unweighted 108 105 114 111 108 -d B Total Harmonic Distortion + Noise -1 dB referred to typical full scale -20 dB -60 dB 40 kHz bandwidth -1dB THD+N - -105 -91 -51 -102 -99 -45 dB Dynamic Performance for All Modes Interchannel Isolation - 110 - dB DC Accuracy Interchannel Gain Mismatch - 0.1 - dB Gain Error -5 - 5 % Gain Drift - ± 100 - ppm/°C Offset Error HPF enabled HPF disabled
100 LSB
Analog Input Characteristics Full-scale Differential Input Voltage 1.07*VA 1.13*VA 1.19*VA Vpp Input Impedance (Differential) - 250 - k Ω Common Mode Rejection Ratio CMRR - 82 - dB
ANALOG CHARACTERISTICS (AUTOMOTIVE) and TA = -40° to +85° C. Full-scale input sine wave. Measurement Bandwidth is 10 Hz to 20 kHz. Parameter Symbol Min Typ Max Unit Single-Speed Mode Fs = 48 kHz Dynamic Range A-weighted unweighted 106 103 114 111 -d B Total Harmonic Distortion + Noise -1 dB referred to typical full scale -20 dB -60 dB THD+N - -105 -91 -51 -97 -45 dB Double-Speed Mode Fs = 96 kHz Dynamic Range A-weighted unweighted 40 kHz bandwidth unweighted 106 103 114 111 108 -d B Total Harmonic Distortion + Noise -1 dB referred to typical full scale -20 dB -60 dB 40 kHz bandwidth -1 dB THD+N - -105 -91 -51 -102 -97 -45 dB Quad-Speed Mode Fs = 192 kHz Dynamic Range A-weighted unweighted 40 kHz bandwidth unweighted 106 103 114 111 108 -d B Total Harmonic Distortion + Noise -1 dB referred to typical full scale -20 dB -60 dB 40 kHz bandwidth -1 dB THD+N - -105 -91 -51 -102 -97 -45 dB Dynamic Performance for All Modes Interchannel Isolation - 110 - dB DC Accuracy Interchannel Gain Mismatch - 0.1 - dB Gain Error -7 - 7 % Gain Drift - ± 100 - ppm/°C Offset Error HPF enabled HPF disabled Analog Input Characteristics Full-scale Input Voltage 1.02*VA 1.13*VA 1.24*VA Vpp Input Impedance (Differential) 250 - k Ω Common Mode Rejection Ratio CMRR - 82 - dB
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DIGITAL FILTER CHARACTERISTICS Notes: 1. The filter frequency response scales precisely with Fs. 2. Response shown is for Fs equal to 48 kH z. Filter characteristics scale with Fs. OVERFLOW TIMEOUT Logic "0" = GND = 0 V; Logic "1" = VLS; CL = 30 pF, timing threshold is 50% of VLS. Parameter Symbol Min Typ Max Unit Single-Speed Mode (2 kHz to 54 kHz sample rates) Passband (Note 1) (-0.1 dB) 0 0.47 Fs Passband Ripple -0.035 0.035 dB Stopband (Note 1) 0.58 Fs Stopband Attenuation -95 dB Total Group Delay (Fs = Output Sample Rate) t gd -1 2 / F s s Double-Speed Mode (54 kHz to 108 kHz sample rates) Passband (Note 1) (-0.1 dB) 0 0.45 Fs Passband Ripple -0.035 0.035 dB Stopband (Note 1) 0.68 Fs Stopband Attenuation -92 dB Total Group Delay (Fs = Output Sample Rate) t gd -9 / F s s Quad-Speed Mode (108 kHz to 216 kHz sample rates) Passband (Note 1) (-0.1 dB) 0 0.24 Fs Passband Ripple -0.035 0.035 dB Stopband (Note 1) 0.78 Fs Stopband Attenuation -92 dB Total Group Delay (Fs = Output Sample Rate) t gd -5 / F s s High-Pass Filter Characteristics Frequency Response (Note 2) -3.0 dB -0.13 dB - 1 20 -H z Phase Deviation (Note 2) @ 20 Hz 10 - Deg Passband Ripple -0 d B Filter Settling Time 105/Fs - s Parameter Symbol Min Typ Max Unit OVFL time-out on overrange condition Fs = 44.1 kHz Fs = 192 kHz (217-1)/Fs 2972 683 -m s
The serial audio port is a three-pin interface consisting of SCLK, LRCK and SDOUT. Logic "0" = GND = 0 V; Logic "1" = VLS; CL = 20 pF, timing threshold is 50% of VLS.
- Duty cycle of generated SCLK depends on duty cycle of received MCLK as specified under “System
- CLKMODE functionality described in Section 4.6.3 "Master Mode Clock Dividers" on page 24.
- In Slave Mode, the SCLK/LRCK ratio can be set a ccording to preference. However, chip performance
Figure 3. I²S/LJ Timing
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The serial audio port is a three-pin interface consisting of SCLK, LRCK and SDOUT. Logic "0" = GND = 0 V; Logic "1" = VLS; CL = 20 pF, timing threshold is 50% of VLS.
- TDM Quad-Speed Mode only specified to operate correctly at VLS ≥ 3.14 V.
- Duty cycle of generated SCLK depends on duty cycle of received MCLK as specified under “System
- CLKMODE functionality described in Section 4.6.3 "Master Mode Clock Dividers" on page 24.
- In Slave Mode, the SCLK/LRCK ratio can be set acco rding to preference; chip performance is guaran-
teed only when using the ratios in Section 4.7 Master and Slave Clock Frequencies on page 25. Figure 4. TDM Timing
- Data must be held for sufficient ti me to bridge the transition time, tfc, of SCL.
Figure 5. I²C Timing
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- Data must be held for sufficient time to bridge the transition time of CCLK.
Figure 6. SPI Timing
4.1 Power
powered from the analog supply via a single-pole decoupling filter. itors must be positioned to minimize the electrical path to ground. The CDB5368 evaluation board demonstrates optimum layout for the device.
4.2 Control Port Mode a nd Stand-Alone Operation
4.2.1 Stand-Alone Mode
offered in Control Port Mode. tion on the reset function is available in Section 4.5 on page 22.
4.2.2 Control Port Mode
page 30 provides detailed information about the I²C and SPI bus protocols. Table 1. Power Supply Pin Definitions
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4.3 Master Clock Source
driver or an externally generated clock.
4.3.1 On-Chip Crystal Oscillator Driver
chronize other parts to the device. Figure 7. Crystal Oscillator Topology
4.3.2 Externally Gene rated Master Clock
4.4 Master and Slave Operation
CS5368 operation depends on two clocks that are synchronously derived from MCLK: SCLK and LRCK/FS. See Section 4.5 on page 22 for a detailed description of SCLK and LRCK/FS. both Master and Slave Modes. 23 for more information regarding the configuration of M1 and M0 pins or M[1] and M[0] bits. Figure 8. Master/Slave Clock Flow
4.4.1 Synchronization of Multiple Devices
all converters begin sampling on the same clock edge. Figure 9. Master and Slave Clocking for a Multi-Channel Application
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4.5 Serial Audio Interface (SAI) Format
Stand-Alone Mode and Control Port Mode.
4.5.1 I²S and LJ Format
transmitted, odd channels first, then even. The MSB is always clocked out first. Figure 10. I²S Format Figure 11. LJ Format
4.5.2 TDM Format
timizing Performance in TDM Mode” on page 29 for critical system design information. Figure 12. TDM Format
4.5.3 Configuring Serial Audio Interface Format
Table 2. DIF1 and DIF0 Pin Settings
4.6 Speed Modes
4.6.1 Sample Rate Ranges
Double-Speed Mode (DSM), and Quad-Speed Mode (QSM), respectively.
4.6.2 Using M1 and M0 to Set Sampling Parameters
Port Mode, as shown in Table 3. Table 3. M1 and M0 Settings
01 I ² S
10 T D M
11 R e s e r v e d
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4.6.3 Master Mode Clock Dividers
cluding the significance of each MCLK divider pin (in Stand-Alone Mode) or bit (in Control Port Mode). Figure 13. Master Mode Clock Dividers
4.6.4 Slave Mode Audio Cl ocking With Auto-Detect
Figure 14. Slave Mode Auto-Detect Speed
4.7 Master and Slave Clock Frequencies
the frequencies shown. In Slave Mo de, the SCLK/LRCK ratio can be set according to design preference. However, device performance is guaranteed only when using the ratios shown in the tables. Table 4. Frequencies for 48 kHz Sample Rate using LJ/I²S Table 5. Frequencies for 96 kHz Sample Rate using LJ/I²S Table 6. Frequencies for 192 kHz Sample Rate using LJ/I²S Table 7. Frequencies for 48 kHz Sample Rate using TDM Table 8. Frequencies for 48 kHz Sample Rate using TDM
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Table 9. Frequencies for 96 kHz Sample Rate using TDM Table 10. Frequencies for 96 kHz Sample Rate using TDM Table 11. Frequencies for 192 kHz Sample Rate using TDM Table 12. Frequencies for 192 kHz Sample Rate using TDM
4.8 Reset
The device should be held in reset until power is applied and all incoming clocks are stable and valid. Upon de-assertion of RST, the state of the configuration pins is latched, the state machine begins, and the device starts sending audio output data a maximum of 524288 MCLK cycles after the release of RST. When chang- ing between mode configurations in Stand-Alone Mode, including clock dividers, serial audio interface for- mat, master/slave, or speed modes, it is recommended to reset the device following the change by holding the RST pin low for a minimum of one MCLK cycle and then restoring the pin to a logic-high condition.
4.8.1 Power-Down Mode
The CS5368 features a Power-Down Mode in which power is temporarily withheld from the modulators, the crystal oscillator driver, the digita l core, and the serial port. The us er can access Power-Down Mode by holding the device in reset and holding all clock lines at a static, valid logic level (either logic-high or logic- low). “DC Power” on page 11 shows the power-saving associated with Power-Down Mode.
4.9 Overflow Detection
4.9.1 Overflow in Stand-Alone Mode
The CS5368 includes overflow detection on all input channels. In Stand-Alone Mode, this information is presented as open drain, active low on the OVFL pin. The pin will go to a logical low as soon as an over- range condition in any channel is detected. The data will remain low, then time-out as specified in Section "Overflow Timeout" on page 14. After the time-out, the OVFL pin will return to a logical high if there has not been any other over-range condition detected. Note that an over-range condition on any channel will restart the time-out period.
4.9.2 Overflow in Control Port Mode
In Control Port Mode, the Overflow Status Register interacts with the Overflow Mask Register to provide interrupt capability for each individual channel. See Section 5.4 "02h (OVFL) Overflow Status Register" on page 33 for details on these two registers.
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4.10 Analog Connections
Figure 15. Recommended Analog Input Buffer
4.11 Optimizing Performance in TDM Mode
Noise Management is a design technique that is utilized in the majority of audio A/D converters. Noise man- agement is relatively simple conceptually. The goal of noise management is to interleave the on-chip digital activity with the analog sampling processes to ensure that the noise generated by the digital activity is min- imized (ideally non-existant) wh en the analog sampling occurs. Noise management, when implemented properly, minimizes the on-chip interference between the analog and digital sections of the device. This technique has proven to be very effective and has simplified the process of implementing an A/D converter into a systems design. The dominate source of interference (and most difficult to control) is the activity on the serial audio interface (SAI). However, noise management becomes more difficult to implement as audio sample rates increase simply due to the fact that there is less time between transitions on the SAI. The CS5368 A/D converter supports a multi-channel Time-Division-Multiplexed interface for Single, Double and Quad-Speed sampling modes. In Single-Speed Mode, sample rates below 50 kHz, the required fre- quencies of the audio serial ports are sufficiently low that it is possible to implement noise-management. In this mode, the performance of the devices are relatively immune to activity on the audio ports. However, in Double-Speed and Quad-Speed modes there is insufficient time to implement noise manage- ment due to the required frequencies of the audio ports. Therefore, analog performance, both dynamic range and THD+N, can be degraded if the serial por t transitions occurr concurrently with the analog sam- pling. The magnitude of the interference is not only related to the timing of the transition but also the di/dt or transient currents associated with the ac tivity on the serial ports. Even th ough there is insufficient time to properly implement noise management , the interference effects can be minimized by controlling the tran- sient currents required of the serial ports in Double- and Quad-Speed TDM Modes. In addition to standard mixed-signal design techniques, system performance can be maximized by following several guidelines during design. – Operate the serial audio port at 3.3 V and not 5 V. The lower serial port voltage lowers transent currents. – Operate the A/D converter as a system clock Slave. The serial clock and Left/Right clock become high- impedence inputs in this mode and do not generate significant transient currents. – Place a buffer on the serial data output very near the A/D converter. Minimizing the stray capacitance of the printed circuit board trace and the loading presented by other devices on the serial data line will minimize the transient current. – Place a resistor, near the converte r, beween the A/D serial data output and the buffer. This resistor will reduce the instantaneous switching currents into the capacitive loads on the nets, resulting in a slower edge rate. The value of the resistor should be as high as possible without causing timing problems elsewhere in the system.
4.12 DC Offset Control
The CS5368 includes a dedicated high-pass filter for each channel to remove input DC offset at the system level. A DC level may result in audible “clicks” when switching between devices in a multi-channel system. In Stand-Alone Mode, all of the high-pass filters remain enabled. In Control Port Mode, the high-pass filters default to enabled, but may be controlled by writing to the HPF register. If any HPF bit is taken low, the re- spective high-pass filter is enabled, and it continuously subtracts a measure of the DC offset from the output of the decimation filter. If any HPF bit is taken high during device operation, the value of the DC offset reg- ister is frozen, and this DC offset will continue to be subtracted from the conversion result.
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4.13 Control Port Operation
transition on the AD0/CS pin after the RST pin has been restored high. are ignored, and the internal register settings determine the operating modes of the part.
4.13.1 SPI Mode
from a controller); CDIN is the input data line from a controller; CDOUT is the output data line to a controller. Data is clocked in on the rising edge of CCLK and is supplied on the falling edge of CCLK.
- The eighth bit is a read/write indicator (R/W), which should be low to write. The next eight bits
form the Memory Address Pointer (MAP), which is set to the address of the register that is to be updated. increment after each byte is read or written, allowing block reads or writes of successive registers. desired. To begin a read, bring CS low, send out the chip address and set the read/write bit (R/W ) high. Figure 16. SPI Format
4.13.2 I²C Mode
In I²C Mode, SDA is a bidirectional da ta line. Data is clocked into and out of the part by the clock, SCL. CS5368 is being released from RST. CS5368 from the microcontroller after each transmitted byte. pseudocode illustrates an aborted write operation followed by a read operation. Send 10011xx0 (chip address & write operation). Send MAP byte, auto increment off. Send stop condition, aborting write. Send 10011xx1 (chip address & read operation). Receive byte, contents of selected register. Figure 17. I²C Write Format Figure 18. I²C Read Format
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- REGISTER MAP In Control Port Mode, the bits in these registers are used to control all of the programmable features of the ADC. All registers above 0Ah are RESERVED.
5.1 Register Quick Reference
5.2 00h (REVI) Chip ID Code & Revision Register Default: See description The Chip ID Code & Revision Register is used to store the ID and revision of the chip. Bits[7:4] contain the chip ID, where the CS5368 is represented with a value of 0x8. Bits[3:0] contain the revision of the chip, where revision A is represented as 0x0, revision B is represented as 0x1, etc. 5.3 01h (GCTL) Global M ode Control Register Default: 0x00 The Global Mode Control Register is used to control the Master/Slave Speed modes, the serial audio data format and the Master clock dividers for all channels. It also contains a Control Port enable bit. Bit[7] CP-EN manages the Control Port Mode. Until this bit is asserted, all pins behave as if in Stand-Alone Mode. When this bit is asserted, all pins used in Stand-Alone Mode are ignored, and the corresponding reg- ister values become functional. Bit[6] CLKMODE Setting this bit puts the part in 384X mode (divides XTI by 1.5), and clearing the bit in- vokes 256X mode (divide XTI by 1.0 - pass through). A d r N a m e 7654321 0
00 REVI CHIP-ID[3 :0] REVISION[3:0]
01 GCTL CP-EN CLKMODE MDIV[1:0] DIF[1:0] MODE[1:0]
02 OVFL OVFL8
OVFL7 OVFL6 OVFL5 OVFL4 OVFL3 OVFL2 OVFL1
03 OVFM OVFM8 OVFM7 OVFM6 OVFM5 OVFM4 OVFM3 OVFM2 OVFM1
04 HPF HPF8
HPF7 HPF6 HPF5 HPF4 HPF3 HPF2 HPF1
05 RESERVED - - - - - - - -
06 PDNE RESERVED PDN-BG PDN-OSC PDN87 PDN65 PDN43 PDN21
07 RESERVED - - - - - - - -
08 MUTE MUTE8 MUTE7 MUTE6 MUTE5 MUTE4 MUTE3 MUTE2 MUTE1
09 RESERVED - - - - - - - -
R CHIP-ID[3:0] REVISION[3:0] R / W 76543210 R/W CP-EN CLKMODE MDIV[1: 0] DIF[1:0] MODE[1:0]
Bits[5:4] MDIV[1:0] Each bit selects an XTI divider. When either bit is low, an XTI divide-by-1 function is selected. When either bit is HIGH, an XTI divide-by-2 function is selected. With both bits HIGH, XTI is divid- ed by 4. The table below shows the composite XTI division using both CLKMODE and MDIV[1:0]. Bits[3:2] DIF[1:0] Determine which data format the serial audio interface is using to clock-out data. DIF[1:0] 0x00 Left-Justified format 0x01 I²S format 0x02 TDM 0x03 Reserved Bits[1:0] MODE[1:0] This bit field determines the device sample rate range and whether it is operating as an audio clocking Master or Slave. MODE[1:0] 0x00 Single-Speed Mode Master 0x01 Double-Speed Mode Master 0x02 Quad-Speed Mode Master 0x03 Slave Mode all speeds 5.4 02h (OVFL ) Overflow Status Register Default: 0xFF, no overflows have occurred. Note: This register interacts with Register 03h, the Overflow Mask Register. The Overflow Status Register is used to indicate an individual overflow in a channel. If an overflow condition on any channel is detected, the corresponding bit in this register is asserted (low) in addition to the open drain active low OVFL pin going low. Each overflow status bit is sticky and is cleared only when read, pro- viding full interrupt capability. 5.5 03h (OVFM) Over flow Mask Register Default: 0xFF, all overflow interrupts enabled. The Overflow Mask Register is used to allow or prev ent individual channel overflow events from creating activity on the OVFL pin. When a particular bit is set low in the Mask register, the corresponding overflow bit in the Overflow Status register is prevented from causing any activity on the OVFL pin. CLKMODE,MDIV[1],MDIV[0] DESCRIPTION
000 Divide-by-1
100 Divide-by-1.5 001 or 010 Divide-by-2 101 or 110 Divide-by-3
011 Divide-by-4
111 Reserved
OVFL7 OVFL6 OVFL5 OVFL4 OVFL3 OVFL2 OVFL1 R / W 76543210 R/W OVFM8 OVFM7 OVFM6 OVFM5 OVFM4 OVFM3 OVFM2 OVFM1
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5.6 04h (HPF ) High-Pass Filter Register Default: 0x00, all high-pass filters enabled. The High-Pass Filter Register is used to enable or di sable a high-pass filter that exists for each channel. These filters are used to perform DC offset calibration, a procedure that is detailed in “DC Offset Control” on page 29. 5.7 05h Reserved 5.8 06h (PDN) Power Down Register Default: 0x00 - everything powered up The Power Down Register is used as needed to reduce the chip’s power consumption. Bit[7] RESERVED Bit[6] RESERVED Bit[5] PDN-BG When set, this bit powers-down the bandgap reference. Bit[4] PDN-OSC controls power to the internal oscillator core. When asserted, the internal oscillator core is shut down, and no clock is supplied to the chip. If the chip is running off an externally supplied clock at the MCLK pin, it is also prevented from clocking the device internally. Bit[3:0] PDN When any bit is set, all clocks going to a channel pair are turned off, and the serial data outputs are forced to all zeroes. 5.9 07h Reserved 5.10 08h (MUTE) Mute Control Register Default: 0x00, no channels are muted. The Mute Control Register is used to mute or unmute the serial audio data output of individual channels. When a bit is set, that channel’s serial data is muted by forcing the output to all zeroes. R / W 76543210 R/W HPF8 HPF7 HPF6 HPF5 HPF4 HPF3 HPF2 HPF1 R / W 76543210 RESERVED - - - - - - - - R / W 76543210 R/W RESERVED PDN-BG PDN-OSC PDN87 PDN65 PDN43 PDN21 R / W 76543210 RESERVED - - - - - - - - R / W 76543210 R/W MUTE8 MUTE7 MUTE6 MUTE5 MUTE4 MUTE3 MUTE2 MUTE1
5.11 09h Reserved 5.12 0Ah (SDEN ) SDOUT Enable Control Register Default: 0x00, all SDOUT pins enabled. The SDOUT Enable Control Register is used to tri-stat e the serial audio data output pins. Each bit, when set, tri-states the associated SDOUT pin. R / W 76543210 RESERVED - - - - - - - - R / W 76543210 R/W RESERVED SDEN4 SDEN3 SDEN2 SDEN1
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Figure 19. SSM Passband Figure 20. DSM Passband Figure 21. QSM Passband
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Figure 25. SSM -1 dB Cutoff Figure 26. DSM -1 dB Cutoff Figure 27. QSM -1 dB Cutoff
- PARAMETER DEFINITIONS Dynamic Range The ratio of the rms value of the signal to the rms su m of all other spectral components over the specified bandwidth. Dynamic Range is a signal-to-noise ratio measurement over the specified bandwidth made with a -60 dBFS signal. 60 dB is added to resulting measurement to refer the measurement to full scale. This technique ensures that the distortion components are below the noise level and do not affect the measure- ment. This measurement technique has been accepted by the Audio Engineering Society, AES17-199, and the Electronic Industries Association of Japan, EIAJ CP-307. Expressed in decibels. The dynamic range is specified with and without an A-weighting filter. Total Harmonic Distortion + Noise The ratio of the rms value of the signal to the rms su m of all other spectral components over the specified bandwidth (typically 10 Hz to 20 kH z), including distortion components. Expressed in decibels. Measured at -1 and -20 dBFS as suggested in AES17-1991 Annex A. Specified using an A-weighting filter. Frequency Response A measure of the amplitude response variation from 10 Hz to 20 kHz relative to the amplitude response at 1 kHz. Units in decibels. Interchannel Isolation A measure of crosstalk between one channel and all remaining channels, measured for each channel at the converter's output with no signal to the input under test and a full-scale signal applied to all other channels. Units in decibels. Interchannel Gain Mismatch The gain difference between left and right channels. Units in decibels. Gain Error The deviation from the nominal full-scale analog output for a full-scale digital input. Gain Drift The change in gain value with temperature. Units in ppm/°C. Offset Error Intrachannel Phase Deviation The deviation from linear phase within a given channel. Interchannel Phase Deviation The difference in phase response between channels.
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- PACKAGE DIMENSIONS THERMAL CHARACTERISTICS INCHES MILLIMETERS DIM MIN NOM MAX MIN NOM MAX * Nominal pin pitch is 0.50 mm Controlling dimension is mm. JEDEC Designation: MS026 Parameter Symbol Min Typ Max Unit Allowable Junction Temperature - - 135 °C Package Thermal Resistance θJA -4 8- °C/WθJC -1 5- E D1D e L B A 48L LQFP PACKAGE DRAWING E D1D e L B A
- ORDERING INFORMATION 10.REVISION HISTORY Product Description Package Pb-Free Grade Temp Range Container Order # CS5368 1 1 4d B , 1 9 2k H z , 8-channel A/D Converter 48-pin LQFP YES Commercial -40° to +85°C Tray CS5368-CQZ Tape & Reel CS5368-CQZR Automotive -40° to +105°C Tray CS5368-DQZ Tape & Reel CS5368-DQZR CDB5368 Evaluation Board for CS5368 CDB5368 Revision Changes A1 Initial Release A2 Added TDM information PP1 Updated table under “DC Power” on page 11. Updated Gain Error specification under “Analog Characteristics (Commercial)” on page 12 Added Master Mode specifications under “Serial Audio Interface - I²S/LJ Timing” on page 15 Added Master Mode specifications under “Serial Audio Interface - TDM Timing” on page 16 PP2 Updated “DC Power” on page 11. PP3 Updated TDM Timing Specifications. See “Serial Audio Interface - TDM Timing” on page 16. F1 Final Release Added Section 4.11 “Optimizing Performance in TDM Mode” on page 29. F2 Updated the wording of pin 24, LRCK/FS, in the pin description table on page 7 to correctly reflect the high/low clocking state for odd-channel selection in I²S and LJ Modes. Contacting Cirrus Logic Support For all product questions and inquiries, contact a Cirrus Logic Sales Representative. To find the one nearest you, go to www.cirrus.com. IMPORTANT NOTICE Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives con- sent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROP- ERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DE- VICES, LIFE SUPPORT PRODUCTS OR OTHER CRI TICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN S UCH APPLICATIONS IS UNDER- STOOD TO BE FULLY AT THE CUSTOMER’S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER’S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS’ FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. I²C is a registered trademark of Philips Semiconductor. SPI is a trademark of Motorola, Inc.