CS4812 CIRRUS | Alldatasheet
Document overview
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- PDF pages: 36
Technical content
Features
/G108DSP for embedded reverb/effects
applications
– 24-bit Audio Processing Engine – No External RAM required – Two 24-bit ∆Σ ADCs with 100 dB Dyn. Range – Two 24-bit ∆Σ DACs with 100 dB Dyn. Range /G108Mono Guitar or Mixer Effects firmware included /G108Real time parameter control via messaging protocol /G108Serial Control Port for microcontroller interface /G108Single +5V supply operation /G108100-pin Metric Quad Flat Package (MQFP) ORDERING INFO CS4812-KM -10 to +70°C 100-pin MQFP CDB4812 Electric Guitar Effects w/ Parameter Controls.
Description
The CS4812 is a complete audio effects processing system on a chip. This device includes a proprietary 24- bit audio processing engine with considerable on-chip RAM, two ADCs and two DACs. A full-featured serial control port allows interfacing to an external host microcontroller. Other features such as single +5V operation simplify system design. The CS4812, combined with Crystal effects firmware, is the ideal solution for a variety of effects processing applications where user parameter control is desired. The Crystal effects firmware provides a messaging protocol for the serial control port that allows an external microcontroller to have real-time parameter control over the audio effects. The complete processor and effects solution may be evaluated with the CDB4812 demonstration board. The CDB4812 demonstrates a host of mono electric guitar effects including a digital spring reverb, delay, chorus, flange and tremolo with parameter adjustment capability. Please refer to AN195 for more information on application firmware for the CS4812. I /c39/c36/c38/c3 /c6/c20 /c39/c36/c38/c3/c6 /c21 /c38/c48/c50/c56/c55 /c38/c48/c41/c44/c47 /c55/c14 /c38/c48/c41/c44/c47 /c55 /c16 /c36/c44 /c49/c47/c14 /c36/c44/c49/c53 /c14 /c59/c55 /c50 /c59/c55/c44 /c38/c47/c50 /c38/c46 /c48/c36/c49 /c36/c42 /c40/c53 /c36/c50/c56/c55/c20/c16 /c36/c50/c56/c55/c21/c16 /c57/c50/c47 /c55 /c36/c42/c40 /c53 /c40/c41 /c40/c53/c40/c49 /c38/c40 /c51/c44/c50 /c22/c51/c44/c50 /c21/c51/c44/c50 /c20/c51/c44/c50 /c19 /c54/c55/c40/c53/c40/c50 /c36/c49 /c36 /c47/c50/c42/c3/c47/c51/c41/c3/c36/c49 /c39 /c50/c56/c55/c51/c56/c55/c3/c54/c55/c36/c42/c40 /c39/c44/c42/c44/c55/c36/c47/c3/c43/c51/c41 /c36/c44/c49/c53 /c16 /c36 /c44/c49/c47/c16 /c54/c40/c53/c44/c36/c47/c3/c38 /c50 /c49/c55/c53/c50/c47 /c3 /c51/c50 /c53/c55/c3/c11 /c54/c51/c44/c3/c82/c85 /c3/c44 /c21 /c38/c12 /c36/c39/c38 /c54/c38/c51/c48 /c18 /c54 /c54/c51/c44 /c18/c44/c21 /c38 /c54/c38/c47/c18/c38/c38/c47/c46 /c54/c39/c36/c18/c38/c39 /c50 /c56/c55 /c36/c39/c20 /c18/c38/c39/c44 /c49 /c36/c39 /c19/c18/c38 /c54 /c53/c40/c52 /c53/c54/c55 /c50 /c57/c47/c18/c40/c53 /c53 /c3 /c3/c3 /c39/c44 /c42 /c44/c55 /c36/c47 /c3 /c51/c53/c50/c51/c53/c44/c40/c55 /c36/c53 /c60 /c21/c23 /c16/c37 /c44 /c55 /c3 /c36 /c56/c39 /c44 /c50 /c51/c53/c50/c38/c40/c54/c54/c44/c49/c42/c3/c40/c49/c42/c44/c49/c40 /c53/c36 /c48 /c38/c47/c46/c50/c56/c55 /c41/c44/c47 /c55/c40/c53/c54 /c36/c50/c56/c55/c20/c16 /c36/c50/c56/c55/c21/c14 JUL ‘01 DS291PP3
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Figure 3. I Figure 6. Typical Connection Diagram, Control Port I Figure 8. Typical Connection Diagram, Control Port I marks and service marks can be found at http://www.cirrus.com.
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- CHARACTERISTICS AND SPECIFICATIONS ADC CHARACTERISTICS (TA = 25°C; VA, VD = + 5V; -1 dB Full Scale Input Sine wave, 997 Hz; Fs = 48 kHz; XTI = 12.288 MHz (PLL disabled). Measurement Bandwidth is 20 Hz to 20 kHz.) Notes: 1. Referenced to typical full-scale differential input voltage (2 V rms). 2. Bench tested only. 3. Filter characteristics scale with output sample rate. 4. Group delay for Fs = 48 kHz, t gd = 15/48 kHz = 313 µs. 5. Measured using differential analog input circuit, see Figure 10. 6. Filter Response is not tested but guaranteed by design. Parameters Symbol Min Typ Max Units Analog Input Characteristics ADC Conversion Stereo Audio channels 16 - 24 Bits Dynamic Range (A weighted, Note 5) (unweighted, Note 5) 100 dB dB Total Harmonic Distortion + Noise (Note 1,5) (PLL enabled) (Note 1,2,5) THD+N - -92 -92 -87 dB Interchannel Isolation - 90 - dB Interchannel Gain Mismatch - 0.1 - dB Offset Error (with high pass filter enabled) (Note 6) - - 0 LSB Full Scale Input Voltage (Differential) 1.9 2.0 2.1 V rms Gain Drift (Note 2) - 100 - ppm/ °C Input Resistance 10 - - k Ω Input Capacitance - - 15 pF CMOUT Output Voltage - 2.3 - V Common Mode Rejection Ratio (Note 2) CMRR 60 dB Group Delay (Fs = Output Sample Rate) (Note 4) t gd -1 5 / F s- s Group Delay Variation vs. Frequency ∆tgd --0 µ s High Pass Filter Characteristics Frequency Response -3dB (Note 3) -0.14dB (Note 3) 3.7 Hz Hz Phase Deviation @ 20 Hz (Note 3) - 10 - Degree Passband Ripple - - 0 dB
DAC CHARACTERISTICS (TA = 25°C; VA, VD = + 5V; -1 dB Full Scale Output Sine wave, 997 Hz; Fs = 48 kHz; XTI = 12.288 MHz (PLL disabled). Measurement Bandwidth is 20 Hz to 20 kHz.) Notes: 7. Measured with DAC calibration disabled. 8. Measured with XTI clock disabled. Parameters Symbol Min Typ Max Units Analog Output Characteristics - Minimum Attenuation, 10 kΩ, 100 pF load; unless otherwise specified. DAC Resolution 16 - 24 Bits Dynamic Range (DAC not muted, A weighted) 95 100 - dB Total Harmonic Distortion + Noise THD+N - -90 -85 dB Interchannel Isolation - 90 - dB Interchannel Gain Mismatch - 0.1 - dB Offset Voltage (differential) (Note 7) - -20 ± 5 - mV Offset Voltage (V+/V- relative to CMOUT) (Note 7) - -45/-25 - mV Full Scale Output Voltage (Differential) 1.9 2.0 2.1 V rms Gain Drift (Note 2) - 100 - ppm/ °C Out of Band Energy (Fs/2 to 2Fs, Note 2) - -60 - dBFS Analog Output Load Resistance Capacitance 100 kΩ pF Group Delay (Fs = Input Sample Rate) t gd -1 6 / F s- s Analog Loopback Performance Signal-to-Noise Ratio (CCIR-2K weighted, -20 dB input) CCIR-2K - 74 - dB Power Supply Power Supply Current Operating Power Down (Note 8) 200 mA mA Power Supply Rejection (1 kHz, 10 mV rms, Note 2) - 50 - dB
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SWITCHING CHARACTERISTICS (TA = 25 °C; VA, VD = +5V, CL = 30 pF) Notes: 9. Guaranteed by characterization but not tested. 10. On power-up, the CS4812 RST pin should be asserted until the power supplies have reached steady state. Parameters Symbol Min Typ Max Units Audio ADC’s & DAC’s Sample Rate Fs 30 - 50 kHz XTI Frequency XTI = 128Fs, 256Fs, 512Fs 3.84 - 25.6 MHz XTI Duty Cycle XTI = 128Fs, 256Fs, 512Fs (Note 9) 40 - 60 % XTI Jitter Tolerance - 500 - ps RST Low Time (Note 10) 500 - - ns
SWITCHING CHARACTERISTICS - CONTROL PORT - SPI SLAVE (TA = 25 °C; VA, VD = 5 V; Inputs: Logic 0 = DGND, Logic 1 = VD, CL = 30 pF) Notes: 11. Data must be held for sufficient time to bridge 100 ns transition time of CCLK. 12. CDOUT should NOT be sampled during this time period. 13. DSPCLK frequency is twice the DSP instruction rate. 14. Timing is guaranteed by characterization. Production test guarantees functionality. Parameter Symbol Min Max Unit SPI Slave Mode (SPI /I2C = 0, SCPM/S = 0, Note 14) CCLK Clock Frequency fsck -6 M H z CCLK Low Time tscl 66 - ns CCLK High Time tsch 66 - ns Rise Time of Both CDIN and CCLK Lines tr -1 0 0 n s Fall Time of Both CDIN and CCLK Lines tf -1 0 0 n s Setup Time CDIN to CCLK Rising tcdisu 40 - ns Hold Time CCLK Rising to CDIN (Note 11) tcdih 15 - ns Time from CCLK edge to CDOUT Valid (Note 12) tscdov -4 5 n s Rise Time for CDOUT tcdor -2 5 n s Fall Time for CDOUT tcdof -2 5 n s CS Falling to CCLK Rising tcss 20 - ns Time from CCLK Falling to CS Rising tsccsh 0- n s High Time Between Active CS tcsht 1- µs Time from CCLK Rising to REQ Rising (Note 13) tscrh -2 * D S P C L K + 1 0 n s Rise Time for REQ trr -1 0 0 n s Fall Time for REQ trf -1 0 0 n s
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Figure 1. SPI Control Port Slave Mode Timing
RST is de-asserted and before the control port registers have been initialized.
- Measured with a 2.2 k Ω pull-up resistor to VD.
Figure 2. SPI Control Port Master Mode (AutoBoot) Timing
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SWITCHING CHARACTERISTICS - CONTROL PORT - I2C® SLAVE (TA = 25 °C; VA, VD = 5 V; Inputs: Logic 0 = DGND, Logic 1 = VD, CL = 30 pF) Notes: 17. Use of the I 2C bus interface requires a license from Philips. I2C is a registered trademark of Philips Semiconductors. 18. Not tested. 19. Data must be held for sufficient time to bridge the 300 ns transition time of SCL. 20. DSPCLK frequency is twice the DSP instruction rate. Parameter Symbol Min Max Units I2C® Slave Mode (SPI/I2C = 1, SCPM/S = 0) (Note 17) SCL Clock Frequency fscl -1 0 0 k H z Bus Free Time Between Transmissions tbuf 4.7 - µs Start Condition Hold Time (prior to first clock pulse) thdst 4.0 - µs SCL Low Time tlow 4.7 - µs SCL High Time thigh 4.0 - µs RST rising to start condition (Note18) tsrs 1- m s SDA Hold Time from SCL Falling (Note 19) thdd 0- µ s Rise Time of Both SDA and SCL tr -1 µ s Fall Time of Both SDA and SCL tf -3 0 0 n s SCL Falling to CS4812 ACK tsca -1 . 3 µ s SCL Falling to SDA Valid During READ tscsdv -1 . 5 µ s Time from SCL Rising to REQ Rising (Note 20) tscrh -2 * D S P C L K + 1 0 n s Rise Time for REQ trr -1 0 0 n s Fall Time for REQ trf -1 0 0 n s Setup Time for Stop Condition tsusp 4.7 - µs Setup Time for Repeated Start tsust 4.7 µs
Figure 3. I2C® Control Port Slave Mode Timing
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- Depending on the input clock configuration, CCLK may be up to 2*Fs temporarily during AutoBoot after
RST has been de-asserted and before the control port registers have been initialized.
- Data must be held for sufficient time to bridge the worst case fall time of 300 ns for CCLK/SCL.
- For both SDA transmitting and receiving.
Figure 4. I2C® Control Port Master Mode (AutoBoot) Timing
ABSOLUTE MAXIMUM RATINGS (All voltages with respect to AGND = DGND = 0V.) Notes: 25. Any pin except supplies. Transient currents of up to ±100 mA on the analog input pins will not cause SCR latch-up. 26. The maximum over or under voltage is limited by the input current. Warning: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. RECOMMENDED OPERATING CONDITIONS (All voltages with respect to AGND = DGND = 0V.) DIGITAL CHARACTERISTICS (TA = 25 °C; VA, VD = 5V) SWITCHING CHARACTERISTICS - PROGRAMMABLE I/O (TA = 25 °C; VA, VD = 5V ±5%; Inputs: logic 0 = DGND, logic 1 = VD, CL = 30 pF) Parameters Symbol Min Typ Max Units Power Supplies Digital Analog VD VA -0.3 -0.3 6.0 6.0 V V Input Current (Note 25) - - ±10.0 mA Analog Input Voltage (Note 26) -0.7 - (VA)+0.7 V Digital Input Voltage (Note 26) -0.7 - (VD)+0.7 V Ambient Temperature (Power Applied) -55 - +125 °C Storage Temperature -65 - +150 °C Parameters Symbol Min Typ Max Units Power Supplies Digital |VA - VD| < 0.4V Analog VD VA 4.75 4.75 5.0 5.0 5.25 5.25 V V Operating Ambient Temperature T A -10 25 70 °C Parameters Symbol Min Typ Max Units High-level Input Voltage (except XTI) V IH 2.8 - (VD)+0.3 V Low-level Input Voltage (except XTI) V IL -0.3 - 0.8 V High-level Output Voltage at I0 = -2.0 mA (except XTO) V OH (VD)-1.0 - - V Low-level Output Voltage at I0 = 2.0 mA (except XTO) V OL -- 0 . 4 V High-level Input Voltage (XTI) V IH 2.8 - - V Low-level Input Voltage (XTI) V IL -- 2 . 3 V Input Leakage Current (Digital Inputs) - - 10 µA Output Leakage Current (High-Z Digital Outputs) - - 10 µA Parameters Symbol Min Typ Max Units Output Rise Time t rpo -2 0 0 -n s Output Fall Time t fpo -2 0 0 -n s
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- TYPICAL CONNECTION DIAGRAMS
37 PIO2
35 PIO3
69 SPI/I2C
70 SCPM/S
86 AIN1L+
87 AIN1L-
90 AIN1R+
91 AIN1R-
71 REQ
Figure 5. Typical Connection Diagram, Control Port Slave Mode
Figure 6. Typical Connection Diagram, Control Port Figure 7. Typical Connection Diagram, Control Port
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Figure 8. Typical Connection Diagram, Control Port Figure 9. Typical Connection Diagram, Control Port
3.1 Overview
3.2 Analog Inputs
3.2.1 Line Level Inputs
internally biased to the CMOUT voltage of 2.3 V. then the on-chip high pass filter must be disabled. Figure 10. Recommended Line Input Buffer
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the analog input is out-of-range.
3.2.2 Digital High Pass Filter
ter may be disabled via a control port register.
3.3 Analog Outputs
3.3.1 Line Level Outputs
Figure 11. Single Ended Input Figure 12. Butterworth Output Filters
3.4 Clock Generation
may be derived from an external clock source.
3.4.1 Clock Source
3.5 Serial Control Port
ter/slave mode is selected via the SCPM/S pin. connected to an external host controller.
3.5.1 SPI Bus
Figure 13. Output Mute Circuit
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3.5.1.1 SPI Master Mode
Figure 14. On exit from reset, the CS4812 asserts CS CS4812 deasserts CS and begins program execution.
3.5.1.2 SPI Slave Mode
Figure 14. Control Port Timing, SPI Master Mode AutoBoot Figure 15. Control Port Timing, SPI Slave Mode Write
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- If data is written to the serial control port output
should continue to shift out this new byte.
- If data is placed in the SCP output register by the
ting the INCR bit in the MAP byte. Figure 18. SPI Slave Mode Read Flow Diagram Figure 19. SPI Slave Mode Read from DSP Core
following that designated in the MAP.
3.5.2 I 2C Bus
consists of 3 digital signals, SCL, SDA and REQ . CS4812 is configured for master mode. quest communication with the master.
3.5.2.1 I 2C Master Mode
Figure 20. Control Port Timing, I2C Master Mode AutoBoot
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3.5.2.2 I 2C Slave Mode
to be written to the register designated by the MAP. sends a stop condition to complete the transaction. Figure 22. Control Port Timing, I2C Slave Mode Write Figure 23. Control Port Timing, I2C Slave Mode Read Figure 21. I2C Slave Mode Write Flow Diagram
the address of the control register to be accessed. the contents of this register to the host controller.
- The REQ line will be de-asserted immediately
by the bus master, thus completing the transfer.
- If data is written to the SCP output register prior
- If data is placed in the SCP output register by the
ting the INCR bit in the MAP byte. Figure 24. I2C Slave Mode Read Flow Diagram
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3.6 Boot Modes
3.6.1 AutoBoot
2C or SPI serial bus interface.
3.6.2 HostBoot
Figure 25. I2C Slave Mode Read from DSP Core
AN195 for an example of a host boot sequence.
3.7 Resets
DSP automatically executes a soft reset. Figure 26. HostBoot Flow Diagram
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- POWER SUPPLY AND GROUNDING
verely degrade overall system performance. wide as possible to maintain low impedance. Figure 27. CS4812 Suggested Layout
Figure 28. Pin Assignments
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Power: analog supply, +5V. AGND - Analog Ground Ground: analog ground. VD - Digital Power Power: digital supply, +5V. DGND - Digital Ground Ground: digital ground. Analog Inputs AINL+/-,AINR+/- - Differential Analog Inputs Inputs: These pins accept differential analog input signals and are internally biased to the reference voltage of 2.3 V. The + and - input signals should be 180 ° out of phase. A single-ended signal may also be directly applied to either the + or - input with the other input AC coupled to ground through a capacitor. In general, differential input signals provide better performance. For best audio performance, a passive anti-aliasing filter is required. The typical connection diagram in Figure 5. shows the recommended single-ended input circuit. Figure 10 shows the recommended differential input circuit. Inputs may be externally AC or DC coupled. This permits use of the ADCs for input of audio signals or for measurement of DC control voltages. By default, an internal high pass filter removes any DC offsets from both of the ADC inputs. If measurement of DC is required on either of the ADC inputs, then the internal high pass filter must be disabled. Analog audio input signals that are DC coupled must be biased at 2.3 V to maintain proper input signal swing. DC control input voltages may range from ground to Vcc and should be applied to only the + or - input with the other input coupled to ground through a capacitor. OVL - ADC Overload Indicator Output: This pin is asserted if either ADC is clipping. The pin does not latch and de-asserts when clipping stops. Analog Outputs AOUT1+/-, AOUT2+/- - Differential Audio Outputs Outputs: These pins output differential analog signals which are biased to the internal reference voltage of approximately 2.3V. The + and - output signals are 180 ° out of phase resulting in a nominal differential output voltage of twice the output pin voltage. For best performance, an anti-imaging filter is required. Figure 12 shows the recommended second and third order Butterworth differential-to-single- ended output buffer circuits. Voltage Reference CMOUT - Common Mode Output Output: This pin provides an internally generated reference of 2.3V to be used for biasing external analog circuitry. The load on CMOUT must be DC only, with an impedance of not less than 50 k Ω. CMFILT+,CMFILT- - Common Mode Filter Connections Inputs: These pins are connections for external filter components required by the internal common mode reference circuit. See the typical connection diagram in Figure 5. for details.
SCPM/S - Serial Control Port Master/Slave Select Input: This pin configures the serial control port as a master if tied to VD or a slave if tied to DGND. SPI/I2C - Serial Control Port Format Select Input: This pin configures the control port for I 2C format if tied to VD or SPI format if tied to DGND. SCL/CCLK - Serial Control Port Clock Bidirectional: This pin clocks serial control port data into and out of SDA in I 2C mode. In SPI mode, it clocks control port data into CDIN and out of CDOUT. When the serial control port is configured as a master, SCL/CCLK is an output and is generated internally. When the serial control port is configured as a slave, SCL/CCLK is an input and may operate asynchronously to the master clock. AD0/CS - I2C Address Bit 0 / SPI Chip Select Bidirectional: In I 2C® mode, AD0 is an input and defines bit 0 of the partial chip address. The upper 5 bits of the 7-bit address must be 00100. In SPI mode, CS is the chip select pin. When the serial control port is defined as a master in SPI mode, CS is an output. When the serial control port is defined as a slave in SPI mode, CS is an input. AD1/CDIN - I2C Address Bit 1 / SPI Data Input Input: In I 2C® mode, AD1 is an input and defines bit 1 of the partial chip address. The upper 5 bits of the 7-bit address must be 00100. In SPI mode, CDIN is the serial control port data input and is clocked in on the rising edge of CCLK. SDA/CDOUT - I2C Data / SPI Data Output Bidirectional: In I 2C® mode, SDA is the bidirectional data I/O line. In SPI mode, CDOUT is the serial control port data output and is clocked out on the falling edge of CCLK. REQ - DSP Output Request Output: This pin is used when the serial control port is configured for slave mode operation. This pin is asserted when the DSP has written a byte to a register in the control port. When this register is read by the master device, REQ is de-asserted. Clock and Crystal XTI, XTO - Crystal Oscillator Connections (Master Clock) Input, Output: These pins provide connections for an external parallel resonant quartz crystal. Alternately, an external clock source may be applied to XTI. The clock frequency must be 256xFs. CLKOUT - Clock Output Output: This pin provides a clock output which can be used to synchronize external components. Available output frequencies 1xFs, 128xFs and 256xFs are selectable via a control port register. The default frequency is 256xFs. It is recommended to externally buffer this signal with a CMOS gate as shown in Figure 5. Miscellaneous PIO0:3 - General Purpose Inputs/Outputs Bidirectional: These pins are general-purpose digital I/O pins. The Default state is input. The functionality of these pins after boot-up is determined by the application firmware code loaded into the device during the boot-up process. RST - Reset Input: This pin causes the device to enter a low power mode and forces all control port and i/o registers to be reset to their default values. The control port can not be accessed when reset is low.
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Input: These pins are not internally connected and should be tied to ground for optimal performance. RES-NC - Reserved, No Connect These pins are reserved and must be left unconnected for normal operation. RES-VD - Reserved, Connect to VD These pins are reserved and must be tied to VD for normal operation. RES-DGND - Reserved, Connect to DGND These pins are reserved and must be tied to digital ground for normal operation. RES-AGND - Reserved, Connect to AGND These pins are reserved and must be tied to analog ground for normal operation.
- PARAMETER DEFINITIONS Dynamic Range The ratio of the full scale RMS value of the signal to the RMS sum of all other spectral components over the specified bandwidth. Dynamic range is a signal-to-noise measurement over the specified bandwidth made with a -60 dbFs signal. 60 dB is then added to the resulting measurement to refer the measurement to full scale. This technique ensures that the distortion components are below the noise level and do not effect the measurement. This measurement technique has been accepted by the Audio Engineering Society, AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307. Total Harmonic Distortion + Noise The ratio of the RMS value of the signal to the RMS sum of all other spectral components over the specified bandwidth (typically 20 Hz to 20 kHz), including distortion components. Expressed in decibels. ADCs are measured at -1dBFs as suggested in AES 17-1991 Annex A. Idle Channel Noise / Signal-to-Noise-Ratio The ratio of the RMS analog output level with 1kHz full scale digital input to the RMS analog output level with all zeros into the digital input. Measured A-weighted over a 10 Hz to 20 kHz bandwidth. Units in decibels. This specification has been standardized by the Audio Engineering Society, AES17-1991, and referred to as Idle Channel Noise. This specification has also been standardized by the Electronic Industries Association of Japan, EIAJ CP-307, and referred to as Signal-to-Noise-Ratio. Total Harmonic Distortion (THD) THD is the ratio of the test signal amplitude to the RMS sum of all the in-band harmonics of the test signal. Units in decibels. Interchannel Isolation A measure of crosstalk between channels. Measured for each channel at the converter ’s output with no signal to the input under test and a full-scale signal applied to the other channel. Units in decibels. Frequency Response A measure of the amplitude response variation from 20Hz to 20kHz relative to the amplitude response at 1kHz. Units in decibels. Interchannel Gain Mismatch For the ADCs, the difference in input voltage that generates the full scale code for each channel. For the DACs, the difference in output voltages for each channel with a full scale digital input. Units are in decibels. Gain Error The deviation from the nominal full scale output for a full scale input. Gain Drift The change in gain value with temperature. Units in ppm/ °C. Offset Error For the ADCs, the deviation in LSBs of the output from mid-scale with the selected input grounded. For the DACs, the deviation of the output from zero (relative to CMOUT) with mid-scale input code. Units are in volts.
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- PACKAGE DIMENSIONS INCHES MILLIMETERS DIM MIN MAX MIN MAX A1 0.010 0.014 0.250 0.350 B 0.009 0.015 0.220 0.380 D 0.667 0.687 16.950 17.450 D1 0.547 0.555 13.900 14.100 E 0.904 0.923 22.950 23.450 E1 0.783 0.791 19.900 20.100 e* 0.022 0.030 0.550 0.750 L 0.018 0.030 0.450 0.750 * Nominal pin pitch is 0.65 mm Controlling dimension is mm. JEDEC Designation: MS022 100L MQFP PACKAGE DRAWING E D1D e L B A
- Notes •