CS43L42 CIRRUS | Alldatasheet

Document overview

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Technical content

Features

‰1.8 to 3.3 Volt supply ‰24-Bit conversion / 96 kHz sample rate ‰96 dB dynamic range at 3 V supply ‰-85 dB THD+N ‰Low power consumption ‰Digital volume control

  • 96 dB attenuation, 1 dB step size ‰Digital bass and treble boost
  • Selectable corner frequencies
  • Up to 12 dB boost in 1 dB increments ‰Peak signal limiting to prevent clipping ‰De-emphasis for 32 kHz, 44.1 kHz, and 48 kHz ‰Headphone amplifier
  • up to 25 mWrms power output into 16 Ω load*
  • 25 dB analog attenuation and mute
  • Zero crossing click free level transitions ‰ATAPI mixing functions ‰24-Pin TSSOP package * 1 kHz sine wave at 3.3V supply

Description

The CS43L42 is a complete stereo digital-to-analog out- put system including interpolation, 1-bit D/A conversion, analog filtering, volume control, line level outputs, and a headphone amplifier, in a 24-pin TSSOP package. The CS43L42 is based on delta-sigma modulation, where the modulator output controls the reference volt- age input to an ultra-linear analog low-pass filter. This architecture allows infinite adjustment of the sample rate between 2 kHz and 100 kHz simply by changing the master clock frequency. The CS43L42 contains on-chip digital bass and treble boost, peak signal limiting, and de-emphasis. The CS43L42 operates from a +1.8 V to +3.3 V supply and consumes only 16 mW of power with a 1.8 V supply with the line amplifier powered-down. These features are ideal for portable CD, MP3 and MD players and other portable playback systems that require extremely low power consumption.

ORDERING INFORMATION

-10 to 70 °C 24-pin TSSOP CS43L42-KZZ, Lead Free -10 to 70 °C 24-pin TSSOP CDB43L42 Evaluation Board SCL/CCLK/DIF1 SDA/CDIN/DIF0 AD0/CS/DEM0 MUTEC Control Port Digital Volume Control Bass/Treble Boost Limiting Analog Filter Analog Filter HP_A HP_B AOUTA AOUTB RST LRCK SCLK/DEM1 SDATA Serial Port De-emphasis Digital Filters DAC DAC Headphone Amplifier External Mute Control Analog Volume Control MCLK Analog Volume Control Line Amplifier Compensation Gain VA_HP VA_LINE VA VL GND VQ_HP FILT+ REF_GND VQ_LINE CS43L42 Low Voltage, Stereo DAC with Headphone Amp Sep ‘04 DS481PP2

SWITCHING CHARACTERISTICS - CONTROL PORT - TWO-WIRE MODE12

4.2 Channel A Analog Headphone Attenuation Control (address 02h) (HVOLA)18

4.3 Channel B Analog Headphone Attenuation Control (address 03h) (hVOLB)18

Contacting Cirrus Logic Support For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at: http://www.cirrus.com/corporate/contacts/ I2C is a registered trademark of Philips Semiconductors. Preliminary product information describes products which are in production, but for which full characterization data is not yet available. Advance product infor- mation describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty of any kind (express or implied). No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, nor for infringements of patents or other rights of third parties. This document is the property of Cirrus Logic, Inc. and implies no license under patents, copyrights, trademarks, or trade secrets. No part of this publication may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc. Items from any Cirrus Logic website or disk may be printed for use by the user. However, no part of the printout or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc.Furthermore, no part of this publication may be used as a basis for manufacture or sale of any items without the prior written consent of Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trade- marks and service marks can be found at http://www.cirrus.com.

  1. CHARACTERISTICS/SPECIFICATIONS ANALOG CHARACTERISTICS (TA = 25° C; Logic "1" = VL = 1.8 V; Logic "0" = GND = 0 V; Full-Scale Output Sine Wave, 997 Hz; MCLK = 12.288 MHz; Measurement Bandwidth 10 Hz to 20 kHz, unless oth- erwise specified; Fs for Base-rate Mode = 48 kHz, SCLK = 3.072 MHz. Fs for High-Rate Mode = 96 kHz, SCLK = 6.144 MHz. Test load RL = 10 kΩ, CL = 10 pF (see Figure 17) for line out, RL = 16 Ω, CL = 10 pF (see Fig- ure 18) for headphone out). Notes: One-half LSB of triangular PDF dither is added to data. Parameter Base-rate Mode High-Rate Mode Symbol Min Typ Max Min Typ Max Unit Line Output Dynamic Performance for VA = VA_LINE = 1.8 V Dynamic Range (Note 1) 18 to 24-Bit unweighted A-Weighted 16-Bit unweighted A-Weighted TBD TBD TBD TBD dB dB dB dB Total Harmonic Distortion + Noise (Note 1) 18 to 24-Bit 0 dB -20 dB -60 dB 16-Bit 0 dB -20 dB -60 dB THD+N -80 -71 -31 -78 -69 -29 TBD -80 -69 -29 -78 -67 -27 TBD dB dB dB dB dB dB Interchannel Isolation (1 kHz) 100 100 dB Headphone Output Dynamic Performance for VA = VA_HP = 1.8 V Dynamic Range (Note 1) 18 to 24-Bit unweighted A-Weighted 16-Bit unweighted A-Weighted TBD TBD TBD TBD dB dB dB dB Total Harmonic Distortion + Noise (Note 1) 18 to 24-Bit 0 dB -20 dB -60 dB 16-Bit 0 dB -20 dB -60 dB THD+N -82 -68 -28 -80 -66 -26 TBD -85 -68 -28 -83 -66 -26 TBD dB dB dB dB dB dB Interchannel Isolation (1 kHz) dB

ANALOG CHARACTERISTICS (Continued) Parameter Base-rate Mode High-Rate Mode Symbol Min Typ Max Min Typ Max Unit Line Output Dynamic Performance for VA = VA_LINE = 3.0 V Dynamic Range. (Note 1) 18 to 24-Bit. unweighted A-Weighted 16-Bit. unweighted A-Weighted TBD TBD TBD TBD dB dB dB dB Total Harmonic Distortion + Noise. (Note 1) 18 to 24-Bit. 0 dB -20 dB -60 dB 16-Bit. 0 dB -20 dB -60 dB THD+N -85 -73 -33 -83 -71 -31 TBD -85 -73 -33 -83 -71 -31 TBD dB dB dB dB dB dB Interchannel Isolation. (1 kHz) 100 100 dB Headphone Output Dynamic Performance for VA = VA_HP = 3.0 V Dynamic Range. (Note 1) 18 to 24-Bit. unweighted A-Weighted 16-Bit. unweighted A-Weighted TBD TBD TBD TBD dB dB dB dB Total Harmonic Distortion + Noise. (Note 1) 18 to 24-Bit. 0 dB -20 dB -60 dB 16-Bit. 0 dB -20 dB -60 dB THD+N -76 -70 -30 -74 -68 -28 TBD -73 -70 -30 -71 -68 -28 TBD dB dB dB dB dB dB Interchannel Isolation. (1 kHz) dB

ANALOG CHARACTERISTICS (Continued) Notes: See Line Amplifier Gain Compensation (line) for details. Filter response is not tested but is guaranteed by design. Response is clock dependent and will scale with Fs. Note that the response plots (Figures 9-16) have been normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs. Referenced to a 1 kHz, full-scale sine wave. For Base-Rate Mode, the measurement bandwidth is 0.5465 Fs to 3 Fs. For High-Rate Mode, the measurement bandwidth is 0.577 Fs to 1.4 Fs. De-emphasis is not available in High-Rate Mode. Parameters Symbol Min Typ Max Units Analog Output Full Scale Line Output Voltage (Note 2) VFS_LINE TBD G x VA TBD Vpp Line Output Quiescent Voltage VQ_LINE 0.5 x VA_LINE VDC Full Scale Headphone Output Voltage VFS_HP TBD 0.55 x VA TBD Vpp Headphone Output Quiescent Voltage VQ_HP 0.5 x VA_HP VDC Interchannel Gain Mismatch 0.1 dB Gain Drift 100 ppm/°C Maximum Line Output AC-Current VA=VA_LINE=1.8 V VA=VA_LINE=3.0 V ILINE 0.1 0.15 mA mA Maximum Headphone Output VA=VA_HP=1.8 V AC-Current VA=VA_HP=3.0 V IHP mA mA Parameter Base-rate Mode High-Rate Mode Symbol Min Typ Max Min Typ Max Unit Combined Digital and On-chip Analog Filter Response (Note 3) Passband (Note 4) to -0.05 dB corner to -0.1 dB corner to -3 dB corner .4535 .4998 .4426 .4984 Fs Fs Fs Frequency Response 10 Hz to 20 kHz (Note 5) -.02 +.08 +0.11 dB StopBand .5465 .577 Fs StopBand Attenuation (Note 6) dB Group Delay tgd 9/Fs 4/Fs s Passband Group Delay Deviation 0 - 40 kHz 0 - 20 kHz ±0.36/Fs ±1.39/Fs ±0.23/Fs s s De-emphasis Error Fs = 32 kHz (Relative to 1 kHz) Fs = 44.1 kHz Fs = 48 kHz +.2/-.1 +.05/-.14 +0/-.22 (Note 7) dB dB dB

POWER AND THERMAL CHARACTERISTICS (GND = 0 V; All voltages with respect to ground. All measurements taken with all zeros input and open outputs, unless otherwise specified.) Notes: Power Down Mode is defined as RST = LO with all clocks and data lines held static. Valid with the recommended capacitor values on FILT+, VQ_LINE and VQ_HP as shown in Figure 6. Increasing the capacitance will also increase the PSRR. Note that care should be taken when selecting capacitor type, as any leakage current in excess of 1.0 µA will cause degradation in analog performance. Parameters Symbol Min Typ Max Units Power Supplies Power Supply Current- VA=1.8 V Normal Operation VA_HP=1.8 V VA_LINE=1.8 V VL=1.8 V IA IA_HP IA_LINE ID_L 7.3 1.5 1.6 mA mA mA µA Power Supply Current- VA=1.8 V Power Down Mode (Note 8) VA_HP=1.8 V VA_LINE=1.8 V VL=1.8 V IA IA_HP IA_LINE ID_L TBD TBD TBD TBD µA µA µA µA Power Supply Current- VA=3.0 V Normal Operation VA_HP=3.0 V VA_LINE=3.0 V VL=3.0 V IA IA_HP IA_LINE ID_L 10.5 1.5 1.7 9.3 mA mA mA µA Power Supply Current- VA=3.0 V Power Down Mode (Note 8) VA_HP=3.0 V VA_LINE=3.0 V VL=3.0 V IA IA_HP IA_LINE ID_L TBD TBD TBD TBD µA µA µA µA Total Power Dissipation- All Supplies=1.8 V Normal Operation All Supplies=3.0 V TBD TBD mW mW Maximum Headphone Power Dissipation (1 kHz full-scale sine wave VA=1.8 V into 16 ohm load) VA=3.0 V TBD TBD mW mW Package Thermal Resistance θJA °C/Watt Power Supply Rejection Ratio (Note 9) (1 kHz) (60 Hz) PSRR dB dB

DIGITAL CHARACTERISTICS (TA = 25° C; VL = 1.7 V - 3.6 V; GND = 0 V) ABSOLUTE MAXIMUM RATINGS (GND = 0V; all voltages with respect to ground.) WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. RECOMMENDED OPERATING CONDITIONS (GND = 0V; all voltages with respect to ground.) Notes: 10. To prevent clipping the outputs, VA_HPMIN is limited by the Full-Scale Output Voltage VFS_HP, where VA_HP must be 200 mV greater than VFS_HP. However, if distortion is not a concern, VA_HP may be as low as 0.9 V at any time. Parameters Symbol Min Typ Max Units High-Level Input Voltage VIH 0.7 x VL V Low-Level Input Voltage VIL 0.3 x VL V Input Leakage Current Iin ±10 µA Input Capacitance pF Maximum MUTEC Drive Capability VA=1.8 V VA=3.0 V TBD mA mA MUTEC High-Level Output Voltage VA V MUTEC Low-Level Output Voltage V Parameters Symbol Min Max Units DC Power Supplies: Positive Analog Headphone Line Digital I/O VA VA_HP VA_LINE VL -0.3 -0.3 -0.3 -0.3 4.0 4.0 4.0 4.0 V V V V Input Current, Any Pin Except Supplies Iin ±10 mA Digital Input Voltage VIND -0.3 VL+0.4 V Ambient Operating Temperature (power applied) TA -55 125 Storage Temperature Tstg -65 150 Parameters Symbol Min Typ Max Units Ambient Temperature TA -10 DC Power Supplies: Positive Analog Headphone (Note 10) Line Digital I/O VA VA_HP VA_LINE VL 1.7 0.9 VA 1.7 3.6 3.6 3.6 3.6 V V V V

SWITCHING CHARACTERISTICS (TA = -10 to 70° C; VL = 1.7 V - 3.6 V; Inputs: Logic 0 = GND, Logic 1 = VL, CL = 20 pF) Notes: 11. Internal SCLK Mode timing is not tested, but is guaranteed by design. 12. In Internal SCLK Mode, the LRCK duty cycle must be 50% +/− 1/2 MCLK Period. Parameters Symbol Min Typ Max Units Input Sample Rate Base Rate Mode High Rate Mode Fs Fs 100 kHz kHz MCLK Pulse Width High MCLK/LRCK = 1024 ns MCLK Pulse Width Low MCLK/LRCK = 1024 ns MCLK Pulse Width High MCLK/LRCK = 768 ns MCLK Pulse Width Low MCLK/LRCK = 768 ns MCLK Pulse Width High MCLK/LRCK = 512 ns MCLK Pulse Width Low MCLK/LRCK = 512 ns MCLK Pulse Width High MCLK / LRCK = 384 or 192 ns MCLK Pulse Width Low MCLK / LRCK = 384 or 192 ns MCLK Pulse Width High MCLK / LRCK = 256 or 128 ns MCLK Pulse Width Low MCLK / LRCK = 256 or 128 ns External SCLK Mode LRCK Duty Cycle (External SCLK only) SCLK Pulse Width Low tsclkl ns SCLK Pulse Width High tsclkh ns SCLK Period Base Rate Mode tsclkw ns High Rate Mode tsclkw ns SCLK rising to LRCK edge delay tslrd ns SCLK rising to LRCK edge setup time tslrs ns SDATA valid to SCLK rising setup time tsdlrs ns SCLK rising to SDATA hold time tsdh ns Internal SCLK Mode (Note 11) LRCK Duty Cycle (Internal SCLK only) (Note 12) SCLK Period tsclkw ns SCLK rising to LRCK edge tsclkr µs SDATA valid to SCLK rising setup time tsdlrs ns SCLK rising to SDATA hold time Base Rate Mode tsdh ns High Rate Mode tsdh ns 128 )Fs )Fs SCLK tsclkw 512 )Fs 512 )Fs 384 )Fs

The Two-Wire Mode is compatible with the I2C protocol. Data must be held for sufficient time to bridge the transition time, tfc, of SCL. Figure 4. Control Port Timing - Two-Wire Mode

tspi only needed before first falling edge of CS after RST rising edge. tspi = 0 at all other times. Data must be held for sufficient time to bridge the transition time of CCLK. Figure 5. Control Port Timing - SPI Mode

  1. TYPICAL CONNECTION DIAGRAM

Figure 6. Typical Connection Diagram

  1. REGISTER QUICK REFERENCE Addr Function Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved default Power and Muting Control AMUTE SZC1 SZC0 POR PDNHP PDNLN PDN Reserved default Channel A Analog Headphone Attenuation Control HVOLA7 HVOLA6 HVOLA5 HVOLA4 HVOLA3 HVOLA2 HVOLA1 HVOLA0 default Channel B Analog Headphone Attenuation Control HVOLB7 HVOLB6 HVOLB5 HVOLB4 HVOLB3 HVOLB2 HVOLB1 HVOLB0 default Channel A Digital Volume Control DVOLA7 DVOLA6 DVOLA5 DVOLA4 DVOLA3 DVOLA2 DVOLA1 DVOLA0 default Channel B Digital Volume Control DVOLB7 DVOLB6 DVOLB5 DVOLB4 DVOLB3 DVOLB2 DVOLB1 DVOLB0 default Tone Control BB3 BB2 BB1 BB0 TB3 TB2 TB1 TB0 default Mode Control BBCF1 BBCF0 TBCF1 TBCF0 A=B DEM1 DEM0 VCBYP default Limiter Attack Rate ARATE7 ARATE6 ARATE5 ARATE4 ARATE3 ARATE2 ARATE1 ARATE0 default Limiter Release Rate RRATE7 RRATE6 RRATE5 RRATE4 RRATE3 RRATE2 RRATE1 RRATE0 default Ah Volume and Mixing Control TC1 TC0 TC_EN LIM_EN ATAPI3 ATAPI2 ATAPI1 ATAPI0 default Bh Mode Control 2 MCLKDIV LINE1 LINE0 Reserved Reserved DIF2 DIF1 DIF0 default
  1. REGISTER DESCRIPTION Note: All registers are read/write in Two-Wire mode and write only in SPI, unless otherwise noted.

4.1 Power and Muting Control (address 01h)

4.1.1 AUTO-MUTE (AMUTE)

Default = 1 0 - Disabled 1 - Enabled Function: The Digital-to-Analog converter output will mute following the reception of 8192 consecutive audio sam- ples of static 0 or -1. A single sample of non-static data will release the mute. Detection and muting is done independently for each channel. The quiescent voltage on the output will be retained and the Mute Control pin will go active during the mute period. The muting function is affected, similar to volume control changes, by the Soft and Zero Cross bits in the Power and Muting Control register.

4.1.2 SOFT RAMP AND ZERO CROSS CONTROL (SZC)

Default = 10 00 - Immediate Change 01 - Zero Cross Digital and Analog 10 - Ramped Digital and Analog 11 - Reserved Function: Immediate Change When Immediate Change is selected all level changes will take effect immediately in one step. Zero Cross Digital and Analog Zero Cross Enable dictates that signal level changes, either by attenuation changes or muting, will occur on a signal zero crossing to minimize audible artifacts. The requested level change will occur after a timeout period of 512 sample periods (10.7 ms at 48 kHz sample rate) if the signal does not encounter a zero crossing. The zero cross function is independently monitored and implemented for each channel. Ramped Digital and Analog Soft Ramp allows digital level changes, both muting and attenuation, to be implemented by incrementally ramping, in 1/8 dB steps, from the current level to the new level at a rate of 1 dB per 8 left/right clock pe- riods. Analog level changes will occur in 1 dB steps on a signal zero crossing. The analog level change will occur after a timeout period of 512 sample periods (10.7 ms at 48 kHz sample rate) if the signal does not encounter a zero crossing. The zero cross function is independently monitored and implemented for each channel. Note: Ramped Digital and Analog is not available in High-Rate Mode. AMUTE SZC1 SZC0 POR PDNHP PDNLN PDN RESERVED

4.1.3 POPGUARD® TRANSIENT CONTROL (POR)

Function: The PopGuard® Transient Control allows the quiescent voltage to slowly ramp to and from 0 volts to the quiescent voltage during power-on or power-off when this function is enabled. Please see section 6.5 for implementation details.

4.1.4 POWER DOWN HEADPHONE AMPLIFIER (PDNHP)

Default = 0 0 - Disabled 1 - Enabled Function: The headphone amplifier will independently enter a low-power state when this function is enabled.

4.1.5 POWER DOWN LINE AMPLIFIER (PDNLN)

Default = 0 0 - Disabled 1 - Enabled Function: The line output amplifier will independently enter a low-power state when this function is enabled.

4.1.6 POWER DOWN (PDN)

Default = 1 0 - Disabled 1 - Enabled Function: The entire device will enter a low-power state when this function is enabled, and the contents of the control registers are retained in this mode. The power-down bit defaults to ‘enabled’ on power-up and must be disabled before normal operation will begin.

4.2 Channel A Analog Headphone Attenuation Control (address 02h) (HVOLA)

4.3 Channel B Analog Headphone Attenuation Control (address 03h) (hVOLB)

The Analog Headphone Attenuation only affects the headphone outputs.

4.4 Channel A Digital Volume Control (address 04h) (DVOLA)

4.5 Channel B Digital Volume Control (address 05h) (DVOLB)

from +18 to -96 dB. Volume settings are decoded using a 2’s complement code, as shown in Table 2. ATAPI bits (see Section 4.10.4). register to values greater than +18 dB will cause distortion in the audio outputs. Table 1. Example Analog Volume Settings

4.6 Tone Control (address 06h)

4.6.1 BASS BOOST LEVEL (BB)

+12 dB are interpreted as +12 dB.

4.6.2 TREBLE BOOST LEVEL (TB)

+12 dB are interpreted as +12 dB. Treble Boost is not available in High-Rate Mode. Table 2. Example Digital Volume Settings Table 3. Example Bass Boost Settings Table 4. Example Treble Boost Settings

4.7 Mode Control (address 07h)

4.7.1 BASS BOOST CORNER FREQUENCY (BBCF)

Default = 00 00 - 50 Hz 01 - 100 Hz 10 - 200 Hz 11 - Reserved Function: The bass boost corner frequency is user selectable as shown above.

4.7.2 TREBLE BOOST CORNER FREQUENCY (TBCF)

Default = 00 00 - 2 kHz 01 - 4 kHz 10 - 7 kHz 11 - Reserved Function: The treble boost corner frequency is user selectable as shown above. Note: Treble Boost is not available in High-Rate Mode.

4.7.3 CHANNEL A VOLUME = CHANNEL B VOLUME (A=B)

Default = 0 0 - Disabled 1 - Enabled Function: The AOUTA/HP_A and AOUTB/HP_B volume levels are independently controlled by the A and the B Channel Volume Control Bytes when this function is disabled. The volume on both AOUTA/HP_A and AOUTB/HP_B are determined by the A Channel Attenuation and Volume Control Bytes, and the B Chan- nel Bytes are ignored when this function is enabled. BBCF1 BBCF0 TBCF1 TBCF0 A=B DEM1 DEM0 VCBYP

4.7.4 DE-EMPHASIS CONTROL (DEM)

De-emphasis is not available in High-Rate Mode.

4.7.5 DIGITAL VOLUME CONTROL BYPASS (VCBYP)

tenuation control will remain functional.

4.8 Limiter Attack Rate (address 08h) (ARATE)

A value of zero in this register is not recommended, as it will induce erratic behavior of the limiter. Use the LIM_EN bit to disable the limiter function (see Peak Signal Limiter Enable (LIM_EN)). Table 5. Example Limiter Attack Rate Settings

4.9 Limiter Release Rate (address 09h) (RRATE)

A value of zero in this register is not recommended, as it will induce erratic behavior of the limiter. Use the LIM_EN bit to disable the limiter function (see Peak Signal Limiter Enable (LIM_EN)).

4.10 Volume and Mixing Control (address 0Ah)

4.10.1 TONE CONTROL MODE (TC)

The Tone Control Mode bits determine how the Bass Boost and Treble Boost features are configured. when these bits are set to ‘00’. Alternately, one of three pre-defined settings may be used.

4.10.2 TONE CONTROL ENABLE (TC_EN)

The Bass Boost and Treble Boost features are active when this function is enabled. Table 6. Example Limiter Release Rate Settings

4.10.3 PEAK SIGNAL LIMITER ENABLE (LIM_EN)

The CS43L42 will limit the maximum signal amplitude to prevent clipping when this function is enabled. is determined by the Limiter Release Rate register. Note: The A=B bit should be set to ‘1’ for optimal limiter performance.

4.10.4 ATAPI CHANNEL MIXING AND MUTING (ATAPI)

ble 7 and Figure 31 for additional information. All mixing functions occur prior to the digital volume control. Table 7. ATAPI Decode

4.11 Mode Control 2 (address 0Bh)

4.11.1 MASTER CLOCK DIVIDE ENABLE (MCLKDIV)

Default = 0 0 - Disabled 1 - Enabled Function: The MCLKDIV bit enables a circuit which divides the externally applied MCLK signal by 2 prior to all other internal circuitry. Note: Internal SCLK is not available when this function is enabled.

4.11.2 LINE AMPLIFIER GAIN COMPENSATION (LINE)

Default = 00 00 - 0.785 x VA 01 - 0.943 x VA 10 - 1.571 x VA 11 - Line Mute Function: The Line Amplifier Gain Compensation bits allow the user to scale the full-scale line output level according to the power supply voltage used. The full-scale line output level will be equal to {gain factor}xVA, where {gain factor} is selected from options above. For example, if the user wants the full-scale line output volt- age to be 1 VRMS (2.8 VPP) with VA = 1.8 VDC and VA_LINE = 3.0 VDC, then the gain factor would be 1.571. Note: It is possible to exceed the maximum output level, limited by VA_LINE, by incorrectly setting the gain compensation factor. The Line Mute option is available to allow muting of the line output when the headphone output is still in use and the line amp is still powered up. To use this feature, first mute the outputs via the ATAPI bits. Next, set the LINE GAIN to Line Mute. Finally, un-mute the outputs with the ATAPI bits. Following these steps will ensure a click free mute.

4.11.3 DIGITAL INTERFACE FORMAT (DIF)

Default = 000 - Format 0 (I2S, up to 24-bit data, 64 x Fs Internal SLCK) Function: The required relationship between the Left/Right clock, serial clock and serial data is defined by the Digital Interface Format and the options are detailed in Figures 19-25. Note: Internal SCLK is not available when MCLKDIV is enabled. MCLKDIV LINE1 LINE0 RESERVED RESERVED DIF2 DIF1 DIF0

I2S, up to 24-bit data, 64 x Fs Internal SLCK I2S, up to 24-bit data, 32 x Fs Internal SLCK Left Justified, up to 24-bit data, Right Justified, 24-bit data Right Justified, 20-bit data Right Justified, 16-bit data Right Justified, 18-bit data Identical to Format 1 Table 8. Digital Interface Format

  1. PIN DESCRIPTION RST Reset (Input) - The device enters a low power mode and all internal registers are reset to their default settings, including the control port, when low. When high, the control port becomes operational and the PDN bit must be cleared before normal operation will occur. The control port cannot be accessed when Reset is low. LRCK Left/Right Clock (Input) - Determines which channel is currently being input on the serial audio data input, SDATA. The frequency of the Left/Right clock must be equal to the input sample rate. Audio samples in Left/Right sample pairs will be simultaneously output from the digital-to-analog converter whereas Right/Left pairs will exhibit a one sample period dif- ference. The required relationship between the Left/Right clock, serial clock and serial data is defined by the Mode Control 2 (0Bh) register when in Control Port Mode or by the DIF1-0 pins when in Stand-Alone mode. The options are detailed in Figures 19-29. SDATA Serial Audio Data (Input) - Two's complement MSB-first serial data is input on this pin. The data is clocked into SDATA via the serial clock and the channel is determined by the Left/Right clock. The required relationship between the Left/Right clock, serial clock and serial data is defined by the Mode Control 2 (0Bh) register when in Control Port Mode or by the DIF1-0 pins when in Stand-Alone mode. The options are detailed in Figures 19-29. AD0/CS (Control Port Mode) Address Bit / Chip Select (Input) - In Two-Wire mode, AD0 is a chip address bit. CS is used to enable the control port interface in SPI mode. The device will enter the SPI mode anytime a high to low transition is detected on this pin. Once the device has entered the SPI mode, it will remain in SPI mode until either the part is reset or power is removed. SCLK Serial Clock (Input) - Clocks the individual bits of the serial data into the SDATA pin. The required relationship between the Left/Right clock, serial clock and serial data is defined by the Mode Control 2 (0Bh) register when in Control Port Mode or by the DIF1-0 pins when in Stand-Alone mode. The options are detailed in Figures 19-29. The CS43L42 supports both internal and external serial clock generation modes. The Inter- nal Serial Clock Mode eliminates possible clock interference from an external SCLK. Use of the Internal Serial Clock Mode is always preferred. Internal Serial Clock Mode - In the Internal Serial Clock Mode, the serial clock is internally derived and synchronous with the master clock and left/right clock. The SCLK/LRCK fre- quency ratio is either 32, 48, or 64 depending upon the Mode Control 2 (0Bh) register when in Control Port Mode or the DIF1-0 pins when in Stand-Alone mode as shown in Figures 19-29. Operation in this mode is identical to operation with an external serial clock synchro- nized with LRCK. External Serial Clock Mode - The CS43L42 will enter the External Serial Clock Mode when- ever 16 low to high transitions are detected on the SCLK pin during any phase of the LRCK period. The device will revert to Internal Serial Clock Mode if no low to high transitions are detected on the SCLK pin for 2 consecutive periods of LRCK. Reset RST MUTEC Mute Control Left/Right Clock LRCK AOUTA Analog Output A Serial Data SDATA AOUTB Analog Output B AD0/CS/DEM0 AD0/CS/DEM0 HP_B Headphone Output B Serial Clock/DEM1 SCLK/DEM1 VA_HP Headphone Amp Power Interface Power VL VA_LINE Line Amp Power Master Clock MCLK VA Analog Power SCL/CCLK/DIF1 SCL/CCLK/DIF1 GND Ground SDA/CDIN/DIF0 SDA/CDIN/DIF0 HP_A Headphone Output A No Connection N.C. VQ_LINE Line Out Quiescent Voltage Mode Select CP/SA FILT+ Positive Voltage Reference HP Quiescent Voltage VQ_HP REF_GND Reference Ground

(Stand-Alone Mode) 4 and 5 De-emphasis Control (Input) - Selects the appropriate digital filter to maintain the standard 15 µs/50 µs digital de-emphasis filter response at 32, 44.1 or 48 kHz sample rates. (see Fig- ure 30) When using Internal Serial Clock Mode, Pin 5 is available for de-emphasis control, DEM1, and all de-emphasis filters are available. When using External Serial Clock Mode, Pin 5 is not available for de-emphasis use and only the 44.1 kHz de-emphasis filter is avail- able. (see Table 9) Note: De-emphasis is not available in High-Rate Mode. VL Interface Power (Input) - Digital interface power supply. Typically 1.8 to 3.3 VDC. MCLK Master Clock (Input) - Frequency must be either 256x, 384x, 512x, 768x or 1024x the input sample rate in Base Rate Mode (BRM) and 128x, 192x, 256x or 384x the input sample rate in High Rate Mode (HRM). Note that some multiplication factors require setting the MCLKDIV bit (see Master Clock DIVIDE ENABLE (mclkdiv)). Tables 10 and 11 illustrate several standard audio sample rates and the required master clock frequencies. SCL/CCLK (Control Port Mode) Serial Control Interface Clock (Input) - Clocks the serial control data into or out of SDA/CDIN. SDA/CDIN (Control Port Mode) Serial Control Data I/O (Input/Output) - In Two-Wire mode, SDA is a data I/O line. CDIN is the input data line for the control port interface in SPI mode. Internal SCLK External SCLK DEM1 DEMO 44.1kHz 44.1 kHz 48kHz 32kHz Table 9. Stand Alone De-Emphasis Control

  • Requires MCLKDIV bit = 1 in Mode Control 2 register (address 0Bh).

Table 10. HRM Common Clock Frequencies

  • Requires MCLKDIV bit = 1 in Mode Control 2 register (address 0Bh).

Table 11. BRM Common Clock Frequencies

(Stand-Alone Mode) 8 and 9 Digital Interface Format (Input) - The required relationship between the Left/Right clock, serial clock and serial data is defined by the Digital Interface Format and the options are de- tailed in Figures 26-29. N.C. No Connection - This pin has no internal connection to the device. CP/SA Mode Select (Input) - The Mode Select pin is used to select control port or stand-alone mode. When high, the CS43L42 will operate in control port mode. When low, the CS43L42 will operate in stand-alone mode. VQ_HP Headphone Quiescent Voltage (Output) - Filter connection for internal headphone amp quiescent reference voltage. A capacitor must be connected from VQ_HP to analog ground, as shown in Figure 6. VQ_HP is not intended to supply external current. VQ_HP has a typ- ical source impedance of 250 kΩ and any current drawn from this pin will alter device per- formance. REF_GND Reference Ground (Input) - Ground reference for the internal sampling circuits. Must be connected to analog ground. FILT+ Positive Voltage Reference (Output) - Positive reference for internal sampling circuits. An external capacitor is required from FILT+ to analog ground, as shown in Figure 6. The rec- ommended value will typically provide 60 dB of PSRR at 1 kHz and 40 dB of PSRR at 60 Hz. FILT+ is not intended to supply external current. FILT+ has a typical source impedance of 250 kΩ and any current drawn from this pin will alter device performance. VQ_LINE Line Out Quiescent Voltage (Output) - Filter connection for internal line amp quiescent ref- erence voltage. A capacitor must be connected from VQ_LINE to analog ground, as shown in Figure 6. VQ_LINE is not intended to supply external current. VQ_LINE has a typical source impedance of 250 kΩ and any current drawn from this pin will alter device perfor- mance. HP_A and HP_B 16 and 21 Headphone Outputs (Output) - The full scale analog headphone output level is specified in the Analog Characteristics specifications table. GND Ground (Input) - Ground Reference. Should be connected to analog ground. VA Analog Power (Input) - Analog power supply. Typically 1.8 to 3.3 VDC. VA_LINE Line Amp Power (Input) - Line amplifier power supply. Typically 1.8 to 3.3 VDC. Note: If the line outputs are not used, connect VA_LINE to VA. VA_HP Headphone Amp Power (Input) - Headphone amplifier power supply. Typically 0.9 to 3.3 VDC. AOUTA and AOUTB 22 and 23 Analog Outputs (Output) - The full scale analog line output level is specified in the Analog Characteristics specifications table. MUTEC Mute Control (Output) - The Mute Control pin goes high during power-up initialization, re- set, muting, power-down or if the master clock to left/right clock frequency ratio is incorrect. This pin is intended to be used as a control for an external mute circuit on the line outputs to prevent the clicks and pops that can occur in any single supply system. Use of Mute Con- trol is not mandatory but recommended for designs requiring the absolute minimum in ex- traneous clicks and pops. DIF1 DIF0 I2S, up to 24-bit data Left Justified, up to 24-bit data Right Justified, 24-bit Data Right Justified, 16-bit Data Table 12. Digital Interface Format - DIF1 and DIF0 (Stand-Alone Mode)

  1. APPLICATIONS

6.1 Grounding and Power Supply

As with any high resolution converter, the CS43L42 requires careful attention to power sup- ply and grounding arrangements to optimize per- formance. Figure 6 shows the recommended power arrangement with VA, VA_HP, VA_LINE and VL connected to clean supplies. Decoupling capacitors should be located as close to the device package as possible. If desired, all supply pins may be con- nected to the same supply, but a decoupling capac- itor should still be used on each supply pin.

6.2 Clock Modes

The CS43L42 operates in one of two clocking modes. Base Rate Mode supports input sample rates up to 50 kHz, and High Rate Mode supports input sample rates up to 100 kHz, see Table 10 and 11. All clock modes use 64x oversampling.

6.3 De-Emphasis

The CS43L42 includes on-chip digital de-empha- sis. Figure 30 shows the de-emphasis curve for Fs equal to 44.1 kHz. The frequency response of the de-emphasis curve will scale proportionally with changes in sample rate, Fs. The de-emphasis feature is included to accommo- date older audio recordings that utilize pre-empha- sis equalization as a means of noise reduction.

6.4 Recommended Power-up Sequence

1) Hold RST low until the power supply, master clock and left/right clock are stable. In this state, the control port is reset to its default set- tings and VQ_HP and VQ_LINE will remain low. Set the CP/SA pin at this time. 2) Bring RST high. The device will remain in a low power state and latch CP/SA, and VQ_HP and VQ_LINE remain low. If CP/SA is high, the control port will be accessible at this time and the desired register settings can be loaded while keeping the PDN bit set to 1. If CP/SA is low, the device will begin the stand-alone pow- er-up sequence 3) (For Control Port Mode) Once the registers are configured as desired, set the PDN bit to 0, ini- tiating the power-up sequence. This requires approximately 50 µS when the PopGuard® Transient Control (POR) bit is set to 0. If the POR bit is set to 1, see PopGuard® Transient Control for total power-up timing.

6.5 PopGuard® Transient Control

The CS43L42 uses PopGuard® technology to min- imize the effects of output transients during pow- er-up and power-down. This technique minimizes the audio transients commonly produced by sin- gle-ended, single-supply converters when it is im- plemented with external DC-blocking capacitors connected in series with the audio outputs. When the device is initially powered-up, the audio outputs, AOUTA, AOUTB, HP_A and HP_B are clamped to GND. Following a delay of approxi- mately 1000 sample periods, each output begins to ramp toward the quiescent voltage. Approximately 10,000 left/right clock cycles later, the outputs reach VQ_LINE and VQ_HP respectively, and audio output begins. This gradual voltage ramping allows time for the external DC-blocking capacitor to charge to the quiescent voltage, minimizing the power-up transient. To prevent transients at power-down, the device must first enter its power-down state. When this oc- curs, audio output ceases and the internal output buffers are disconnected from AOUTA, AOUTB, HP_A and HP_B. In their place, a soft-start current sink is substituted which allows the DC-blocking capacitors to slowly discharge. Once this charge is dissipated, the power to the device may be turned off, and the system is ready for the next power-on.

To prevent an audio transient at the next power-on, the DC-blocking capacitors must fully discharge before turning off the power or exiting the pow- er-down state. If full discharge does not occur, a transient will occur when the audio outputs are ini- tially clamped to GND. The time that the device must remain in the power-down state is related to the value of the DC-blocking capacitance and the output load. For example, with a 220 µF capacitor and a 16 ohm load on the headphone outputs, the minimum power-down time will be approximately 0.4 seconds. Use of the Mute Control function on the line out- puts is recommended for designs requiring the ab- solute minimum in extraneous clicks and pops. Also, use of the Mute Control function can enable the system designer to achieve idle channel noise/signal-to-noise ratios only limited by the ex- ternal mute circuit. See the CDB43L42 Datasheet for a suggested mute circuit. 7. CONTROL PORT INTERFACE The control port is used to load all the internal set- tings. The operation of the control port may be completely asynchronous with the audio sample rate. However, to avoid potential interference prob- lems, the control port pins should remain static if no operation is required. The control port has 2 modes: SPI and Two-Wire, with the CS43L42 operating as a slave device. If Two-Wire operation is desired, AD0/CS should be tied to VL or GND. If the CS43L42 ever detects a high to low transition on AD0/CS after power-up, SPI mode will be selected.

7.1 SPI Mode

In SPI mode, CS is the CS43L42 chip select signal, CCLK is the control port bit clock, CDIN is the in- put data line from the microcontroller and the chip address is 0010000. All signals are inputs and data is clocked in on the rising edge of CCLK. Figure 7 shows the operation of the control port in SPI mode. To write to a register, bring CS low. The first 7 bits on CDIN form the chip address and must be 0010000. The eighth bit is a read/write indicator (R/W), which must be low to write. The next 8 bits form the Memory Address Pointer (MAP), which is set to the address of the register that is to be updat- ed. The next 8 bits are the data which will be placed into register designated by the MAP. The CS43L42 has a MAP auto increment capabili- ty, enabled by the INCR bit in the MAP register. If INCR is a zero, then the MAP will stay constant for successive writes. If INCR is set to a 1, then MAP will auto increment after each byte is written, al- lowing block writes of successive registers.

7.2 Two-Wire Mode

In Two-Wire mode, SDA is a bidirectional data line. Data is clocked into and out of the part by the clock, SCL, with the clock to data relationship as shown in Figure 8. There is no CS pin. Pin AD0 forms the partial chip address and should be tied to VL or GND as required. The upper 6 bits of the 7 bit address field must be 001000. To communicate with the CS43L42, the LSB of the chip address field, which is the first byte sent to the CS43L42, should match the setting of the AD0 pin. The eighth bit of the address byte is the R/W bit (high for a read, low for a write). If the operation is a write, the next byte is the Memory Address Pointer, MAP, which selects the register to be read or written. The MAP is then followed by the data to be written. If the operation is a read, the contents of the register pointed to by the MAP will be output after the chip address. The CS43L42 has MAP auto increment capability, enabled by the INCR bit in the MAP register. If INCR is 0, then the MAP will stay constant for suc- cessive writes. If INCR is set to 1, then MAP will auto increment after each byte is written, allowing block reads or writes of successive registers. The Two-Wire mode is compatible with the I2C protocol.

7.3 Memory Address Pointer (MAP)

7.3.1 INCR (AUTO MAP INCREMENT ENABLE)

7.3.2 MAP0-3 (MEMORY ADDRESS POINTER)

Figure 7. Control Port Timing, SPI mode Note: If operation is a write, this byte contains the M em ory A ddress Pointer, M AP. Figure 8. Control Port Timing, Two-Wire Mode

  1. PARAMETER DEFINITIONS Total Harmonic Distortion + Noise (THD+N) The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels. Dynamic Range The ratio of the full scale rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. Dynamic range is a signal-to-noise measurement over the specified bandwidth made with a -60 dBFS signal. 60 dB is then added to the resulting measurement to refer the measurement to full scale. This technique ensures that the distortion components are below the noise level and do not effect the measurement. This measurement technique has been accepted by the Audio Engineering So- ciety, AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307. Interchannel Isolation A measure of crosstalk between the left and right channels. Measured for each channel at the converter's output with all zeros to the input under test and a full-scale signal applied to the other channel. Units in decibels. Interchannel Gain Mismatch The gain difference between left and right channels. Units in decibels. Gain Error The deviation from the nominal full scale analog output for a full scale digital input. Gain Drift The change in gain value with temperature. Units in ppm/°C. 9. REFERENCES 1) "How to Achieve Optimum Performance from Delta-Sigma A/D & D/A Converters" by Steven Harris. Paper presented at the 93rd Convention of the Audio Engineering Society, October 1992. 2) CDB43L42 Evaluation Board Datasheet 3) “The I2C-Bus Specification: Version 2.0” Philips Semiconductors, December 1998. http://www.semiconductors.philips.com
  1. PACKAGE DIMENSIONS Notes: 1. “D” and “E1” are reference datums and do not included mold flash or protrusions, but do include mold mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per side. Dimension “b” does not include dambar protrusion/intrusion. Allowable dambar protrusion shall be 0.13 mm total in excess of “b” dimension at maximum material condition. Dambar intrusion shall not reduce dimension “b” by more than 0.07 mm at least material condition. These dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips. INCHES MILLIMETERS NOTE DIM MIN NOM MAX MIN NOM MAX A 0.043 1.10 0.002 0.004 0.006 0.05 0.15 0.03346 0.0354 0.037 0.85 0.90 0.95 b 0.00748 0.0096 0.012 0.19 0.245 0.30 2,3 D 0.303 0.307 0.311 7.70 7.80 7.90 E 0.248 0.2519 0.256 6.30 6.40 6.50 0.169 0.1732 0.177 4.30 4.40 4.50 e

0.026 BSC

0.65 BSC

L 0.020 0.024 0.028 0.50 0.60 0.70 JEDEC #: MO-153 Controlling Dimension is Millimeters. 24L TSSOP (4.4 mm BODY) PACKAGE DRAWING E N 1 2 3 e A D SEATING PLANE E11 L SIDE VIEW END VIEW TOP VIEW