CDB43L21

CS43L21 CIRRUS | Alldatasheet

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Technical content

Copyright © Cirrus Logic, Inc. 2006 (All Rights Reserved) http://www.cirrus.com Advance Product Information This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice. JULY '06 DS723A1 Low Power, Stereo Digital to Analog Converter

FEATURES

 98 dB Dynamic Range (A-wtd)  -86 dB THD+N  Headphone Amplifier - GND Centered On-Chip Charge Pump Provides -VA_HP No DC-Blocking Capacitor Required 46 mW Power Into Stereo 16 Ω @ 1.8 V 88 mW Power Into Stereo 16 Ω @ 2.5 V -75 dB THD+N  Digital Signal Processing Engine Bass & Treble Tone Control, De-Emphasis PCM Mix w/Independent Vol Control Master Digital Volume Control and Limiter Soft Ramp & Zero Cross Transitions  Beep Generator Tone Selections Across Two Octaves Separate Volume Control Programmable On & Off Time Intervals Continuous, Periodic or One-Shot Beep Selections  Programmable Peak-Detect and Limiter  Pop and Click Suppression SYSTEM FEATURES  24-bit Conversion  4 kHz to 96 kHz Sample Rate  Multi-bit Delta Sigma Architecture  Low Power Operation Stereo Playback: 12.93 mW @ 1.8 V  Variable Power Supplies 1.8 V to 2.5 V Digital & Analog 1.8 V to 3.3 V Interface Logic  Power Down Management  Software Mode (I²C® & SPI™ Control)  Hardware Mode (Stand-Alone Control)  Digital Routing/Mixes: Mono Mixes  Flexible Clocking Options Master or Slave Operation High-Impedance Digital Output Option (for easy MUXing between DAC and Other Data Sources) Quarter-Speed Mode - (i.e. Allows 8 kHz Fs while maintaining a flat noise floor up to 16 kHz) 1.8 V to 3.3 V Multibit ∆Σ Modulator Charge Pump Left HP Out Right HP Out Serial Audio Input 1.8 V to 2.5 V PCM Serial Interface Register Configuration Level Translator Reset Hardware Mode or I2C & SPI Software Mode Control Data Beep Generator MUX MUX Headphone Amp - GND Centered Headphone Amp - GND Centered 1.8 V to 2.5 V Switched Capacitor DAC and Filter Switched Capacitor DAC and Filter Digital Signal Processing Engine CS43L21

APPLICATIONS

 Portable Audio Players  MD Players  PDAs  Personal Media Players  Portable Game Consoles  Smart Phones  Wireless Headsets GENERAL DESCRIPTION The CS43L21 is a highly integrated, 24-bit, 96 kHz, low power stereo DAC. Based on multi-bit, delta-sigma modulation, it allows infinite sample rate adjustment be- tween 4 kHz and 96 kHz. The DAC offers many features suitable for low power, portable system applications. The DAC output path includes a digital signal process- ing engine. Tone Control provides bass and treble adjustment of four selectable corner frequencies. The Mixer allows independent volume control for PCM mix, as well as a master digital volume control for the analog output. All volume level changes may be configured to occur on soft ramp and zero cross transitions. The DAC also includes de-emphasis, limiting functions and a beep generator delivering tones selectable across a range of two full octaves. The stereo headphone amplifier is powered from a sep- arate positive supply and the integrated charge pump provides a negative supply. This allows a ground-cen- tered analog output with a wide signal swing and eliminates external DC-blocking capacitors. In addition to its many features, the CS43L21 operates from a low-voltage analog and digital core, making this DAC ideal for portable systems that require extremely low power consumption in a minimal amount of space. The CS43L21 is available in a 32-pin QFN package in both Commercial (-10 to +70° C) and Automotive grades (-40 to +85° C). The CS43L21 Customer Dem- onstration board is also available for device evaluation and implementation suggestions. Please see “Ordering Information” on page 63 for complete details.

6.7 PCMX Mixer Volume Control:

6.12 AOUTx Volume Control:

1. PIN DESCRIPTIONS - SOFTWARE (HARDWARE) MODE Pin Name Pin Description LRCK Left Right Clock (Input/Output) - Determines which channel, Left or Right, is currently active on the serial audio data line. SDA/CDIN (MCLKDIV2) Serial Control Data (Input/Output) - SDA is a data I/O in I²C Mode. CDIN is the input data line for the control port interface in SPI Mode. MCLK Divide by 2 (Input) - Hardware Mode: Divides the MCLK by 2 prior to all internal circuitry. SCL/CCLK (I²S/LJ) Serial Control Port Clock (Input) - Serial clock for the serial control port. Interface Format Selection (Input) - Hardware Mode: Selects between I²S & Left-Justified interface for- mats for the DAC. AD0/CS (DEM) Address Bit 0 (I²C) / Control Port Chip Select (SPI) (Input) - AD0 is a chip address pin in I²C Mode; CS is the chip-select signal for SPI format. De-Emphasis (Input) - Hardware Mode: Enables/disables the de-emphasis filter. VA_HP Analog Power For Headphone (Input) - Positive power for the internal analog headphone section. FLYP Charge Pump Cap Positive Node (Input) - Positive node for the external charge pump capacitor. GND_HP Analog Ground (Input) - Ground reference for the internal headphone/charge pump section. FLYN Charge Pump Cap Negative Node (Input) - Negative node for the external charge pump capacitor. VSS_HP Negative Voltage From Charge Pump (Output) - Negative voltage rail for the internal analog head- phone section. CS43L21 VD DGND TSTO(M/S) MCLK SDIN SCLK VSS_HP AOUTB AOUTA VA AGND FILT+ NIC VQ SDA/CDIN (MCLKDIV2) SCL/CCLK (I²S/LJ) ADO/CS (DEM) FLYP VL RESET GND_HP FLYN TSTO TSTO TSTO TSTO TSTO TSTO TSTO TSTO VA_HP LRCK

Analog Audio Output (Output) - The full-scale output level is specified in the DAC Analog Characteris- tics specification table VA Analog Power (Input) - Positive power for the internal analog section. AGND Analog Ground (Input) - Ground reference for the internal analog section. FILT+ Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling circuits. VQ Quiescent Voltage (Output) - Filter connection for internal quiescent voltage. NIC Not Internally Connected - This pin is not connected internal to the device and may be connected to ground or left “floating”. No other external connection should be made to this pin. TSTO Test Out (Output) - This pin is an output used for test purposes only and must be left “floating” (no con- nection external to the pin). TSTO Test Out (Output) - This pin is an output used for test purposes only and must be left “floating” (no con- nection external to the pin). TSTO Test Out (Output) - This pin is an output used for test purposes only and must be left “floating” (no con- nection external to the pin). TSTO Test Out (Output) - This pin is an output used for test purposes only and must be left “floating” (no con- nection external to the pin). TSTO Test Out (Output) - This pin is an output used for test purposes only and must be left “floating” (no con- nection external to the pin). TSTO Test Out (Output) - This pin is an output used for test purposes only and must be left “floating” (no con- nection external to the pin). RESET Reset (Input) - The device enters a low power mode when this pin is driven low. VL Digital Interface Power (Input) - Determines the required signal level for the serial audio interface and host control port. Refer to the Recommended Operating Conditions for appropriate voltages. VD Digital Power (Input) - Positive power for the internal digital section. DGND Digital Ground (Input) - Ground reference for the internal digital section. TSTO (M/S) Test Out (Output) - This pin is an output used for test purposes only and must be left “floating” (no con- nection external to the pin). Serial Port Master/Slave (Input/Output) - Hardware Mode Startup Option: Selects between Master and Slave Mode for the serial port. MCLK Master Clock (Input) - Clock source for the delta-sigma modulators. SCLK Serial Clock (Input/Output) - Serial clock for the serial audio interface. SDIN Serial Audio Data Input (Input) - Input for two’s complement serial audio data. Thermal Pad Thermal relief pad for optimized heat dissipation. See “QFN Thermal Pad” on page 59.

The logic level for each input should not exceed the maximum ratings for the VL power supply. Table 1. I/O Power Rails

1. TYPICAL CONNECTION DIAGRAMS

• *Use low ESR ceramic capacitors.

result in clipping on the audio output. Figure 1. Typical Connection Diagram (Software Mode)

internal routing applications please see the DAC Analog Output Characteristics section for loading limitations . supply (VSS_HP) and result in clipping on the audio output.

• *Use low ESR ceramic capacitors.

down to DGND for Slave Mode. Figure 2. Typical Connection Diagram (Hardware Mode)

1. CHARACTERISTIC AND SPECIFICATION TABLES (All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical per- formance characteristics and specifications are derived from measurements taken at nominal supply voltages and TA = 25° C.) SPECIFIED OPERATING CONDITIONS (AGND=DGND=0 V, all voltages with respect to ground.) ABSOLUTE MAXIMUM RATINGS (AGND = DGND = 0 V; all voltages with respect to ground.) WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. Notes: The device will operate properly over the full range of the analog, headphone amplifier, digital core and serial/control port interface supplies. Any pin except supplies. Transient currents of up to ±100 mA on the analog input pins will not cause SCR latch-up. The maximum over/under voltage is limited by the input current. Parameters Symbol Min Nom Max Units DC Power Supply (Note 1) Analog Core VA 1.65 2.37 1.8 2.5 1.89 2.63 V V Headphone Amplifier VA_HP 1.65 2.37 1.8 2.5 1.89 2.63 V V Digital Core VD 1.65 2.37 1.8 2.5 1.89 2.63 V V Serial/Control Port Interface VL 1.65 2.37 3.14 1.8 2.5 3.3 1.89 2.63 3.47 V V V Ambient Temperature Commercial - CNZ Automotive - DNZ TA -10 -40 +70 +85 Parameters Symbol Min Max Units DC Power Supply Analog Digital Serial/Control Port Interface VA, VA_HP VD VL -0.3 -0.3 -0.3 3.0 3.0 4.0 V V V Input Current (Note 2) Iin ±10 mA Digital Input Voltage (Note 3) VIND -0.3 VL+ 0.4 V Ambient Operating Temperature (power applied) TA -50 +115 Storage Temperature Tstg -65 +150

ANALOG OUTPUT CHARACTERISTICS (COMMERCIAL - CNZ) (Test conditions (unless otherwise specified): Input test signal is a full-scale 997 Hz sine wave; measurement bandwidth is 10 Hz to 20 kHz; Sample Frequency = 48 kHz; test load RL = 10 kΩ, CL = 10 pF for the line output (see Figure 3), and test load RL = 16 Ω, CL = 10 pF (see Figure 3) for the headphone output. HP_GAIN[2:0] = 011.) Parameter (Note 4) VA = 2.5V (nominal) Min Typ Max VA = 1.8V (nominal) Min Typ Max Unit RL = 10 kΩ Dynamic Range 18 to 24-Bit A-weighted unweighted 16-Bit A-weighted unweighted dB dB dB dB Total Harmonic Distortion + Noise 18 to 24-Bit 0 dB -20 dB -60 dB 16-Bit 0 dB -20 dB -60 dB -86 -75 -35 -86 -73 -33 -78 -88 -72 -32 -88 -70 -30 -82 dB dB dB dB dB dB RL = 16 Ω Dynamic Range 18 to 24-Bit A-weighted unweighted 16-Bit A-weighted unweighted dB dB dB dB Total Harmonic Distortion + Noise 18 to 24-Bit 0 dB -20 dB -60 dB 16-Bit 0 dB -20 dB -60 dB -75 -75 -35 -75 -73 -33 -69 -75 -72 -32 -75 -70 -30 -69 dB dB dB dB dB dB Other Characteristics for RL = 16 Ω or 10 kΩ Output Parameters Modulation Index (MI) (Note 5) Analog Gain Multiplier (G) 0.6787 0.6047 0.6787 0.6047 Full-scale Output Voltage (2•G•MI•VA) (Note 5) Refer to Table “Line Output Voltage Characteristics” on page 14 Vpp Full-scale Output Power (Note 5) Refer to Table “Headphone Output Power Characteristics” on page 15 mW Interchannel Isolation (1 kHz) 16 Ω 10 kΩ dB dB Interchannel Gain Mismatch 0.1 0.25 0.1 0.25 dB Gain Drift ±100 ±100 ppm/° C AC-Load Resistance (RL) (Note 6) Ω Load Capacitance (CL) (Note 6) 150 150 pF

ANALOG OUTPUT CHARACTERISTICS (AUTOMOTIVE - DNZ) (Test conditions (unless otherwise specified): Input test signal is a full-scale 997 Hz sine wave; measurement bandwidth is 10 Hz to 20 kHz; Sample Frequency = 48 kHz and 96 kHz; test load RL = 10 kΩ, CL = 10 pF for the line output (see Figure 3), and test load RL = 16 Ω, CL = 10 pF (see Figure 3) for the headphone output. HP_GAIN[2:0] = 011.) Parameter (Note 4) VA = 2.5V (nominal) Min Typ Max VA = 1.8V (nominal) Min Typ Max Unit RL = 10 kΩ Dynamic Range 18 to 24-Bit A-weighted unweighted 16-Bit A-weighted unweighted dB dB dB dB Total Harmonic Distortion + Noise 18 to 24-Bit 0 dB -20 dB -60 dB 16-Bit 0 dB -20 dB -60 dB -86 -75 -35 -86 -73 -33 -73 -88 -72 -32 -88 -70 -30 -80 dB dB dB dB dB dB RL = 16 Ω Dynamic Range 18 to 24-Bit A-weighted unweighted 16-Bit A-weighted unweighted dB dB dB dB Total Harmonic Distortion + Noise 18 to 24-Bit 0 dB -20 dB -60 dB 16-Bit 0 dB -20 dB -60 dB -75 -75 -35 -75 -73 -33 -67 -75 -72 -32 -75 -70 -30 -67 dB dB dB dB dB dB Other Characteristics for RL = 16 Ω or 10 kΩ Output Parameters Modulation Index (MI) (Note 5) Analog Gain Multiplier (G) 0.6787 0.6047 0.6787 0.6047 Full-scale Output Voltage (2•G•MI•VA) (Note 5) Refer to Table “Line Output Voltage Characteristics” on page 14 Vpp Full-scale Output Power (Note 5) Refer to Table “Headphone Output Power Characteristics” on page 15 mW Interchannel Isolation (1 kHz) 16 Ω 10 kΩ dB dB Interchannel Gain Mismatch 0.1 0.25 0.1 0.25 dB Gain Drift ±100 ±100 ppm/° C AC-Load Resistance (RL) (Note 6) Ω Load Capacitance (CL) (Note 6) 150 150 pF

LINE OUTPUT VOLTAGE CHARACTERISTICS Test conditions (unless otherwise specified): Input test signal is a full-scale 997 Hz sine wave; measurement band- width is 10 Hz to 20 kHz; Sample Frequency = 48 kHz; test load RL = 10 kΩ, CL = 10 pF (see Figure 3). Parameter VA = 2.5V (nominal) Min Typ Max VA = 1.8V (nominal) Min Typ Max Unit AOUTx Voltage Into RL = 10 kΩ HP_GAIN[2:0] Analog Gain (G) VA_HP 000 0.3959 1.8 V 1.34 0.97 Vpp 2.5 V 1.34 0.97 Vpp 001 0.4571 1.8 V 1.55 1.12 Vpp 2.5 V 1.55 1.12 Vpp 010 0.5111 1.8 V 1.73 1.25 Vpp 2.5 V 1.73 1.25 Vpp 011 (default) 0.6047 1.8 V 2.05 1.41 1.48 1.55 Vpp 2.5 V 1.95 2.05 2.15 1.48 Vpp 100 0.7099 1.8 V 2.41 1.73 Vpp 2.5 V 2.41 1.73 Vpp 101 0.8399 1.8 V 2.85 2.05 Vpp 2.5 V 2.85 2.05 Vpp 110 1.0000 1.8 V 3.39 2.44 Vpp 2.5 V 3.39 2.44 Vpp 111 1.1430 1.8 V (See (Note 7) 2.79 Vpp 2.5 V 3.88 2.79 Vpp

width is 10 Hz to 20 kHz; Sample Frequency = 48 kHz; test load RL = 16 Ω, CL = 10 pF (see Figure 3). One-half LSB of triangular PDF dither is added to data. mended 150 pF can cause the internal op-amp to become unstable. may not achieve the full THD+N performance at full-scale output voltage and power. Figure 3. Headphone Output Test Load

COMBINED DAC INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE Notes: Response is clock dependent and will scale with Fs. Note that the response plots (Figure 27 to Figure 30 on page 60) have been normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs. Measurement Bandwidth is from Stopband to 3 Fs. SWITCHING SPECIFICATIONS - SERIAL PORT (Inputs: Logic 0 = DGND, Logic 1 = VL.) Parameter (Note 8) Min Typ Max Unit Frequency Response 10 Hz to 20 kHz -0.01 +0.08 dB Passband to -0.05 dB corner to -3 dB corner 0.4780 0.4996 Fs Fs StopBand 0.5465 Fs StopBand Attenuation (Note 9) dB Group Delay 10.4/Fs s De-emphasis Error Fs = 32 kHz Fs = 44.1 kHz Fs = 48 kHz +1.5/+0 +0.05/-0.25 -0.2/-0.4 dB dB dB Parameters Symbol Min Max Units RESET pin Low Pulse Width (Note 10) ms MCLK Frequency 1.024 38.4 MHz MCLK Duty Cycle (Note 11) Slave Mode Input Sample Rate (LRCK) Quarter-Speed Mode Half-Speed Mode Single-Speed Mode Double-Speed Mode Fs Fs Fs Fs 12.5 100 kHz kHz kHz kHz LRCK Duty Cycle SCLK Frequency 1/tP 64•Fs Hz SCLK Duty Cycle LRCK Setup Time Before SCLK Rising Edge ts(LK-SK) ns SDIN Setup Time Before SCLK Rising Edge ts(SD-SK) ns SDIN Hold Time After SCLK Rising Edge th ns

1. Data must be held for sufficient time to bridge the transition time, tfc, of SCL.

Figure 6. Control Port Timing - I²C

1. Data must be held for sufficient time to bridge the transition time of CCLK.

Figure 7. Control Port Timing - SPI Format

DC ELECTRICAL CHARACTERISTICS (AGND = 0 V; all voltages with respect to ground.) 16. The DC current draw represents the allowed current draw from the VQ pin due to typical leakage through electrolytic de-coupling capacitors. 17. Valid with the recommended capacitor values on FILT+ and VQ. Increasing the capacitance will also increase the PSRR. DIGITAL INTERFACE SPECIFICATIONS & CHARACTERISTICS 18. See “Digital I/O Pin Characteristics” on page 8 for serial and control port power rails. Parameters Min Typ Max Units VQ Characteristics Nominal Voltage Output Impedance DC Current Source/Sink (Note 16) 0.5•VA V kΩ µA FILT+ VA V VSS_HP Characteristics Nominal Voltage DC Current Source -0.8•(VA_HP) V µA Power Supply Rejection Ratio (PSRR) (Note 17) 1 kHz dB Parameters (Note 18) Symbol Min Max Units Input Leakage Current Iin ±10 µA Input Capacitance pF 1.8 V - 3.3 V Logic High-Level Output Voltage (IOH = -100 µA) VOH VL - 0.2 V Low-Level Output Voltage (IOL = 100 µA) VOL 0.2 V High-Level Input Voltage VIH 0.68•VL V Low-Level Input Voltage VIL 0.32•VL V

See (Note 19) 19. Unless otherwise noted, test conditions are as follows: All zeros input, slave mode, sample rate = 48 kHz; No load. Digital (VD) and logic (VL) supply current will vary depending on speed mode and mas- ter/slave operation. 20. RESET pin 25 held LO, all clocks and data lines are held LO. 21. RESET pin 25 held HI, all clocks and data lines are held HI. 22. VL current will slightly increase in master mode. Power Ctl. Registers Typical Current (mA) Operation 02h 03h PDN_DACB PDN_DACA BIT 4 BIT 3 BIT 2 BIT 1 PDN BIT 3 BIT 2 BIT 1 V iVA_HP iVA iVD iVL (Note 22) Total Power (mWrms) Off (Note 20) x x x x x x x x x x 1.8 2.5 Standby (Note 21) x x x x x x 1 x x x 1.8 0.01 0.02 0.05 2.5 0.01 0.03 0.10 Mono Playback 1 0 1 1 1 1 0 1 1 1 1.8 1.66 1.40 2.35 0.01 9.74 2.5 2.03 1.71 3.48 0.02 18.08 Stereo Playback 0 0 1 1 1 1 0 1 1 1 1.8 2.77 2.05 2.35 0.01 12.93 2.5 3.21 2.50 3.49 0.02 23.02

1. APPLICATIONS 4.1 Overview 4.1.1 Architecture The CS43L21 is a highly integrated, low power, 24-bit audio D/A comprised of stereo digital-to-analog converters (DAC) designed using multi-bit delta-sigma techniques. The DAC operates at an oversampling ratio of 128Fs. The D/A operates in one of four sample rate speed modes: Quarter, Half, Single and Dou- ble. It accepts and is capable of generating serial port clocks (SCLK, LRCK) derived from an input Master Clock (MCLK). 4.1.2 Line & Headphone Outputs The analog output portion of the D/A includes a headphone amplifier capable of driving headphone and line-level loads. An on-chip charge pump creates a negative headphone supply allowing a full-scale out- put swing centered around ground. This eliminates the need for large DC-Blocking capacitors and allows the amplifier to deliver more power to headphone loads at lower supply voltages. Eight gain settings for the headphone amplifier are available. 4.1.3 Signal Processing Engine A signal processing engine is available to process serial input D/A data before output to the DAC. The D/A data has independent volume controls and mixing functions such as mono mixes and left/right chan- nel swaps. A Tone Control provides bass and treble at four selectable corner frequencies. An automatic level control provides limiting capabilities at programmable attack and release rates, maximum thresholds and soft ramping. A 15/50 µs de-emphasis filter is also available at a 44.1 kHz sample rate. 4.1.4 Beep Generator A beep may be generated internally at select frequencies across approximately two octave major scales and configured to occur continuously, periodically or at single time intervals controlled by the user. Volume may be controlled independently. 4.1.5 Device Control (Hardware or Software Mode) In Software Mode, all functions and features may be controlled via a two-wire I²C or three-wire SPI control port interface. In Hardware Mode, a limited feature set may be controlled via stand-alone control pins. 4.1.6 Power Management Two Software Mode control registers provide independent power-down control of the DAC, allowing op- eration in select applications with minimal power consumption.

of functions/features, the default configuration and the associated stand-alone control available. Table 2. Hardware Mode Feature Summary

“DAC Control (Address 09h)” on page 42. “DAC Control (Address 09h)” on page 42. Figure 8. Output Architecture

ments of 0.125 dB at a rate controlled by the soft ramp/zero cross settings. ment a left/right channel swap. ume, DAC volume may alternatively be controlled using the PCMMIXx_VOL[6:0] bits. “PCM Channel Mixer (Address 18h)” on page 49. Figure 9. De-Emphasis Curve

cies. Boosting will affect peak detect and limiting when levels exceed the maximum threshold settings. soft ramp and zero cross dependency may be independently enabled/disabled. manually. Alternative volume control may be realized using the PCMMIXx_VOL[6:0] bits. “Tone Control (Address 15h)” on page 48. and set for additional beeps. Figure 10. Beep Configuration Options

amplifiers to drive line or headphone outputs. connection diagrams, is the input impedance of the receiving device. an off-chip low pass filter. & AOUTB (Address 17h)” on page 49. Figure 11. Peak Detect & Limiter

4.3.8 On-Chip Charge Pump An on-chip charge pump derives a negative supply voltage from the VA_HP supply. This provides dual rail supplies allowing a full-scale output swing centered around ground and eliminates the need for large, DC-blocking capacitors. Added benefits include greater pop suppression and improved low frequency (bass) response. Note: Series resistance in the path of the power supplies must be avoided. Any voltage drop on the VA_HP supply will directly impact the derived negative voltage on the charge pump supply, VSS_HP, and may result in clipping. The FLYN and FLYP pins connect to internal switches that charges and discharges the external capacitor attached, at a default switching frequency. This frequency may be adjusted in the control port registers. Increasing the charge-pumping capacitor will slightly decease the pumping frequency. The capacitor con- nected to VSS_HP acts as a charge reservoir for the negative supply as well as a filter for the ripple in- duced by the charge pump. Increasing this capacitor will decrease the ripple on VSS_HP. Refer to the typical connection diagrams in Figure 1 on page 9 or Figure 2 on page 10 for the recommended capacitor values for the charge pump circuitry. 4.4 Serial Port Clocking The D/A serial audio interface port operates either as a slave or master. It accepts externally generated clocks in slave mode and will generate synchronous clocks derived from an input master clock (MCLK) in master mode. The frequency of the MCLK must be an integer multiple of, and synchronous with, the system sample rate, Fs. The LRCK frequency is equal to Fs, the frequency at which audio samples for each channel are clocked into or out of the device. The SPEED and MCLKDIV2 software control bits or the M/S and MCLKDIV2 stand-alone control pins, con- figure the device to generate the proper clocks in Master Mode and receive the proper clocks in Slave Mode. The value on the M/S pin is latched immediately after powering up in Hardware Mode. Software Controls: “Charge Pump Frequency (Address 21h)” on page 53. Software Control: , “DAC Control (Address 09h)” on page 42. Hardware Control: Pin Setting Selection “M/S” pin 29 47 kΩ Pull-down Slave 47 kΩ Pull-up Master “MCLKDIV2” pin 2 LO No Divide HI MCLK is divided by 2 prior to all internal circuitry.

mode must be selected using the SPEED[1:0] bits. LRCK and SCLK are internally derived from the internal MCLK (after the divide, if MCLKDIV2 is enabled). quarter-, half-, single- or double-speed depending on the setting of the SPEED[1:0] bits. Table 3. MCLK/LRCK Ratios Figure 12. Master Mode Timing

disable the soft ramp and/or zero cross volume transitions to achieve faster muting/power down.

1. No audio signal generated.
2. Control Port Registers reset
3. Aout bias = last audio sample.
4. DAC Modulators stop operation.
5. No audio signal generated.
6. Control Port Registers retain

Figure 17. Initialization Flow Chart

4.9.3 Memory Address Pointer (MAP) The MAP byte comes after the address byte and selects the register to be read or written. Refer to the pseudo code above for implementation details. 4.9.3.1 Map Increment (INCR) The device has MAP auto-increment capability enabled by the INCR bit (the MSB) of the MAP. If INCR is set to 0, MAP will stay constant for successive I²C writes or reads and SPI writes. If INCR is set to 1, MAP will auto-increment after each byte is read or written, allowing block reads or writes of successive registers.

1. REGISTER QUICK REFERENCE Software mode register defaults are as shown. “Reserved” registers must maintain their default state. Addr Function 01h ID Chip_ID4 Chip_ID3 Chip_ID2 Chip_ID1 Chip_ID0 Rev_ID2 Rev_ID1 Rev_ID0 p 39 default 02h Power Ctl. 1 Reserved PDN_DACB PDN_DACA Reserved Reserved Reserved Reserved PDN p 39 default 1(See Note 2 on page 39) 1(See Note 2 on page 39) 1(See Note 2 on page 39) 1(See Note 2 on page 39) 03h Speed Ctl. & Power Ctl. 2 AUTO SPEED1 SPEED0 3-ST_SP Reserved Reserved Reserved MCLKDIV2 p 40 default 04h Interface Ctl. Reserved M/S DAC_DIF2 DAC_DIF1 DAC_DIF0 Reserved Reserved Reserved p 41 default 05h Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved default 06h Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved default 07h Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved default 08h DAC Output Control HP_GAIN2 HP_GAIN1 HP_GAIN0 DAC_SNG VOL INV_PCMB INV_PCMA DACB_ MUTE DACA_ MUTE p 41 default 09h DAC Control DATA_SEL1 DATA_SEL0 FREEZE Reserved DEEMPH AMUTE DAC_SZC1 DAC_SZC0 p 42 default 0Ah Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved default 0Bh Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved default 0Ch Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved default 0Dh Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved default 0Eh Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved default

Vol. Control PCMMIXA MUTE_PCM MIXA PCMMIXA VOL6 PCMMIXA VOL5 PCMMIXA VOL4 PCMMIXA VOL3 PCMMIXA VOL2 PCMMIXA VOL1 PCMMIXA VOL0 p 44 default 11h Vol. Control PCMMIXB MUTE_PCM MIXB PCMMIXB VOL6 PCMMIXB VOL5 PCMMIXB VOL4 PCMMIXB VOL3 PCMMIXB VOL2 PCMMIXB VOL1 PCMMIXB VOL0 p 44 default 12h BEEP Freq. & OnTime FREQ3 FREQ2 FREQ1 FREQ0 ONTIME3 ONTIME2 ONTIME1 ONTIME0 p 45 default 13h BEEP Off Time & Vol OFFTIME2 OFFTIME1 OFFTIME0 BPVOL4 BPVOL3 BPVOL2 BPVOL1 BPVOL0 p 46 default 14h BEEP Con- trol & Tone Config REPEAT BEEP Reserved TREB_CF1 TREB_CF0 BASS_CF1 BASS_CF0 TC_EN p 47 default 15h Tone Control TREB3 TREB2 TREB1 TREB0 BASS3 BASS2 BASS1 BASS0 p 48 default 16h Vol. Control AOUTA AOUTA_ VOL7 AOUTA_ VOL6 AOUTA_ VOL5 OUTA_ VOL4 AOUTA_ VOL3 AOUTA_ VOL2 AOUTA_ VOL1 AOUTA_ VOL0 p 49 default 17h Vol. Control AOUTB AOUTB_ VOL7 AOUTB_ VOL6 AOUTB_ VOL5 AOUTB_ VOL4 AOUTB_ VOL3 AOUTB_ VOL2 AOUTB_ VOL1 AOUTB_ VOL0 p 49 default 18h PCM Channel Mixer PCMA1 PCMA0 PCMB1 PCMB0 Reserved Reserved Reserved Reserved p 49 default 19h Limiter Threshold & SZC Disable MAX2 MAX1 MAX0 CUSH2 CUSH1 CUSH0 LIM_SRDIS LIM_ZCDIS p 50 default 1Ah Limiter Con- fig & Release Rate LIMIT_EN LIMIT_ALL LIM_RRATE LIM_RRATE LIM_RRATE LIM_RRATE LIM_RRATE LIM_RRATE p 51 default 1Bh Limiter Attack Rate Reserved Reserved LIM_ARATE5 LIM_ARATE4 LIM_ARATE3 LIM_ARATE2 LIM_ARATE1 LIM_ARATE0 p 52 default 1Ch Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Addr Function

SP_CLKER R SPEB_OVFL SPEA_OVFL PCMA_OVFL PCMB_OVFL Reserved Reserved p 52 default 21h CHRG_ FREQ3 CHRG_ FREQ2 CHRG_ FREQ1 CHRG_ FREQ0 Reserved Reserved Reserved Reserved p 53 default Addr Function

1. REGISTER DESCRIPTION All registers are read/write except for the chip I.D. and Revision Register and Interrupt Status Register which are read only. See the following bit definition tables for bit assignment information. The default state of each bit after a power-up sequence or reset is listed in each bit description. All “Reserved” registers must maintain their default state. 6.1 Chip I.D. and Revision Register (Address 01h) (Read Only) Chip I.D. (Chip_ID[4:0]) Default: 11011 Function: I.D. code for the CS43L21. Permanently set to 11011. Chip Revision (Rev_ID[2:0]) Default: 001 Function: CS43L21 revision level. Revision B is coded as 001. Revision A is coded as 000. 6.2 Power Control 1 (Address 02h) Notes: To activate the power-down sequence for individual channels (A or B,) both channels must first be pow- ered down either by enabling the PDN bit or by enabling the power-down bits for both channels. En- abling the power-down bit on an individual channel basis after the D/A has fully powered up will mute the selected channel without achieving any power savings. Reserved bits 1 - 4 should always be set “high” by the user to minimize power consumption during nor- mal operation. Recommended channel power-down sequence: 1.) Enable the PDN bit, 2.) enable power-down for the se- lect channels, 3.) disable the PDN bit. Power Down DAC X (PDN_DACX) Default: 0 0 - Disable 1 - Enable Function: DAC channel x will either enter a power-down or muted state when this bit is enabled. See Note 1 above. Chip_ID4 Chip_ID3 Chip_ID2 Chip_ID1 Chip_ID0 Rev_ID2 Rev_ID1 Rev_ID0 Reserved PDN_DACB PDN_DACA Reserved Reserved Reserved Reserved PDN

Power Down (PDN) Default: 0 0 - Disable 1 - Enable Function: The entire D/A will enter a low-power state when this function is enabled. The contents of the control port registers are retained in this mode. 6.3 Speed Control (Address 03h) Auto-Detect Speed Mode (AUTO) Default: 1 0 - Disable 1 - Enable Function: Enables the auto-detect circuitry for detecting the speed mode of the D/A when operating as a slave. When AUTO is enabled, the MCLK/LRCK ratio must be implemented according to Table 3 on page 29. The SPEED[1:0] bits are ignored when this bit is enabled. Speed is determined by the MCLK/LRCK ratio. Speed Mode (SPEED[1:0]) Default: 01 11 - Quarter-Speed Mode (QSM) - 4 to 12.5 kHz sample rates 10 - Half-Speed Mode (HSM) - 12.5 to 25 kHz sample rates 01 - Single-Speed Mode (SSM) - 4 to 50 kHz sample rates 00 - Double-Speed Mode (DSM) - 50 to 100 kHz sample rates Function: Sets the appropriate speed mode for the D/A in Master or Slave Mode. QSM is optimized for 8 kHz sample rate and HSM is optimized for 16 kHz sample rate. These bits are ignored when the AUTO bit is enabled (see Auto-Detect Speed Mode (AUTO) above). Tri-State Serial Port Interface (3ST_SP) Default: 0 0 - Disable 1 - Enable Function: When enabled and the device is configured as a master, the SCLK/LRCK signals are placed in a high-im- pedance output state. If the serial port is configured as a slave, SCLK/LRCK are configured as inputs. MCLK Divide By 2 (MCLKDIV2) Default: 0 0 - Disabled 1 - Divide by 2 AUTO SPEED1 SPEED0 3-ST_SP Reserved Reserved Reserved MCLKDIV2

Function: Divides the input MCLK by 2 prior to all internal circuitry. This bit is ignored when the AUTO bit is disabled in Slave Mode. 6.4 Interface Control (Address 04h) Master/Slave Mode (M/S) Default: 0 0 - Slave 1 - Master Function: Selects either master or slave operation for the serial port. DAC Digital Interface Format (DAC_DIF[2:0]) Default = 000 Function: Selects the digital interface format used for the data in on SDIN. The required relationship between the Left/Right clock, serial clock and serial data is defined by the Digital Interface Format and the options are detailed in the section “Digital Interface Formats” on page 30. 6.5 DAC Output Control (Address 08h) Headphone Analog Gain (HP_GAIN[2:0]) Default: 011 Reserved M/S DAC_DIF2 DAC_DIF1 DAC_DIF0 Reserved Reserved Reserved DAC_DIF[2:0]

Description

Left-Justified, up to 24-bit data 15 on page 31 001 I²S, up to 24-bit data 14 on page 30 010 Right-Justified, 24-bit data 17 on page 3217 on page 32 011 Right-Justified, 20-bit data 17 on page 3217 on page 32 100 Right-Justified, 18-bit data 17 on page 3217 on page 32 101 Right-Justified, 16-bit data 17 on page 3217 on page 32 110 Reserved 100 Reserved HP_GAIN2 HP_GAIN1 HP_GAIN0 DAC_ SNGVOL INV_PCMB INV_PCMA DACB_MUTE DACA_MUTE HP_GAIN[2:0] Gain Setting 000 0.3959 001 0.4571 010 0.5111 011 0.6047 100 0.7099 101 0.8399 110 1.0000 111 1.1430

Function: These bits select the gain multiplier for the headphone/line outputs. See “Line Output Voltage Characteris- tics” on page 14 and “Headphone Output Power Characteristics” on page 15. DAC Single Volume Control (DAC_SNGVOL) Default: 0 Function: The individual channel volume levels are independently controlled by their respective Volume Control reg- isters when this function is disabled. When enabled, the volume on all channels is determined by the AOU- TA Volume Control register and the AOUTB Volume Control register is ignored. PCMX Invert Signal Polarity (INV_PCMX) Default: 0 0 - Disabled 1 - Enabled Function: When enabled, this bit will invert the signal polarity of the PCM x channel. DACX Channel Mute (DACX_MUTE) Default: 0 0 - Disabled 1 - Enabled Function: The output of channel x DAC will mute when enabled. The muting function is affected by the DACx Soft and Zero Cross bits (DACx_SZC[1:0]). 6.6 DAC Control (Address 09h) DAC Data Selection (DATA_SEL[1:0]) Default: 00 00 - PCM Serial Port to DAC 01 - Signal Processing Engine to DAC 10 - Reserved 11 - Reserved Function: Selects the digital signal source for the DAC. Note: Certain functions are only available when the “Signal Processing Engine to DAC” option is selected using these bits. DATA_SEL1 DATA_SEL0 FREEZE Reserved DEEMPH AMUTE DAC_SZC1 DAC_SZC0

Freeze Controls (FREEZE) Default: 0 Function: This function will freeze the previous settings of, and allow modifications to be made to all control port reg- isters without the changes taking effect until the FREEZE is disabled. To have multiple changes in the con- trol port registers take effect simultaneously, enable the FREEZE bit, make all register changes, then disable the FREEZE bit. DAC De-Emphasis Control (DEEMPH) Default: 0 0 - No De-Emphasis 1 - De-Emphasis Enabled Function: Note: The DATA_SEL[1:0] bits in reg09h must be set to ‘01’b to enable function control. Enables the digital filter to apply the standard 15µs/50µs digital de-emphasis filter response for a sample rate of 44.1 kHz. Analog Output Auto MUTE (AMUTE) Default: 0 0 - Auto Mute Disabled 1 - Auto Mute Enabled Function: Enables (or disables) Automatic Mute of the analog outputs after 8192 “0” samples on each digital input channel. DAC Soft Ramp and Zero Cross Control (DAC_SZC[1:0]) Default = 10 00 - Immediate Change 01 - Zero Cross 10 - Soft Ramp 11 - Soft Ramp on Zero Crossings Function: Note: The DATA_SEL[1:0] bits in reg09h must be set to ‘01’b to enable function control Immediate Change When Immediate Change is selected all volume-level changes will take effect immediately in one step. Zero Cross This setting dictates that signal-level changes, either by gain changes, attenuation changes or muting, will occur on a signal zero crossing to minimize audible artifacts. The requested level change will occur after a timeout period between 1024 and 2048 sample periods (21.3 ms to 42.7 ms at 48 kHz sample rate) if the signal does not encounter a zero crossing. The zero cross function is independently monitored and imple- mented for each channel. Note: The LIM_SRDIS bit is ignored.

Soft Ramp allows level changes, either by gain changes, attenuation changes or muting, to be implemented by incrementally ramping, in 1/8 dB steps, from the current level to the new level at a rate of 0.5 dB per 4 left/right clock periods. Soft Ramp on Zero Crossing This setting dictates that signal-level changes, either by gain changes, attenuation changes or muting, will occur in 1/8 dB steps and be implemented on a signal zero crossing. The 1/8 dB level change will occur after a timeout period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample rate) if the signal does not encounter a zero crossing. The zero cross function is independently monitored and im- plemented for each channel. Note: The LIM_SRDIS bit is ignored. 6.7 PCMX Mixer Volume Control: PCMA (Address 10h) & PCMB (Address 11h) Note: The DATA_SEL[1:0] bits in reg09h must be set to ‘01’b to enable function control in this register. PCMX Mixer Channel Mute (MUTE_PCMMIXX) Default = 1 0 - Disabled 1 - Enabled Function: The PCM channel X input to the output mixer will mute when enabled. The muting function is affected by the DACX Soft and Zero Cross bits (DACX_SZC[1:0]). PCMX Mixer Volume Control (PCMMIXX_VOL[6:0]) Default: 000 0000 Function: The level of the PCMX input to the output mixer can be adjusted in 0.5 dB increments as dictated by the DACX Soft and Zero Cross bits (DACX_SZC[1:0]) from +12 to -51.5 dB. Levels are decoded as described in the table above. MUTE_ PCMMIXx PCMMIXx_ VOL6 PCMMIXx_ VOL5 PCMMIXx_ VOL4 PCMMIXx_ VOL3 PCMMIXx_ VOL2 PCMMIXx_ VOL1 PCMMIXx_ VOL0 Binary Code Volume Setting 001 1000 +12.0 dB

• ··
• ·· 000 0000 0 dB 111 1111 -0.5 dB 111 1110 -1.0 dB
• ··
• ·· 001 1001 -51.5 dB

6.8 Beep Frequency & Timing Configuration (Address 12h) Note: The DATA_SEL[1:0] bits in reg09h must be set to ‘01’b to enable function control in this register. Beep Frequency (FREQ[3:0]) Default: 0000 Function: The frequency of the beep signal can be adjusted from 260.87 Hz to 2181.82 Hz. Beep frequency will scale directly with sample rate, Fs, but is fixed at the nominal Fs within each speed mode. Refer to Figure 10 on page 26 for single, multiple and continuous beep configurations using the REPEAT and BEEP bits. Beep On Time Duration (ONTIME[3:0]) Default: 0000 Function: The on-duration of the beep signal can be adjusted from approximately 86 ms to 5.2 s. The on-duration will scale inversely with sample rate, Fs, but is fixed at the nominal Fs within each speed mode. Refer to Figure 10 on page 26 for single-, multiple- and continuous-beep configurations using the REPEAT and BEEP bits. FREQ3 FREQ2 FREQ1 FREQ0 ONTIME3 ONTIME2 ONTIME1 ONTIME0 FREQ[3:0] Frequency Fs = 12, 24, 48 or 96 kHz Pitch 0000 260.87 Hz 0001 521.74 Hz 0010 585.37 Hz 0011 666.67 Hz 0100 705.88 Hz 0101 774.19 Hz 0110 888.89 Hz 0111 1000.00 Hz 1000 1043.48 Hz 1001 1200.00 Hz 1010 1333.33 Hz 1011 1411.76 Hz 1100 1600.00 Hz 1101 1714.29 Hz 1110 2000.00 Hz 1111 2181.82 Hz TIME[3:0] On Time Fs = 12, 24, 48 or 96 kHz 0000 86 ms

• ··
• ·· 1111 5.2 s

6.9 Beep Off Time & Volume (Address 13h) Note: The DATA_SEL[1:0] bits in reg09h must be set to ‘01’b to enable function control in this register. Beep Off Time (OFFTIME[2:0]) Default: 000 Function: The off-duration of the beep signal can be adjusted from approximately 75 ms to 680 ms. The off-duration will scale inversely with sample rate, Fs, but is fixed at the nominal Fs within each speed mode. Refer to Figure 10 on page 26 for single-, multiple- and continuous-beep configurations using the REPEAT and BEEP bits. Beep Volume (BPVOL[4:0]) Default: 00000 Function: The level of the beep into the output mixer can be adjusted in 2.0 dB increments from +12 dB to -50 dB. Refer to Figure 10 on page 26 for single-, multiple- and continuous-beep configurations using the REPEAT and BEEP bits. Levels are decoded as described in the table above. OFFTIME2 OFFTIME1 OFFTIME0 BPVOL4 BPVOL3 BPVOL2 BPVOL1 BPVOL0 OFFTIME[2:0] Off Time Fs = 12, 24, 48 or 96 kHz 000 1.23 s 001 2.58 s 010 3.90 s 011 5.20 s 100 6.60 s 101 8.05 s 110 9.35 s 111 10.80 s Binary Code Volume Setting 00110 +12.0 dB

• ··
• ·· 00000 0 dB 11111 -2 dB 11110 -4 dB
• ··
• ·· 00111 -50 dB

6.10 Beep Configuration & Tone Configuration (Address 14h) Note: The DATA_SEL[1:0] bits in reg09h must be set to ‘01’b to enable function control in this register. Repeat Beep (REPEAT) Default: 0 0 - Disabled 1 - Enabled Function: This bit is used in conjunction with the BEEP bit to mix a continuous or periodic beep with the analog output. Refer to Figure 10 on page 26 for a description of each configuration option. Beep (BEEP) Default: 0 0 - Disabled 1 - Enabled Function: This bit is used in conjunction with the REPEAT bit to mix a continuous or periodic beep with the analog output. Note: Re-engaging the beep before it has completed its initial cycle will cause the beep signal to remain ON for the maximum ONTIME duration. Refer to Figure 10 on page 26 for a description of each con- figuration option. Treble Corner Frequency (TREB_CF[1:0]) Default: 00 00 - 5 kHz 01 - 7 kHz 10 - 10 kHz 11 - 15 kHz Function: The treble corner frequency is user selectable as shown above. Bass Corner Frequency (BASS_CF[1:0]) Default: 00 00 - 50 Hz 01 - 100 Hz 10 - 200 Hz 11 - 250 Hz Function: The bass corner frequency is user-selectable as shown above. REPEAT BEEP Reserved TREB_CF1 TREB_CF0 BASS_CF1 BASS_CF0 TC_EN

Tone Control Enable (TC_EN) Default = 0 0 - Disabled 1 - Enabled Function: The Bass and Treble tone control features are active when this bit is enabled. 6.11 Tone Control (Address 15h) Note: The DATA_SEL[1:0] bits in reg09h must be set to ‘01’b to enable function control in this register. Treble Gain Level (TREB[3:0]) Default: 1000 dB (No Treble Gain) Function: The level of the shelving treble gain filter is set by Treble Gain Level. The level can be adjusted in 1.5 dB increments from +12.0 to -10.5 dB. Bass Gain Level (BASS[3:0]) Default: 1000 dB (No Bass Gain) Function: The level of the shelving bass gain filter is set by Bass Gain Level. The level can be adjusted in 1.5 dB in- crements from +10.5 to -10.5 dB. TREB3 TREB2 TREB1 TREB0 BASS3 BASS2 BASS1 BASS0 Binary Code Gain Setting 0000 +12.0 dB

• ··
• ·· 0111 +1.5 dB 1000 0 dB 1001 -1.5 dB
• ··
• ·· 1111 -10.5 dB Binary Code Gain Setting 0000 +12.0 dB
• ··
• ·· 0111 +1.5 dB 1000 0 dB 1001 -1.5 dB
• ··
• ·· 1111 -10.5 dB

6.12 AOUTx Volume Control: AOUTA (Address 16h) & AOUTB (Address 17h) Note: The DATA_SEL[1:0] bits in reg09h must be set to ‘01’b to enable function control in this register. AOUTX Volume Control (AOUTX_VOL[7:0]) Default = 00h Function: The analog output levels can be adjusted in 0.5 dB increments from +12 to -102 dB as dictated by the DAC Soft and Zero Cross bits (DACX_SZC[1:0]). Levels are decoded in unsigned binary as described in the table above. Note: When the limiter is enabled, the AOUT Volume is automatically controlled and should not be ad- justed manually. Alternative volume control may be achieved using the PCMMIXx_VOL[6:0] bits. 6.13 PCM Channel Mixer (Address 18h) Note: The DATA_SEL[1:0] bits in reg09h must be set to ‘01’b to enable function control in this register. Channel Mixer (PCMx[1:0]) Default: 00 Function: Implements mono mixes of the left and right channels as well as a left/right channel swap. AOUTx_VOL7 AOUTx_VOL6 AOUTx_VOL5 AOUTx_VOL4 AOUTx_VOL3 AOUTx_VOL2 AOUTx_VOL1 AOUTx_VOL0 Binary Code Volume Setting 0001 1000 +12.0 dB

• ··
• ·· 0000 0000 0 dB 1111 1111 -0.5 dB 1111 1110 -1.0 dB
• ··
• ·· 0011 0100 -102 dB
• ··
• ·· 0001 1001 -102 dB PCMA1 PCMA0 PCMB1 PCMB0 Reserved Reserved Reserved Reserved PCMA[1:0] AOUTA PCMB[1:0] AOUTB L R R L L R L R

6.14 Limiter Threshold SZC Disable (Address 19h) Note: The DATA_SEL[1:0] bits in reg09h must be set to ‘01’b to enable function control in this register. Maximum Threshold (MAX[2:0]) Default: 000 Function: Sets the maximum level, below full scale, at which to limit and attenuate the output signal at the attack rate. Bass, Treble and digital gain settings that boost the signal beyond the maximum threshold may trigger an attack. Cushion Threshold (CUSH[2:0]) Default: 000 Function: Sets a cushion level below full scale. This setting is usually set slightly below the maximum (MAX[2:0]) threshold. The Limiter uses this cushion as a hysteresis point for the input signal as it maintains the signal below the maximum as well as below the cushion setting. This provides a more natural sound as the limiter attacks and releases. MAX2 MAX1 MAX0 CUSH2 CUSH1 CUSH0 LIM_SRDIS LIM_ZCDIS MAX[2:0] Threshold Setting (dB) 000 001 010 011 101 -12 101 -18 110 -24 111 -30 CUSH[2:0] Threshold Setting (dB) 000 001 010 011 101 -12 101 -18 110 -24 111 -30

Limiter Soft Ramp Disable (LIM_SRDIS) Default: 0 0 - Off 1 - On Function: Overrides the DAC_SZC setting. When this bit is set, the Limiter attack and release rate will not be dictated by the soft ramp setting. Note: This bit is ignored when the zero-cross function is enabled (i.e. when DAC_SZC[1:0] = ‘01’b or ‘11’b.) Limiter Zero Cross Disable (LIM_ZCDIS) Default: 0 0 - Off 1 - On Function: Overrides the DAC_SZC setting. When this bit is set, the Limiter attack and release rate will not be dictated by the zero-cross setting. 6.15 Limiter Release Rate Register (Address 1Ah) Note: The DATA_SEL[1:0] bits in reg09h must be set to ‘01’b to enable function control in this register. Peak Detect and Limiter Enable (LIMIT_EN) Default: 0 0 - Disabled 1 - Enabled Function: Limits the maximum signal amplitude to prevent clipping when this function is enabled. Peak Signal Limiting is performed by digital attenuation. Note: When the limiter is enabled, the AOUT Volume is automatically controlled and should not be adjusted manually. Alternative volume control may be realized using the PCMMIXx_VOL[6:0] bits. Peak Signal Limit All Channels (LIMIT_ALL) Default: 1 0 - Individual Channel 1 - Both channel A & B Function: When set to 0, the peak signal limiter will limit the maximum signal amplitude to prevent clipping on the spe- cific channel indicating clipping. The other channels will not be affected. When set to 1, the peak signal limiter will limit the maximum signal amplitude to prevent clipping on both channels in response to any single channel indicating clipping. LIMIT_EN LIMIT_ALL RRATE5 RRATE4 RRATE3 RRATE2 RRATE1 RRATE0

Limiter RELEASE Rate (RRATE[5:0]) Default: 111111 Function: Sets the rate at which the limiter releases the digital attenuation from levels below the minimum setting in the limiter threshold register, and returns the analog output level to the AOUTx_VOL[7:0] setting. The limiter release rate is user selectable but is also a function of the sampling frequency, Fs, and the DAC_SZC setting unless the disable bit is enabled. 6.16 Limiter Attack Rate Register (Address 1Bh) Note: The DATA_SEL[1:0] bits in reg09h must be set to ‘01’b to enable function control in this register. Limiter Attack Rate (ARATE[5:0]) Default: 000000 Function: Sets the rate at which the limiter attenuates the analog output from levels above the maximum setting in the limiter threshold register. The limiter attack rate is user-selectable but is also a function of the sampling frequency, Fs, and the DAC_SZC setting unless the disable bit is enabled. 6.17 Status (Address 20h) (Read Only) For all bits in this register, a “1” means the associated error condition has occurred at least once since the register was last read. A ”0” means the associated error condition has NOT occurred since the last reading of the register. Reading the register resets all bits to 0. Serial Port Clock Error (SP_CLK Error) Default: 0 Function: Indicates an invalid MCLK to LRCK ratio. See “Serial Port Clocking” section on page 28“Serial Port Clock- ing” on page 28 for valid clock ratios. Note: On initial power up and application of clocks, this bit will be high as the serial port re-synchronizes. Binary Code Release Time 000000 Fastest Release

• ··
• ·· 111111 Slowest Release Reserved Reserved ARATE5 ARATE4 ARATE3 ARATE2 ARATE1 ARATE0 Binary Code Attack Time 000000 Fastest Attack
• ··
• ·· 111111 Slowest Attack Reserved SP_CLKERR SPEA_OVFL SPEB_OVFL PCMA_OVFL PCMB_OVFL Reserved Reserved

Signal Processing Engine Overflow (SPEX_OVFL) Default: 0 Function: Indicates a digital overflow condition within the data path after the signal processing engine. PCMX Overflow (PCMX_OVFL) Default: 0 Function: Indicates a digital overflow condition within the data path of the PCM mix. 6.18 Charge Pump Frequency (Address 21h) Charge Pump Frequency (CHRG_FREQ[3:0]) Default: 0101 Function: Alters the clocking frequency of the charge pump in 1/(N+2) fractions of the DAC oversampling rate, 128Fs, should the switching frequency interfere with other system frequencies such as those in the AM radio band. Note: Distortion performance may be affected. CHRG_FREQ CHRG_FREQ CHRG_FREQ CHRG_FREQ Reserved Reserved Reserved Reserved N CHRG_FREQ[3:0] Frequency 0000 ... ... 1111 64xFs N

1. EXAMPLE SYSTEM CLOCK FREQUENCIES 8.1 Auto Detect Enabled *The”MCLKDIV2” pin 4 must be set HI. Sample Rate LRCK (kHz) MCLK (MHz) 1024x 1536x 2048x* 3072x* 8.1920 12.2880 16.3840 24.5760 11.025 11.2896 16.9344 22.5792 33.8688 12.2880 18.4320 24.5760 36.8640 Sample Rate LRCK (kHz) MCLK (MHz) 512x 768x 1024x* 1536x* 8.1920 12.2880 16.3840 24.5760 22.05 11.2896 16.9344 22.5792 33.8688 12.2880 18.4320 24.5760 36.8640 Sample Rate LRCK (kHz) MCLK (MHz) 256x 384x 512x* 768x* 8.1920 12.2880 16.3840 24.5760 44.1 11.2896 16.9344 22.5792 33.8688 12.2880 18.4320 24.5760 36.8640 Sample Rate LRCK (kHz) MCLK (MHz) 128x 192x 256x* 384x* 8.1920 12.2880 16.3840 24.5760 88.2 11.2896 16.9344 22.5792 33.8688 12.2880 18.4320 24.5760 36.8640

8.2 Auto Detect Disabled Sample Rate LRCK (kHz) MCLK (MHz) 512x 768x 1024x 1536x 2048x 3072x 6.1440 8.1920 12.2880 16.3840 24.5760 11.025 8.4672 11.2896 16.9344 22.5792 33.8688 6.1440 9.2160 12.2880 18.4320 24.5760 36.8640 Sample Rate LRCK (kHz) MCLK (MHz) 256x 384x 512x 768x 1024x 1536x 6.1440 8.1920 12.2880 16.3840 24.5760 22.05 8.4672 11.2896 16.9344 22.5792 33.8688 6.1440 9.2160 12.2880 18.4320 24.5760 36.8640 Sample Rate LRCK (kHz) MCLK (MHz) 256x 384x 512x 768x 8.1920 12.2880 16.3840 24.5760 44.1 11.2896 16.9344 22.5792 33.8688 12.2880 18.4320 24.5760 36.8640 Sample Rate LRCK (kHz) MCLK (MHz) 128x 192x 256x 384x 8.1920 12.2880 16.3840 24.5760 88.2 11.2896 16.9344 22.5792 33.8688 12.2880 18.4320 24.5760 36.8640

1. PCB LAYOUT CONSIDERATIONS 9.1 Power Supply, Grounding As with any high-resolution converter, the CS43L21 requires careful attention to power supply and ground- ing arrangements if its potential performance is to be realized. Figure 1 on page 9 shows the recommended power arrangements, with VA and VA_HP connected to clean supplies. VD, which powers the digital circuit- ry, may be run from the system logic supply. Alternatively, VD may be powered from the analog supply via a ferrite bead. In this case, no additional devices should be powered from VD. Extensive use of power and ground planes, ground plane fill in unused areas and surface mount decoupling capacitors are recommended. Decoupling capacitors should be as close to the pins of the CS43L21 as pos- sible. The low value ceramic capacitor should be closest to the pin and should be mounted on the same side of the board as the CS43L21 to minimize inductance effects. All signals, especially clocks, should be kept away from the FILT+ and VQ pins in order to avoid unwanted coupling into the modulators. The FILT+ and VQ decoupling capacitors, particularly the 0.1 µF, must be positioned to minimize the electrical path from FILT+ and AGND. The CS43L21 evaluation board demonstrates the optimum layout and power supply arrangements. 9.2 QFN Thermal Pad The CS43L21 is available in a compact QFN package. The under side of the QFN package reveals a large metal pad that serves as a thermal relief to provide for maximum heat dissipation. This pad must mate with an equally dimensioned copper pad on the PCB and must be electrically connected to ground. A series of vias should be used to connect this copper pad to one or more larger ground planes on other PCB layers. In split ground systems, it is recommended that this thermal pad be connected to AGND for best perfor- mance. The CS43L21 evaluation board demonstrates the optimum thermal pad and via configuration.

11.PARAMETER DEFINITIONS Dynamic Range The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. Dynamic Range is a signal-to-noise ratio measurement over the specified band width made with a -60 dBFS signal. 60 dB is added to resulting measurement to refer the measurement to full-scale. This technique ensures that the distortion components are below the noise level and do not affect the measure- ment. This measurement technique has been accepted by the Audio Engineering Society, AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307. Expressed in decibels. Total Harmonic Distortion + Noise The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified band width (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels. Measured at -1 and -20 dBFS as suggested in AES17-1991 Annex A. Frequency Response A measure of the amplitude response variation from 10 Hz to 20 kHz relative to the amplitude response at 1 kHz. Units in decibels. Interchannel Isolation A measure of crosstalk between the left and right channel pairs. Measured for each channel at the convert- er's output with no signal to the input under test and a full-scale signal applied to the other channel. Units in decibels. Interchannel Gain Mismatch The gain difference between left and right channel pairs. Units in decibels. Gain Error The deviation from the nominal full-scale analog output for a full-scale digital input. Gain Drift The change in gain value with temperature. Units in ppm/°C. Offset Error

12.PACKAGE DIMENSIONS Dimensioning and tolerance per ASME Y 14.5M-1995. Dimensioning lead width applies to the plated terminal and is measured between 0.20 mm and 0.25 mm from the terminal tip. THERMAL CHARACTERISTICS INCHES MILLIMETERS NOTE DIM MIN NOM MAX MIN NOM MAX A 0.0394 1.00 0.0000 0.0020 0.00 0.05 b 0.0071 0.0091 0.0110 0.18 0.23 0.28 1,2 D

0.1969 BSC

5.00 BSC

0.1280 0.1299 0.1319 3.25 3.30 3.35 E 0.1280 0.1299 0.1319 3.25 3.30 3.35 e

0.0197 BSC

0.50 BSC

L 0.0118 0.0157 0.0197 0.30 0.40 0.50 JEDEC #: MO-220 Controlling Dimension is Millimeters. Parameter Symbol Min Typ Max Units Junction to Ambient Thermal Impedance

2 Layer Board

4 Layer Board

θJA °C/Watt Side View Bottom View Top View A Pin #1 Corner D E L b e Pin #1 Corner 32L QFN (5 X 5 mm BODY) PACKAGE DRAWING

13.ORDERING INFORMATION 14.REFERENCES Cirrus Logic, AN18: Layout and Design Rules for Data Converters and Other Mixed Signal Devices, Version 6.0, February 1998. Cirrus Logic, How to Achieve Optimum Performance from Delta-Sigma A/D and D/A Converters, by Steven Harris. Presented at the 93rd Convention of the Audio Engineering Society, October 1992. Cirrus Logic, A Fifth-Order Delta-Sigma Modulator with 110 dB Audio Dynamic Range, by I. Fujimori, K. Ha- mashita and E.J. Swanson. Paper presented at the 93rd Convention of the Audio Engineering Society, Oc- tober 1992. Philips Semiconductor, The I²C-Bus Specification: Version 2.1, January 2000. http://www.semiconductors.philips.com 15.REVISION HISTORY Product Order # CS43L21 Low-Power Stereo D/A with HP Amp for Portable Apps 32L-QFN Yes Commercial -10 to +70° C Rail CS43L21-CNZ Tape & Reel CS43L21-CNZR Automotive -40 to +85° C Rail CS43L21-DNZ Tape & Reel CS43L21-DNZR CDB43L21 CS43L21 Evaluation Board No CDB43L21 Revision Changes Initial Release Contacting Cirrus Logic Support For all product questions and inquiries, contact a Cirrus Logic Sales Representative. To find one nearest you, go to www.cirrus.com. IMPORTANT NOTICE "Advance" product information describes products that are in development and subject to development changes. Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the infor- mation only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROP- ERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DE- VICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDER- STOOD TO BE FULLY AT THE CUSTOMER’S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER’S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS’ FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. I²C is a registered trademark of Philips Semiconductor. SPI is a trademark of Motorola, Inc.