CDB4382A

CS4382A_05 CIRRUS | Alldatasheet

Document overview

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Technical content

Features

! Advanced Multi-bit Delta Sigma Architecture ! 24-bit Conversion ! Up to 192 kHz Sample Rates ! 114 dB Dynamic Range ! -100 dB THD+N ! Direct Stream Digital Mode ! On-Chip 50 kHz Filter ! Matched PCM and DSD Analog Output Levels ! Selectable Digital Filters ! Volume Control with 1-dB Step Size and Soft Ramp ! Low Clock-Jitter Sensitivity ! +5 V Analog Supply, +2.5 V Digital Supply ! Separate 1.8 to 5 V Logic Supplies for the Control & Serial Ports

Description

The CS4382A is a complete 8-channel digital-to-analog system. This D/A system includes digital de-emphasis, one-dB step size volume control, ATAPI channel mix- ing, selectable fast and slow digital interpolation filters followed by an oversampled, multi-bit delta sigma mod- ulator whitch includes mi smatch shaping technology that eliminates distortion due to capacitor mismatch. Following this stage is a multi-element switched capac- itor stage and low-pass filt er with differential analog outputs. The CS4382A also has a proprietary DSD processor which allows for 50 kHz on-ch ip filtering without an in- termediate decimation stage. The CS4382A is available in a 48-pin LQFP package in both Commercial (-10° to +70°C) and Automotive grades (-40° to +85°C). The CDB4382A Customer Demonstration board is also available for device evaluation and implementation sug- gestions. Please see “Ordering Information” on page 47 for complete details. The CS4382A accepts PCM data at sample rates from 4 kHz to 216 kHz, DSD audio data, and delivers excel- lent sound quality. These features are ideal for multi- channel audio systems including SACD players, A/V re- ceivers, digital TV’s, mixing consoles, effects processors, sound cards and automotive audio systems. Control & Serial Audio Port Supplies = 1.8 V to 5 V Register/Hardware Configuration Internal Voltage Reference Reset Serial Interface Level TranslatorLevel Translator Digital Supply = 2.5 V Hardware Mode or I2C/SPI Software Mode Control Data Analog Supply = 5 V Differential Outputs PCM Serial Audio Input Volume Controls Digital Filters Switch-Cap DAC and Analog Filters Multi-bit ∆Σ Modulators DSD Audio Input DSD Processor -50 kHz filter External Mute Control Mute Signals2 NOVEMBER '05 DS618PP2 CS4382A

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6.6 Mixing Control Pair 1 (Channels A1 & B1)(address 06h)

Mixing Control Pair 2 (Channels A2 & B2)(address 09h) Mixing Control Pair 3 (Channels A3 & B3)(address 0Ch)

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1. PIN DESCRIPTION Pin Name # Pin Description VD 4 Digital Power (Input) - Positive power supply for the digital section. GND 5 31 Ground (Input) - Ground reference. Should be connected to analog ground. MCLK 6 Master Clock (Input) - Clock source for the delta-sigma modulator and digital filters. LRCK 7 Left Right Clock (Input) - Determines which channel, Left or Right, is currently active on the serial audio data line. The frequency of the left/right clock must be at the audio sample rate, Fs. SDIN1 SDIN2 SDIN3 SDIN4 Serial Audio Data Input (Input) - Input for two’s complement serial audio data. SCLK 9 Serial Clock (Input) - Serial clock for the serial audio interface. VLC 18 Control Port Power (Input) - Determines the required signal level for the Control Port. Refer to the Recommended Operating Conditions for appropriate voltages. RST 19 Reset (Input) - The device enters a low power mode and all internal registers are reset to their default settings when low. FILT+ 20 Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling circuits. Requires the capacitive decoupling to analog ground, as shown in the Typical Connection Diagram. VQ 21 Quiescent Voltage (Output) - Filter connection for internal quiescent voltage. VQ must be capaci- tively coupled to analog ground, as shown in the Typical Connection Diagram. The nominal voltage level is specified in the Analog Characteristics and Specifications section. VQ presents an apprecia- ble source impedance and any current drawn from this pin will alter device performance. However, VQ can be used to bias the analog circuitry assuming there is no AC signal component and the DC current is less than the maximum specified in the Analog Characteristics and Specifications section. MUTEC1 MUTEC234 Mute Control (Output) - The Mute Control pins go high during power-up initialization, reset, muting, power-down or if the master clock to left/right clock frequency ratio is incorrect. These pins are intended to be used as a control for external mute circuits to prevent the clicks and pops that can occur in any single supply system. The use of external mute circuits are not mandatory but may be desired for designs requiring the absolute minimum in extraneous clicks and pops. SDIN3 GND AOUTB2- AOUTA3+ AOUTB3- AOUTB2+ VA AOUTA3- AOUTB3+ AOUTA4- AOUTA4+ 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 MCLK DSDB1 VD SDIN1 TST DSDA2 DSDA1 GND SCLK SDIN2 TST LRCK(DSD_EN) M3(DSD_SCLK) DSDB3 DSDA3 DSDA4 CS4382A DSDB4 VLS SDIN4 M2(SCL/CCLK) M1(SDA/CDIN) VLC RST FILT+ VQ MUTEC2 AOUTB4- AOUTB4+ M0(AD0/CS) AOUTA2+ AOUTA2- AOUTB1+ AOUTB1- AOUTA1- AOUTA1+ DSDB2 MUTEC1

AOUTA1 +,- AOUTB1 +,- AOUTA2 +,- AOUTB2 +,- AOUTA3 +,- AOUTB3 +,- AOUTA4 +,- AOUTB4 +,- 39, 40 38, 37 35, 36 34, 33 29, 30 28, 27 25, 26 24, 23 Differential Analog Output (Output) - The full-scale differential analog output level is specified in the Analog Characteristics specification table. VA 32 Analog Power (Input) - Positive power supply for the analog section. VLS 43 Serial Audio Interface Power (Input) - Determines the required signal level for the serial audio inter- face. Refer to the Recommended Operating Conditions for appropriate voltages. TST 10 12 Test - These pins need to be tied to analog ground. Software Mode Definitions SCL/CCLK 15 Serial Control Port Clock (Input) - Serial clock for the serial Control Port. Requires an external pull- up resistor to the logic interface voltage in I²C Mode as shown in the Typical Connection Diagram. SDA/CDIN 16 Serial Control Data (Input/Output) - SDA is a data I/O line in I²C Mode and requires an external pull- up resistor to the logic interface voltage, as shown in the Typical Connection Diagram. CDIN is the input data line for the Control Port interface in SPI Mode. AD0/CS

17 Address Bit 0 (I²C) / Control Port Chip Select (SPI) (Input) - AD0 is a chip address pin in I²C Mode;

CS is the chip select signal for SPI format. Stand-Alone Definitions Mode Selection (Input) - Determines the operational mode of the device. DSD Definitions DSD_SCLK 42 DSD Serial Clock (Input) - Serial clock for the Direct Stream Digital audio interface. DSD_EN 7 DSD-Enable (Input) - When held at logic ‘1’ the device will enter DSD Mode (Stand-Alone mode only). DSDA1 DSDB1 DSDA2 DSDB2 DSDA3 DSDB3 DSDA4 DSDB4 Direct Stream Digital Input (Input) - Input for Direct Stream Digital serial audio data. Pin Name # Pin Description

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1. CHARACTERISTICS AND SPECIFICATIONS All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical performance characteristics and specifications are derived from measurements taken at nominal supply voltage and TA = 25°C. SPECIFIED OPERATING CONDITIONS (GND = 0 V; all voltages with respect to ground.) ABSOLUTE MAXIMUM RATINGS (GND = 0 V; all voltages with respect to ground.) WARNING: Operation at or beyond these limit s may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. Parameters Symbol Min Typ Max Units DC Power Supply Analog power Digital internal power Serial data port interface power Control Port interface power VA VD VLS VLC 4.75 2.37 1.71 1.71 5.0 2.5 5.0 5.0 5.25 2.63 5.25 5.25 V V V V Specified Temperature Range -CQZ -DQZ TA -10 -40 +70 +85 Parameters Symbol Min Max Units DC Power Supply Analog power Digital internal power Serial data port interface power Control Port interface power VA VD VLS VLC -0.3 -0.3 -0.3 -0.3 6.0 3.2 6.0 6.0 V V V V Input Current Any Pin Except Supplies I in -± 1 0 m A Digital Input Voltage Serial data port interface Control Port interface VIND-S VIND-C -0.3 -0.3 VLS+ 0.4 VLC+ 0.4 V V Ambient Operating Temperature (power applied) T op -55 125 °C Storage Temperature T stg -65 150 °C

DAC ANALOG CHARACTERISTICS Full-Scale Output Sine Wave, 997 Hz (Note 1); Fs = 48/96/192 kHz; Test load RL = 3 kΩ, CL = 100 pF; Measure- ment Bandwidth 10 Hz to 20 kHz, unless otherwise specified. Notes: 1. One-half LSB of triangular PDF dither is added to data. 2. Performance limited by 16-bit quantization noise. Parameters Symbol Min Typ Max Unit CS4382A-CQZ Dynamic Performance - All PCM Modes and DSD Specified Temperature Range T A -10 - 70 °C Dynamic Range 24-bit A-weighted unweighted 16-bit A-weighted (Note 2) unweighted 108 105 114 111 dB dB dB dB Total Harmonic Distortion + Noise 24-bit 0 dB -20 dB -60 dB (Note 2) 16-bit 0 dB -20 dB -60 dB THD+N -100 -91 -51 -94 -74 -34 -94 -45 dB dB dB dB dB dB Idle Channel Noise / Signal-to-noise ratio - 114 - dB CS4382A-DQZ Dynamic Performance - All PCM Modes and DSD Specified Temperature Range T A -40 - 85 °C Dynamic Range (Note 1) 24-bit A-weighted unweighted 16-bit A-weighted (Note 2) unweighted 105 102 114 111 dB dB dB dB Total Harmonic Distortion + Noise (Note 1) 24-bit 0 dB -20 dB -60 dB (Note 2) 16-bit 0 dB -20 dB -60 dB THD+N -100 -91 -51 -94 -74 -34 -91 -42 dB dB dB dB dB dB Idle Channel Noise / Signal-to-noise ratio - 114 - dB

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DAC ANALOG CHARACTERISTICS - ALL MODES (CONTINUED) POWER AND THERMAL CHARACTERISTICS Notes: 3. V FS is tested under load RL and includes attenuation due to ZOUT 4. Current consumption increases with increasing FS within a given speed mode and is signal-dependent. Max values are based on highest FS and highest MCLK. 5. I LC measured with no external loading on the SDA pin. 6. Power-Down Mode is defined as RST pin = Low with all clock and data lines held static. 7. Valid with the recommended capacitor values on FILT+ and VQ as shown in Figures 5 and 6. Parameters Symbol Min Typ Max Units Interchannel Isolation (1 kHz) - 110 - dB DC Accuracy Interchannel Gain Mismatch - 0.1 - dB Gain Drift - 100 - ppm/°C Analog Output Full Scale Differential- PCM, DSD processor Output Voltage Direct DSD Mode VFS 132%•VA 94%•VA 134%•VA 96%•VA 136%•VA 98%•VA Vpp Vpp Output Impedance (Note 3) ZOUT -1 3 0 - Ω Max DC Current draw from an AOUT pin I OUTmax -1 . 0 - m A Min AC-Load Resistance R L -3 - k Ω Max Load Capacitance C L -1 0 0 - p F Quiescent Voltage V Q - 50% V A -V D C Max Current draw from VQ IQMAX -1 0 - µA Parameters Symbol Min Typ Max Units Power Supplies Power Supply Current normal operation, VA= 5 V (Note 4) VD= 2.5 V (Note 5) Interface current, VLC=5 V VLS=5 V (Note 6) power-down state (all supplies) IA ID ILC ILS Ipd 200 mA mA µA µA µA Power Dissipation (Note 4) V A = 5V , V D = 2 . 5V normal operation (Note 6) power-down 426 482 mW mW Package Thermal Resistance θ JA θJC °C/Watt °C/Watt Power Supply Rejection Ratio (Note 7) (1 kHz) (60 Hz) PSRR - dB dB

COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE The filter characteristics have been normalized to the sample rate (Fs) and can be referenced to the desired sam- ple rate by multiplying the given characteristic by Fs. See Note 12. Notes: 8. Slow roll-off interpolation filter is only available in Software Mode. 9. Response is clock-dependent and will scale with Fs. 10. For Single-Speed Mode, the Measurement Bandwidth is from stopband to 3 Fs. For Double-Speed Mode, the Measurement Bandwidth is from stopband to 3 Fs. For Quad-Speed Mode, the Measurement Bandwidth is from stopband to 1.34 Fs. 11. De-emphasis is available only in Single-Speed Mode; only 44.1 kHz De-emphasis is available in Hard- ware Mode. 12. Amplitude vs. Frequency plots of this data are available in Section 7. “Filter Plots” on page 41 . Parameter Fast Roll-Off UnitMin Typ Max Combined Digital and On-chip Analog Filter Response - Single-Speed Mode - 48 kHz Passband (Note 9) to -0.01 dB corner to -3 dB corner .454 .499 Fs Fs Frequency Response 10 Hz to 20 kHz -0.01 - +0.01 dB StopBand 0.547 - - Fs StopBand Attenuation (Note 10) 102 - - dB Group Delay - 10.4/Fs - s De-emphasis Error (Note 11) Fs = 32 kHz (Relative to 1 kHz) Fs = 44.1 kHz Fs = 48 kHz ±0.23 ±0.14 ±0.09 dB dB dB Combined Digital and On-chip Analog Filter Response - Double-Speed Mode - 96 kHz Passband (Note 9) to -0.01 dB corner to -3 dB corner .430 .499 Fs Fs Frequency Response 10 Hz to 20 kHz -0.01 - +0.01 dB StopBand .583 - - Fs StopBand Attenuation (Note 10) 80 - - dB Group Delay - 6.15/Fs - s Combined Digital and On-chip Analog Filter Response - Quad-Speed Mode - 192 kHz Passband (Note 9) to -0.01 dB corner to -3 dB corner .105 .490 Fs Fs Frequency Response 10 Hz to 20 kHz -0.01 - +0.01 dB StopBand .635 - - Fs StopBand Attenuation (Note 10) 90 - - dB Group Delay - 7.1/Fs - s

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COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE (CONTINED) DSD COMBINED DIGITAL & ON-CHIP ANALOG FILTER RESPONSE Parameter Slow Roll-Off (Note 8) UnitMin Typ Max Single-Speed Mode - 48 kHz Passband (Note 9) to -0.01 dB corner to -3 dB corner 0.417 0.499 Fs Fs Frequency Response 10 Hz to 20 kHz -0.01 - +0.01 dB StopBand .583 - - Fs StopBand Attenuation (Note 10) 64 - - dB Group Delay - 7.8/Fs - s De-emphasis Error (Note 11) Fs = 32 kHz (Relative to 1 kHz) Fs = 44.1 kHz Fs = 48 kHz ±0.36 ±0.21 ±0.14 dB dB dB Double-Speed Mode - 96 kHz Passband (Note 9) to -0.01 dB corner to -3 dB corner .296 .499 Fs Fs Frequency Response 10 Hz to 20 kHz -0.01 - +0.01 dB StopBand .792 - - Fs StopBand Attenuation (Note 10) 70 - - dB Group Delay - 5.4/Fs - s Quad-Speed Mode - 192 kHz Passband (Note 9) to -0.01 dB corner to -3 dB corner .104 .481 Fs Fs Frequency Response 10 Hz to 20 kHz -0.01 - +0.01 dB StopBand .868 - - Fs StopBand Attenuation (Note 10) 75 - - dB Group Delay - 6.6/Fs - s Parameter Min Typ Max Unit DSD Processor mode Passband (Note 9) to -3 dB corner 0 - 50 kHz Frequency Response 10 Hz to 20 kHz -0.05 - +0.05 dB Roll-off 27 - - dB/Oct

1. Any pin except supplies. Transient currents of up to ±100 mA on the input pins will not cause SCR latch- up Parameters Symbol Min Typ Max Units Input Leakage Current (Note 13) Iin -- ± 1 0 µA Input Capacitance - 8 - pF High-Level Input Voltage Serial I/O Control I/O VIH VIH 70% 70% VLS VLC Low-Level Input Voltage Serial I/O Control I/O VIL VIL 30% 30% VLS VLC High-Level Output Voltage (IOH = -1.2 mA) Control I/O V OH 80% - - V LC Low-Level Output Voltage (IOL = 1.2 mA) Control I/O V OL -- 2 0 % V LC Maximum MUTEC Drive Current I max -3- m A MUTEC High-Level Output Voltage V OH -V A- V MUTEC Low-Level Output Voltage V OL -0- V

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1. After powering up, RST should be held low until after the power supplies and clocks are settled.
2. See Table 1 on page 20 for suggested MCLK frequencies.

Figure 1. Serial Audio Interface Timing

Figure 2. Direct Stream Digital - Serial Audio Input Timing

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1. Data must be held for sufficient ti me to bridge the transition time, tfc, of SCL.

Figure 3. Control Port Timing - I²C Format

1. t spi only needed before first falling edge of CS after RST rising edge. tspi = 0 at all other times.
2. Data must be held for sufficient time to bridge the transition time of CCLK.

Figure 4. Control Port Timing - SPI Format

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1. TYPICAL CONNECTION DIAGRAM

48 DSDB2

42 DSD_SCLK

44 DSDB4

15 SCL/CCLK

Figure 5. Typical Connection Diagram, Software Mode

36 Analog Conditioning

42 M3(DSD_SCLK)

Figure 6. Typical Connection Diagram, Hardware Mode

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on SDINx, and the Serial Clock (SCLK) clocks audio data into the input data buffer.

4.1 Master Clock

quired phase relationship, but MCLK, LRCK and SCLK must be synchronous.

4.2 Mode Select

Note: These modes are only available in Software Mode by setting the MCLKDIV bit = 1. Table 1. Common Clock Frequencies

(DIF1) (DIF0) DESCRIPTION FORMAT FIGURE

00 Left-Justified, up to 24-bit data 0 Figure 7

01 I²S, up to 24-bit data 1 Figure 8

10 Right-Justified, 16-bit Data 2 Figure 9

11 Right-Justified, 24-bit Data 3 Figure 10

Table 2. Digital Interface Format, Stand-Alone Mode Options

00 Single-Speed without De-Emphasis (4 to 50 kHz sample rates)

01 Single-Speed with 44.1 kHz De-Emphasis; see Figure 13

10 Double-Speed (50 to 100 kHz sample rates)

11 Quad-Speed (100 to 200 kHz sample rates)

Table 3. Mode Selection, Stand-Alone Mode Options Table 4. Direct Stream Digital (DSD), Stand-Alone Mode Options

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4.3 Digital Interface Formats

Figure 7. Format 0 - Left-Justified up to 24-bit Data Figure 8. Format 1 - I²S up to 24-bit Data Figure 9. Format 2 - Right-Justified 16-bit Data Figure 10. Format 3 - Right-Justified 24-bit Data

4.4 Oversampling Modes

supports input sample rates up to 200 kHz and uses an oversampling ratio of 32x.

4.5 Interpolation Filter

Plots” on page 41 for more details). When in Hardware Mode, only the “fast” roll-off filter is available. Filter specifications can be found in Section 2, and filter response plots can be found in Figures 19 to 42.

4.6 De-Emphasis

modate older audio recordings th at utilize pre-emphasis equalizatio n as a means of noise reduction. Figure 11. Format 4 - Right-Justified 20-bit Data Figure 12. Format 5 - Right-Justified 18-bit Data

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via the de-emphasis control bits. filter will be scaled by a factor of the actual Fs over 44,100.

4.7 ATAPI Specification

Figure 13. De-Emphasis Curve Figure 14. ATAPI Block Diagram (x = channel pair 1, 2, 3, or 4)

4.8 Direct Stream Digital (DSD) Mode

In Stand-Alone Mode, DSD operation is selected by holding DSD_EN(LRCK) high and applying the DSD data and clocks to the appropriate pins. The M[2:0] pins set the expected DSD rate and MCLK ratio. In Control Port Mode, the FM bits set the device in to DSD Mode (DSD_EN pin is not required to be held high). The DIF register then controls the expected DSD rate and MCLK ratio. During DSD operation, the PCM related pins should either be tied low or remain active with clocks (except LRCK in Stand-Alone Mode). When the DSD related pins are not being used, they should either be tied stat- ic low or remain active with clocks (except M3 in Stand-Alone Mode).

4.9 Grounding and Power Supply Arrangements

As with any high resolution converter, the CS4382A requires careful attention to power supply and ground- ing arrangements if its potential performance is to be realized. The Typical Connection Diagram shows the recommended power arrangements, with VA, VD, VLC, and VLS connected to clean supplies. If the ground planes are split between digital ground and analog gr ound, the GND pins of the CS4382A should be con- nected to the analog ground plane. All signals, especially clocks, should be kept away from the FILT+ and VQ pins in order to avoid unwanted coupling into the DAC.

4.9.1 Capacitor Placement

Decoupling capacitors should be placed as close to the DAC as possible, with the low value ceramic ca- pacitor being the closest. To further minimize impedance, these capacitors should be located on the same layer as the DAC. If desired, all su pply pins with similar voltage ra tings may be connected to the same supply, but a decoupling capacitor should still be placed on each supply pin. Notes: All decoupling capacitors should be referenced to analog ground. The CDB4382A evaluation board demonstrates the optimum layout and power supply arrangements.

4.10 Analog Output and Filtering

The application note “Design Notes fo r a 2-Pole Filter with Differential Input” discusses the second-order Butterworth filter and differential to single-ended converter which was implemented on the CS4382A eval- uation board, CDB4382A, as seen in Figure 16. The CS4382A does not include phase or amplitude com- pensation for an external filter. Therefore, the DAC system phase and amplitude response will be dependent on the external analog circuitry. The off-chip filter has been designed to attenuate the typical full-scale out- put level to below 2 Vrms. Figure 15 shows how the full-scale differential analog output level specification is derived.

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4.11 Mute Control

and pops that can occur in any single-ended, single-supply system. to achieve idle channel noise/signal-to-noise ratios which are only limited by the external mute circuit. Please see the CDB4382A data sheet for a suggested mute circuit. Figure 15. Full-Scale Output Figure 16. Recommended Output Filter

4.12 Recommended Power-Up Sequence

4.12.1 Hardware Mode

1. Hold RST low until the power supplies and configuration pins are stable, and the master and left/right clocks are locked to the appropriate frequencies, as discussed in Section 4.1. In this state, the registers are reset to the default settings, FILT+ will remain low, and VQ will be connected to VA/2. If RST can not be held low long enough the SDINx pins should remain static low until all other clocks are stable, and if possible the RST should be toggled low again once the system is stable. 2. Bring RST high. The device will remain in a low power state with FILT+ low and will initiate the Hardware power-up sequence after approximately 512 LRCK cycles in Single-Speed Mode (1024 LRCK cycles in Double-Speed Mode, and 2048 LRCK cycles in Quad-Speed Mode).

4.12.2 Software Mode

1. Hold RST low until the power supply is stable, and the master and left/right clocks are locked to the appropriate frequencies, as discussed in Section 4.1. In this state, the registers are reset to the default settings; FILT+ will remain low, and VQ will be connected to VA/2. 2. Bring RST high. The device will remain in a low-power state with FILT+ low for 512 LRCK cycles in Single-Speed Mode (1024 LRCK cycles in Double-Speed Mode, and 2048 LRCK cycles in Quad- Speed Mode). 3. In order to reduce the chances of clicks and po ps, perform a write to the CP_EN bit prior to the completion of approximately 512 LRCK cycles in Single-Speed Mode (1024 LRCK cycles in Double- Speed Mode, and 2048 LRCK cycles in Quad-Speed Mode). The desired register settings can be loaded while keeping the PDN bit set to 1. Set the RMP_UP and RMP_DN bits to 1; then set the format and mode control bits to the desired settings. If more than the stated number of LRCK cycles passes before CPEN bit is written, the chip will enter Hardware Mode and begin to operate with the M0-M3 as the mode settings. CPEN bit may be written at anytime, even after the Hardware sequence has begun. It is advised that if the CPEN bit cannot be set in time, the SDINx pins should remain static low (this way, no audio data can be converted incorrectly by the Hardware Mode settings). 4. Set the PDN bit to 0. This will initiate the powe r-up sequence, which lasts approximately 50 µs.

4.13 Recommended Procedure for Switching Operational Modes

For systems where the absolute minimum in clicks and pops is required, it is recommended that the MUTE bits are set prior to changing significant DAC function s (such as changing sample rates or clock sources). The mute bits may then be released after clocks have settled and the proper modes have been set. It is required to have the device held in reset if the minimum high/l ow time specs of MCLK cannot be met during clock source changes.

4.14 Control Port Interface

The Control Port is used to load all the internal register settings in order to operate in Software Mode (see the “Filter Plots” on page 41). The operation of the Control Port ma y be completely asynchronous with the audio sample rate. However, to avoid potential interference problems, the Control Port pins should remain static if no operation is required. The Control Port operates in one of two modes: I²C or SPI.

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4.14.1 MAP Auto Increment

The device has MAP (memory address pointer) auto increment capability enabled by the INCR bit (also the MSB) of the MAP. If INCR is set to 0, MAP will stay constant for successive I²C writes or reads and SPI writes. If INCR is set to 1, MAP will auto increment after each byte is written, allowing block reads or writes of successive registers.

4.14.2 I²C Mode

In the I²C Mode, data is clocked into and out of the bi-directional serial control data line, SDA, by the serial Control Port clock, SCL (see Figure 17 for the clock to data relationship). There is no CS pin. Pin AD0 enables the user to alter the chip address (001100[AD0][R/W]) and should be tied to VLC or GND, as re- quired, before powering up the device. If the device ever detects a high-to-low transition on the AD0/CS pin after power-up, SPI Mode will be selected.

4.14.2.1 I²C Write

To write to the device, follow the procedure below while adhering to the Control Port Switching Specifica- tions in Section 2. 1. Initiate a START condition to the I²C bus followed by the address byte. The upper 6 bits must be 001100. The seventh bit must match the setting of the AD0 pin, and the eighth must be 0. The eighth bit of the address byte is the R/W bit. 2. Wait for an acknowledge (ACK) from the part; then write to the memory address pointer, MAP. This byte points to the register to be written. 3. Wait for an acknowledge (ACK) from the part; then write the desired data to the register pointed to by the MAP. 4. If the INCR bit (see Section 4.14.1) is set to 1, repeat the previous step until all the desired registers are written, then initiate a STOP condition to the bus. 5. If the INCR bit is set to 0 and further I²C writes to other registers are desired, it is necessary to initiate a repeated START condition and follow the procedure detailed from step 1. If no further writes to other registers are desired, initiate a STOP condition to the bus.

4.14.2.2 I²C Read

To read from the device, follow the procedure below while adhering to the Control Port Switching Speci- fications. 1. Initiate a START condition to the I²C bus followed by the address byte. The upper 6 bits must be 001100. The seventh bit must match the setting of the AD0 pin, and the eighth must be 1. The eighth bit of the address byte is the R/W bit. 2. After transmitting an acknowled ge (ACK), the device will then tran smit the contents of the register pointed to by the MAP. The MAP re gister will contain the address of th e last register written to the MAP, or the default address (see Section 4.14.1) if an I²C read is the first operation performed on the device. 3. Once the device has transmitted the contents of the register pointed to by the MAP, issue an ACK. 4. If the INCR bit is set to 1, the device will continue to transmit the contents of successive registers. Con- tinue providing a clock and issue an ACK after each byte until all the desired registers are read; then initiate a STOP condition to the bus. 5. If the INCR bit is set to 0 and further I²C reads from other registers are desired, it is necessary to initiate a repeated START condition and follow the procedure detailed from steps 1 and 2 from the I²C Write

sired, initiate a STOP condition to the bus.

4.14.3 SPI ™ Mode

4.14.3.1 SPI Write

1. The address byte on the CDIN pin must then be 00110000.
2. Write to the memory address pointer, MAP. This byte points to the register to be written.
3. Write the desired data to the register pointed to by the MAP.
4. If the INCR bit (see Section 4.14.1) is set to 1, repeat the previous step until all the desired registers
5. If the INCR bit is set to 0 and furt her SPI writes to other registers are desired, it is necessary to bring

001100 ADDR

Note: If operation is a write, this byte contains the Memory Address Pointer, MAP. Figure 17. Control Port Timing, I²C Mode Figure 18. Control Port Timing, SPI Mode

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4.15 Memory Address Po inter (MAP)

4.16 INCR (Auto Map Increment Enable)

Default = ‘0’ 0 - Disabled 1 - Enabled

4.16.1 MAP4-0 (Memory Address Pointer)

Default = ‘00000’ 76543210 INCR Reserved Reserved MAP4 MAP3 MAP2 MAP1 MAP0 00000000

1. REGISTER QU ICK REFERENCE Addr Function 7 6 5 4 3 2 1 0 01h Mode Control 1 CPEN FREEZE MCLKDIV DAC4_DIS DAC3_DIS DAC2_DIS DAC1_DIS PDN default 00 0 00001 02h Mode Control 2 Reserved DIF2 DIF1 DIF0 Reserved Reserved Reserved Reserved default 00000000 03h Mode Control 3 SZC1 SZC0 SNGLVOL RMP_UP MUTEC+/- AMUTE Reserved MUTEC default 10000100 04h Filter Control Reserved Reserved Reserved FILT_SEL Reserved DEM1 DEM0 RMP_DN default 00000000 05h Invert Control INV_B4 INV_B3 INV_B3 INV_A3 INV_B2 INV_A2 INV_B1 INV_A1 default 00000000 06h Mixing Control Pair 1 (AOUTx1) P1_A=B P1ATAPI4 P1ATAPI3 P1ATAPI2 P1ATAPI1 P1ATAPI0 FM1 FM0 default 00100100 07h Vol. Control A1 A1_MUTE A1_VOL6 A1_VOL 5 A1_VOL4 A1_VOL3 A1_VOL2 A1_VOL1 A1_VOL0 default 00000000 08h Vol. Control B1 B1_MUTE B1_VOL6 B1_VOL 5 B1_VOL4 B1_VOL3 B1_VOL2 B1_VOL1 B1_VOL0 default 00000000 09h Mixing Control Pair 2 (AOUTx2) P2_A=B P2ATAPI4 P2ATAPI3 P2ATAPI2 P2ATAPI1 P2ATAPI0 Reserved Reserved default 00100100 0Ah Vol. Control A2 A2_MUTE A2_VOL6 A2_VOL5 A2_VOL4 A2_VOL3 A2_VOL2 A2_VOL1 A2_VOL0 default 00000000 0Bh Vol. Control B2 B2_MUTE B2_VOL6 B2_VOL5 B2_VOL4 B2_VOL3 B2_VOL2 B2_VOL1 B2_VOL0 default 00000000 0Ch Mixing Control Pair 3 (AOUTx3) P3_A=B P3ATAPI4 P3ATAPI3 P3ATAPI2 P3ATAPI1 P3ATAPI0 Reserved Reserved default 00100100 0Dh Vol. Control A3 A3_MUTE A3_VOL6 A3_VOL5 A3_VOL4 A3_VOL3 A3_VOL2 A3_VOL1 A3_VOL0 default 00000000 0Eh Vol. Control B3 B3_MUTE B3_VOL6 B3_VOL5 B3_VOL4 B3_VOL3 B3_VOL2 B3_VOL1 B3_VOL0 default 00000000 0Fh Mixing Control Pair 4 (AOUTx4) P4_A=B P4ATAPI4 P4ATAPI4 P4ATAPI2 P4ATAPI1 P4ATAPI0 Reserved Reserved default 00100100 10h Vol. Control A4 A4_MUTE A4_VOL6 A4_VOL 5 A4_VOL4 A4_VOL3 A4_VOL2 A4_VOL1 A4_VOL0 default 00000000 11h Vol. Control B4 B4_MUTE B4_VOL6 B4_VOL5 B4_VOL4 B4_VOL3 B4_VOL2 B4_VOL1 B4_VOL0 default 00000000 12h Chip Revision PART4 PART3 PART2 PART1 PART0 REV REV REV default 01110xxx

32 DS618PP2

1. REGISTER DESCRIPTION Note: All registers are read/write in I²C Mode and write only in SPI, unless otherwise noted.

6.1 Mode Control 1 (address 01h)

6.1.1 Control Port Enable (CPEN)

Default = 0 0 - Disabled 1 - Enabled Function: This bit defaults to 0, allowing the device to power-up in Stand-Alone Mode. The Control Port Mode can be accessed by setting this bit to 1. This will allow the operation of the device to be controlled by the reg- isters and the pin definitions will conform to Control Port Mode. To accomplish a clean power-up, the user should write this bit within 10 ms following the release of Reset.

6.1.2 Freeze Controls (Freeze)

Default = 0 0 - Disabled 1 - Enabled Function: This function allows modifications to be made to th e registers without the changes taking effect until the FREEZE is disabled. To make multiple changes in the Control Port registers take effect simultaneously, enable the FREEZE Bit, make all register changes, then Disable the FREEZE bit.

6.1.3 Master Clock DIVI DE ENABLE (mclkdiv)

Default = 0 0 - Disabled 1 - Enabled Function: The MCLKDIV bit enables a circuit which divides the externally applied MCLK signal by 2 prior to all other internal circuitry.

6.1.4 DAC Pair Disable (DACx_DIS)

Default = 0 0 - Enabled 1 - Disabled Function: When enabled the respective DAC channel pair x (AOUTAx and AOUTBx) will remain in a reset state. It is advised that changes to these bits be made while the power down bit is enabled to eliminate the pos- sibility of audible artifacts. 76543210 CPEN FREEZE MCLKDIV DAC4_DIS DAC3_DIS DAC2_DIS DAC1_DIS PDN 00000001

6.1.5 Power Down (PDN)

disabled before normal operation in Control Port Mode can occur.

6.2 Mode Control 2 (address 02h)

6.2.1 Digital Interface Format (dif)

whether PCM or DSD Mode is selected. by the Digital Interface Format and the options are detailed in Figures 7-12. master clock-to-DSD-data-rate is defined by the Digital Interface Format pins.

110 R e s e r v e d -

111 R e s e r v e d -

Table 5. Digital Interface Formats - PCM Mode Table 6. Digital Interface Formats - DSD Mode

34 DS618PP2

6.2.2 Mode Control 3 (address 03h)

6.2.3 Soft Ramp and Zero Cross CONTROL (SZC)

Default = 10 00 - Immediate Change 01 - Zero Cross 10 - Soft Ramp 11 - Soft Ramp on Zero Crossings Function: Immediate Change When Immediate Change is selected, all level changes will take effect immediately in one step. Zero Cross Zero Cross Enable dictates that signal level changes, either by attenuation changes or muting, will occur on a signal zero crossing to minimize audible arti facts. The requested leve l change will occur after a timeout period between 512 and 1024 sample periods (1 0.7 ms to 21.3 ms at 48 kHz sample rate) if the signal does not encounter a zero crossing. The ze ro cross function is independently monitored and implemented for each channel. Soft Ramp Soft Ramp allows level changes, both muting and attenuation, to be implemented by incrementally ramp- ing, in 1/8 dB steps, from the current level to the new level at a rate of 1 dB per 8 left/right clock periods. Soft Ramp on Zero Crossing Soft Ramp and Zero Cross Enable di ctates that signal level changes, either by attenuation changes or muting, will occur in 1/8 dB steps and be implemented on a signal zero crossing. The 1/8 dB level change will occur after a timeout period betwee n 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample rate) if the signal does not encounter a zero crossing. The zero cross function is independently monitored and implemented for each channel.

6.2.4 Single Volume Control (Snglvol)

Default = 0 0 - Disabled 1 - Enabled Function: The individual channel volume levels are independen tly controlled by their re spective Volume Control Bytes when this function is disabled. The volume on all channels is determined by the A1 Channel Vol- ume Control Byte, and the other Volume Control Bytes are ignored when this function is enabled. 76543210 SZC1 SZC0 SNGLVOL RMP_UP MUTEC+/- AMUTE Reserved MUTEC 10000100

6.2.5 Soft Volume Ramp-U p after Error (RMP_UP)

Default = 0 0 - Disabled 1 - Enabled Function: An un-mute will be performed after a LRCK/MCLK ratio change or error, and after changing the Functional Mode. When this feature is enabled, this un-mute is affected, similar to attenuation changes, by the Soft and Zero Cross bits in the Mode Control 3 register. When disabled, an immediate un-mute is performed in these instances. Notes: For best results, it is recommended that this feature be used in conjunction with the RMP_DN bit.

6.2.6 MUTEC Polarity (MUTEC+/-)

Default = 0 0 - Active High 1 - Active Low Function: The active polarity of the MUTEC pin(s) is determine d by this register. When set to 0 (default), the MUTEC pins are high when active. When set to 1 the MUTEC pin(s) are low when active. Notes: When the onboard mute circuitry is designed for active lo w, the MUTEC outputs will be high (un-muted) for the period of time during reset and before this bit is enabled to 1.

6.2.7 Auto-Mute (AMUTE)

Default = 1 0 - Disabled 1 - Enabled Function: The Digital-to-Analog converter output will mute following the reception of 8192 consecutive audio sam- ples of static 0 or -1. A single sample of non-static data will rele ase the mute. Detection and muting is done independently for each channel. The quiescent voltage on the output will be retained, and the Mute Control pin will go active during the mute period. The muting function is affected, similar to volume control changes, by the Soft and Zero Cross bits in the Mode Control 3 register.

6.3 Mutec Pin Control (MUTEC)

Default = 0 0 - Two Mute control signals 1 - Single mute control signal on MUTEC1 Function: Selects how the internal mute signals are routed to the MUTEC1 and MUTEC234 pins. When set to ‘0’, a logical AND of DAC pair 1 mute control signals ar e output on MUTEC1 and a logical AND of the mute control signals of DAC pairs 2, 3, and 4 are output on MUTEC234. When set to ‘1’, a logical AND of all DAC pair mute control signals is output on the MUTEC1 pin, MUTEC234 will remain static. For more in- formation on the use of the mute control function see the MUTEC1 and MUTEC234 pins in Section 5.

36 DS618PP2

6.4 Filter Control (address 04h)

6.4.1 Interpolation Filt er Select (FILT_SEL)

Default = 0 0 - Fast roll-off 1 - Slow roll-off Function: This function allows the user to select whether the inte rpolation filter has a fast or slow roll off. For filter characteristics, please see Section 2.

6.4.2 De-Emphasis Control (DEM)

Default = 00 00 - Disabled 01 - 44.1 kHz 10 - 48 kHz 11 - 32 kHz Function: Selects the appropriate digital filter to maintain the standard 15 µs/50 µs digital de-emphasis filter re- sponse at 32, 44.1 or 48 kHz sample rates. (see Figure 13) De-emphasis is only available in Single-Speed Mode.

6.4.3 Soft Ramp-Down before Fi lter Mode Change (RMP_DN)

Default = 0 0 - Disabled 1 - Enabled Function: If either the FILT_SEL or DEM bi ts are changed, the DAC will stop co nversion for a period of time to change filter values. This bit selects how the data is effected prior to and after the change of the filter val- ues. When this bit is enabled, the DAC will ramp down the volume prior to a filter-mode change and ramp from mute to the original volume value after a filter-mode change according to the settings of the Soft and Zero Cross bits in the Mode Control 3 register. When disabled, an immediate mute and unmute is per- formed. Loss of clocks or a change in the FM bits will a lways cause an immediate mute; unmute in these condi- tions is affected by the RMP_UP bit. Notes: For best results, it is recommended that this feature be used in conjunction with the RMP_UP bit. 76543210 Reserved Reserved Reserved FILT_SEL Reserved DEM1 DEM0 RMP_DN 00000000

6.5 Invert Control (address 05h)

6.5.1 Invert Signal Polarity (Inv_Xx)

Default = 0 0 - Disabled 1 - Enabled Function: When enabled, these bits will invert the signal polarity of their respective channels.

6.6 Mixing Control Pair 1 (Cha nnels A1 & B1)(address 06h)

Mixing Control Pair 2 (Channels A2 & B2)(address 09h) Mixing Control Pair 3 (Channels A3 & B3)(address 0Ch) Mixing Control Pair 4 (Channels A4 & B4)(address 0Fh)

6.6.1 Channel A Volume = Channel B Volume (A=B)

Default = 0 0 - Disabled 1 - Enabled Function: The AOUTAx and AOUTBx volume levels are independently controlled by the A and the B Channel Vol- ume Control Bytes when this function is disabled. The volume on both AOUTAx and AOUTBx are deter- mined by the A Channel Attenuation and Volume Control Bytes (per A-B pair), and the B Channel Bytes are ignored when this function is enabled.

6.6.2 ATAPI Channel Mixi ng and Muting (ATAPI)

Default = 01001 - AOUTAx=aL, AOUTBx=bR (Stereo) Function: The CS4382A implements the channel mixing functions of the ATAPI CD-ROM specification. The ATAPI functions are applied per A-B pair. Refer to Table 7 and Figure 14 for additional information. 76543210 INV_B4 INV_A4 INV_B3 INV_A3 INV_B2 INV_A2 INV_B1 INV_A1 00000000 76543210 Px_A=B PxATAPI4 PxATAPI3 PxATAPI2 PxATAPI1 PxATAPI0 PxFM1 PxFM0 00100100

38 DS618PP2

6.6.3 Functional Mode (FM)

for any channel pair, all pairs switch to DSD Mode.

00000 M U T E M U T E

00001 M U T E b R

00010 M U T E b L

00011 M U T E b [ ( L + R ) / 2 ]

10000 M U T E M U T E

10001 M U T E b R

10010 M U T E b L

10011 M U T E [ ( a L + b R ) / 2 ]

Table 7. ATAPI Decode

6.7 Volume Control (addresses 07h , 08h, 0Ah, 0Bh, 0Dh, 0Eh)

Note: These eight registers provide individual volume and mute control for each of the eight channels.

6.7.1 Mute (MUTE)

bits. The MUTE pins will go active during the mute period according to the MUTEC bit.

6.7.2 Volume Control (xx_VOL)

Table 8. Example Digital Volume Settings

40 DS618PP2

6.8 Chip Revision (address 12h)

6.8.1 Part Number ID (part) [Read Only]

Function: This read-only register can be used to identify the model and revision number of the device. 76543210 PART4 PART3 PART2 PART1 PART0 Reserved Reserved Reserved 01110000

42 DS618PP2

Figure 25. Single-Speed (slow) Transition Band (detail) Figure 26. Single-S peed (slow) Passband Ripple Figure 27. Double-Speed (fast) Stopband Rejection Figure 28. Double-Speed (fast) Transition Band Figure 29. Double-Speed (fast) Transition Band (detail) Figure 30. Double-Speed (fast) Passband Ripple

44 DS618PP2

Figure 37. Quad-Speed (fast) Transition Band (detail) Figure 38. Quad-Speed (fast) Passband Ripple Figure 39. Quad-Speed (slow) Stopband Rejection Figure 40. Quad-Speed (slow) Transition Band Figure 41. Quad-Speed (slow) Transition Band (detail) Figure 42. Quad-Speed (slow) Passband Ripple

1. PARAMETER DEFINITIONS Total Harmonic Distortion + Noise (THD+N) The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels. Dynamic Range The ratio of the full-scale rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. Dynamic range is a signal-to-noise measurement over the specified bandwidth made with a -60 dBFS signal. 60 dB is then added to the resulting measurement to refer the measure- ment to full scale. This technique ensures that the distortion components are below the noise level and do not affect the measurement. This measurement technique has been accepted by the Audio Engineer- ing Society, AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307. Interchannel Isolation A measure of crosstalk between the left and right channels. Measured for each channel at the converter's output with all zeros to the input under test and a full-scale signal applied to the other channel. Units in decibels. Interchannel Gain Mismatch The gain difference between left and right channels. Units in decibels. Gain Error The deviation from the nominal full-scale analog output for a full-scale digital input. Gain Drift The change in gain value with temperature. Units in ppm/°C.

46 DS618PP2

1. PACKAGE DIMENSIONS INCHES MILLIMETERS DIM MIN NOM MAX MIN NOM MAX * Nominal pin pitch is 0.50 mmControlling dimension is mm. JEDEC Designation: MS022 48L LQFP PACKAGE DRAWING E D1D e L B A

10.ORDERING INFORMATION 11.REFERENCES 1. How to Achieve Optimum Performance fr om Delta-Sigma A/D & D/A Converters , by Steven Harris. Paper presented at the 93rd Convention of the Audio Engineering Society, October 1992. 2. CDB4382A Datasheet 3. Design Notes for a 2-Pole Filter with Differential Input, by Steven Green. Cirrus Logic Application Note AN48 4. The I²C-Bus Specification: Version 2.0, Philips Semiconductors, December 1998. http://www.semiconductors.philips.com 12.REVISION HISTORY Release Changes PP1 Updated output impedance spec on page 10 Improved interchannel isolation spec on page 10 Updated legal text Reformatted ordering information PP2 Corrected package type Product Description Package Pb-Free Grade Temp Range Container Order # CS4382A 114 dB, 192 kHz 8- channel D/A Converter 48-pin LQFP YES Commercial -10° to +70° C Tray CS4382A-CQZ Tape & Reel CS4382A-CQZR Automotive -40° to +85° C Tray CS4382A-DQZ Tape & Reel CS4382A-DQZR CDB4382A CS4382A Evaluation Board - - - - CDB4382A Contacting Cirrus Logic Support For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find the one nearest to you, go to www.cirrus.com/corporate/contacts/sales.cfm IMPORTANT NOTICE "Preliminary" product information describes products that are in production, but for which full characterization data is not yet available. Cirrus Logic, Inc. and its sub- sidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order ac- knowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROP- ERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DE- VICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER’S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICA- TIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS’ FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. I²C is a registered trademark of Philips Semiconductor. SPI is a trademark of Motorola, Inc.