CS4360 CIRRUS | Alldatasheet
Document overview
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Technical content
Features
l+3 V to +5 V Power Supply lDigital Volume Control with Soft Ramp – 119 dB Attenuation – 1 dB Step Size – Zero Crossing Click-Free Transitions lLow Power Consumption – 105 mW with 3 V supply lATAPI Mixing lLow Clock Jitter Sensitivity lPopguard Technology® for Control of Clicks and Pops
Description
The CS4360 is a complete 6-channel digital-to-analog system including digital interpolation, fourth-order delta- sigma digital-to-analog conversion, digital de-emphasis, volume control, channel mixing and analog filtering. The advantages of this architecture include: ideal differential linearity, no distortion mechanisms due to resistor matching errors, no linearity drift over time and tempera- ture and a high tolerance to clock jitter. The CS4360 accepts data at audio sample rates from 4 kHz to 200 kHz, consumes very little power and oper- ates over a wide power supply range. These features are ideal for cost-sensitive, multi-channel audio systems in- cluding DVD players, A/V receivers, set-top boxes, digital TVs and VCRs, mini-component systems, and mixing consoles.
ORDERING INFORMATION
CS4360-KS -10 to 70 °C 28-pin SOIC CS4360-BS -40 to 85 °C 28-pin SOIC CS4360-KZ -10 to 70 °C 28-pin TSSOP CS4360-BZ -40 to 85 °C 28-pin TSSOP CDB4360 Evaluation Board I Control Port External Mute Control RST Volume ControlInterpolation Filter Analog Filter AOUT A1ΔΣ DAC Mixer Volume Control ΔΣ DAC Analog Filter AOUTB1Interpolation Filter Volume ControlInterpolation Filter Analog Filter AOUT A2ΔΣ DAC Mixer Volume Control ΔΣ DAC Analog Filter AOUTB2Interpolation Filter Volume ControlInterpolation Filter Analog Filter AOUT A3ΔΣ DAC Mixer Volume Control ΔΣ DAC Analog Filter AOUT B3Interpolation Filter MCLK Serial Port LRCK SCLK SD I N1 SD I N2 SD I N3 DIF1/SCL/CCLK DIF0/SDA/CDIN M1/AD0/CS VLC ÷2 VQ FILT+ VAGNDVD VLS MUTEC1 MUTEC2 MUTEC3M2 GND FEB ‘01 DS517PP1
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4.3 Mixing Control Pair 1 (Channels A1 & B1) (address 03h)
Mixing Control Pair 2 (Channels A2 & B2) (address 04h) Contacting Cirrus Logic Support For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at: http://www.cirrus.com/corporate/contacts/sales.cfm Preliminary product information describes products which are in production, but for which full characterization data is not yet available. Advance product infor- mation describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, including use of this information as the basis for manufacture or sale of any items, nor for infringements of patents or other rights of third parties. This document is the property of Cirrus Logic, Inc. and by furnishing this information, Cirrus Logic, Inc. grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights of Cirrus Logic, Inc. Cirrus Logic, Inc., copyright owner of the information contained herein, gives consent for copies to be made of the information only for use within your organization with respect to Cirrus Logic integrated circuits or other parts of Cirrus Logic, Inc. The same consent is given for similar information contained on any Cirrus Logic website or disk. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some
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- CHARACTERISTICS AND SPECIFICATIONS ANALOG CHARACTERISTICS (Full-Scale Output Sine Wave, 997 Hz; for Single-Speed Mode, Fs = 48 kHz, SCLK = 3.072 MHz, MCLK = 12.288 MHz; for Double-Speed Mode Fs = 96 kHz, SCLK = 6.144 MHz, MCLK = 12.288 MHz; for Quad-Speed Mode Fs = 192 kHz, SCLK = 12.288 MHz, MCLK = 24.576 MHz; Measure- ment Bandwidth 10 Hz to 20 kHz, unless otherwise specified. Test load R L = 10 kΩ, C L = 10 pF (see Figure 15). VA = VD = VLS = VLC), Notes: 1. CS4360-KS/-KZ parts are tested at 25 °C. 2. One-half LSB of triangular PDF dither is added to data. 3. CS4360-BS/-BZ parts are tested at the extremes of the specified temperature range and Min/Max performance numbers are guaranteed across the specified temperature range, TA. Typical numbers are taken at 25 °C. ANALOG CHARACTERISTICS (Continued) Parameter VA = 5 V VA = 3 V Symbol Min Typ Max Min Typ Max Unit CS4360-KS/-KZ Dynamic Performance (Note 1) Specified Temperature Range T A -10 - 70 -10 - 70 °C Dynamic Range (Note 2) unweighted A-Weighted 40 kHz Bandwidth A-Weighted TBD TBD 102 100 TBD TBD dB dB dB Total Harmonic Distortion + Noise (Note 2) 0 dB -20 dB -60 dB THD+N - -91 -79 -39 TBD -91 -74 -34 TBD dB dB dB Interchannel Isolation (1 kHz) - 102 - - 102 - dB CS4360-BS/-BZ Dynamic Performance (Note 3) Specified Temperature Range T A -40 - 85 -40 - 85 °C Dynamic Range (Note 2) unweighted A-Weighted 40 kHz Bandwidth A-Weighted TBD TBD 102 100 TBD TBD dB dB dB Total Harmonic Distortion + Noise (Note 2) 0 dB -20 dB -60 dB THD+N - -91 -79 -39 TBD -91 -74 -34 TBD dB dB dB Interchannel Isolation (1 kHz) - 102 - - 102 - dB Parameter Symbol Min Typ Max Unit Combined Digital and On-chip Analog Filter Response - Single-Speed Mode (Note 4) Passband (Note 5) to -0.05 dB corner to -3 dB corner .4535 .4998 Fs Fs Frequency Response 10 Hz to 20 kHz -.02 - +.035 dB StopBand .5465 - - Fs
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Notes: 4. Filter response is guaranteed by design. 5. Response is clock dependent and will scale with Fs. Note that the response plots (Figures 9 - 12) have been normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs. 6. For Single-Speed Mode, the Measurement Bandwidth is .5465 Fs to 3 Fs. For Double-Speed Mode, the Measurement Bandwidth is .577 Fs to 1.4 Fs. 7. De-emphasis is available only in Single-Speed Mode. 8. Refer to Figure 16. StopBand Attenuation (Note 6) 50 - - dB Group Delay tgd - 9/Fs - s Passband Group Delay Deviation 0 - 20 kHz - ±0.36/Fs - s De-emphasis Error (Relative to 1 kHz) Fs = 32 kHz Control Port Mode Fs = 44.1 kHz (Note 7) Fs = 48 kHz Fs = 32 kHz Stand-Alone Mode Fs = 44.1 kHz Fs = 48 kHz +.2/-.1 +.05/-.14 +0/-.22 +1.5/-0 +.05/-.14 +.2/-.4 dB dB dB dB dB dB Combined Digital and On-chip Analog Filter Response - Double-Speed Mode (Note 4) Passband (Note 5) to -0.1 dB corner to -3 dB corner .4621 .4982 Fs Fs Frequency Response 10 Hz to 20 kHz -0.1 - 0 dB StopBand .577 - - Fs StopBand Attenuation (Note 6) 55 - - dB Group Delay tgd - 4/Fs - s Passband Group Delay Deviation 0 - 20 kHz - ±0.23/Fs - s Combined Digital and On-chip Analog Filter Response - Quad-Speed Mode (Note 4) Passband (Note 5) to -3 dB corner 0 - .25 Fs Frequency Response 10 Hz to 20 kHz -0.7 - 0 dB Group Delay tgd - 1.5/Fs - s Parameters Symbol Min Typ Max Units Analog Output Full Scale Output Voltage 0.60•V A 0.66•VA 0.72•VA Vpp Quiescent Voltage V Q - 0.5•V A -V D C Quiescent Pin External Load I Q -- T B D V D C Interchannel Gain Mismatch - 0.1 - dB Gain Drift - 100 - ppm/°C AC-Load Resistance (Note 8) R L 3--k Ω Load Capacitance C L -- 1 0 0 p F Output Impedance Z OUT - 100 - Ω Parameter Symbol Min Typ Max Unit
POWER AND THERMAL CHARACTERISTICS Notes: 9. Current consumption is directly proportional to Fs. Typ and Max values are based on highest FS 10. ILC measured with no external loading on pin 12 (SDA). 11. Power down mode is defined as RST = Low with all clock and data lines held static. 12. Valid with the recommended capacitor values on FILT+ and VCM as shown in Figure 4. DIGITAL CHARACTERISTICS (For -KS & -KZ parts TA = -10 to +70°C; for -BS & -BZ parts TA = -40 to +85°C; VD = 2.0 V - 5.5 V, VLC = VLS = 1.8 V - 5.5 V) Parameters Symbol Min Typ Max Units Power Supplies Power Supply Current normal operation, All Supplies = 5 V (Note 9) All Supplies = 3 V Interface current (Note 10) power-down state (all supplies) (Note 11) IA ID IA ID ILS ILC Ipd 0.002 0.002 0.016 mA mA mA mA mA mA mA Power Dissipation (Note 9) All Supplies = 5 V normal operation power-down (Note 11) All Supplies = 3 V normal operation power-down (Note 11) 235 0.080 105 0.048 TBD TBD mW mW mW mW Package Thermal Resistance SOIC (-KS & -BS) TSSOP (-KZ & -BZ) θ JA θJC θJA θJC TBD TBD TBD TBD °C/Watt °C/Watt °C/Watt °C/Watt Power Supply Rejection Ratio (1 kHz) (Note 12) (60 Hz) PSRR PSRR dB dB Parameters Symbol Min Typ Max Units High-Level Input Voltage Serial Audio Data Port Control Port V IH VIH 70% 70% VLS VLC Low-Level Input Voltage Serial Audio Data Port Control Port VIL - 20% 20% VLS VLC Input Leakage Current I in -- ± 1 0 µA Input Capacitance - 8 - pF Maximum MUTEC Drive Current - 3 - mA MUTEC High-Level Output Voltage V OH VA V MUTEC Low-Level Output Voltage V OL 0V
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ABSOLUTE MAXIMUM RATINGS (GND = 0V; all voltages with respect to ground.) WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. RECOMMENDED OPERATING CONDITIONS (GND = 0V; all voltages with respect to ground.) 13. Applies to pins 2, 3, 4, 5, 6, and 7. 14. Applies to pins 10, 11, 12, and 13. Parameters Symbol Min Max Units DC Power Supply Analog power Digital power Serial Audio Data Interface power Control Port Interface power VA VD VLS VLC -0.3 -0.3 -0.3 -0.3 6.0 6.0 6.0 6.0 V V V V Input Current, Any Pin Except Supplies I in - ±10 mA Digital Input Voltage Serial audio data interface Control port interface VIND_S VIND_C -0.3 -0.3 VLS + 0.4 VLC + 0.4 V V Ambient Operating Temperature (power applied) T A -55 125 °C Storage Temperature T stg -65 150 °C Parameters Symbol Min Typ Max Units DC Power Supply Analog Power Digital Power Serial Audio Data Interface Power (Note 13) Control Port Interface Power (Note 14) VA VD VLS VLC 2.7 2.0 1.8 1.8 5.5 VA 5.5 5.5 V V V V
Notes: 15. This serial clock is available only in Control Port Mode when the MCLK Divide bit is enabled. Figure 1. Serial Mode Input Timing
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Notes: 16. The Two-Wire Format is compatible with the I2C protocol.
- Data must be held for sufficient time to bridge the transition time, tfc, of SCL.
- The acknowledge delay is based on MCLK and can limit the maximum transaction speed.
- for Single-Speed Mode, for Double-Speed Mode, for Quad-Speed Mode.
Figure 2. Control Port Timing - Two-Wire Format
Notes: 20. tspi only needed before first falling edge of CS after RST rising edge. tspi = 0 at all other times.
- Data must be held for sufficient time to bridge the transition time of CCLK.
Figure 3. Control Port Timing - SPI Format
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- TYPICAL CONNECTION DIAGRAM
6 LRCK1
26 AOUTB1
23 AOUTB2
19 AOUTB3
Figure 4. Typical Connection Diagram
- REGISTER QUICK REFERENCE Addr Function 7 6 5 4 3 2 1 0 1h Mode Control 1 AMUTE DIF2 DIF1 DIF0 DEM1 DEM0 FM1 FM0 default 10000000 2h Invert Signal Reserved Reserved INV_B3 INV_A3 INV_B2 INV_A2 INV_B1 INV_A1 default 00000000 3h Mixing Control P1 Reserved Reserved Reserved Reserved P1ATAPI3 P1ATAPI2 P1ATAPI1 P1ATAPI0 default 00001001 4h Mixing Control P2 Reserved Reserved Reserved Reserved P2ATAPI3 P2ATAPI2 P2ATAPI1 P2ATAPI0 default 00001001 5h Mixing Control P3 Reserved Reserved Reserved Reserved P3ATAPI3 P3ATAPI2 P3ATAPI1 P3ATAPI0 default 00001001 6h Volume Control A1 A1_MUTE A1_VOL6 A1_VOL5 A1_VOL4 A1_VOL3 A1_VOL2 A1_VOL1 A1_VOL0 default 00000000 7h Volume Control B1 B1_MUTE B1_VOL6 B1_VOL5 B1_VOL4 B1_VOL3 B1_VOL2 B1_VOL1 B1_VOL0 default 00000000 8h Volume Control A2 A2_MUTE A2_VOL6 A2_VOL5 A2_VOL4 A2_VOL3 A2_VOL2 A2_VOL1 A2_VOL0 default 00000000 9h Volume Control B2 B2_MUTE B2_VOL6 B2_VOL5 B2_VOL4 B2_VOL3 B2_VOL2 B2_VOL1 B2_VOL0 default 00000000 0Ah Volume Control A3 A3_MUTE A3_VOL6 A3_VOL5 A3_VOL4 A3_VOL3 A3_VOL2 A3_VOL1 A3_VOL0 default 00000000 0Bh Volume Control B3 B3_MUTE B3_VOL6 B3_VOL5 B3_VOL4 B3_VOL3 B3_VOL2 B3_VOL1 B3_VOL0 default 00000000 0Ch Mode Control 2 SZC1 SZC0 CPEN PDN POPG FREEZE MCLKDIV SNGLVOL default 10 0 11000 0Dh Revision Indicator Reserved Reserved Reserved Reserved REV3 REV2 REV1 REV0 default 0000XXXX
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Note: All registers are read/write in Two-Wire mode and write only in SPI, unless otherwise noted.
4.1 Mode Control 1 (address 01h)
4.1.1 AUTO-MUTE (AMUTE)
to volume control changes, by the Soft and Zero Cross bits in the Power and Muting Control register.
4.1.2 DIGITAL INTERFACE FORMAT (DIF)
Digital Interface Format and the options are detailed in Figures 17-22.
000 Left Justified, up to 24-bit data, 01 7
001 I2S, up to 24-bit data 11 8
010 Right Justified, 16-bit data 21 9
011 Right Justified, 24-bit data 32 0
100 Right Justified, 20-bit data 42 1
101 Right Justified, 18-bit data 52 2
110 Reserved
111 Reserved
Table 1. Digital Interface Formats - Control Port Mode
4.1.3 DE-EMPHASIS CONTROL (DEM)
Default = 00 00 - Disabled 01 - 44.1 kHz 10 - 48 kHz 11 - 32 kHz Function: Selects the appropriate digital filter to maintain the standard 15µs/50µs digital de-emphasis filter re- sponse at 32, 44.1 or 48 kHz sample rates. (see Figure 23) Note: De-emphasis is only available in Single-Speed Mode.
4.1.4 FUNCTIONAL MODE (FM)
Default = 00 00 - Single-Speed Mode (2 to 50 kHz sample rates) 01 - Double-Speed Mode (50 to 100 kHz sample rates) 10 - Quad-Speed Mode (100 to 200 kHz sample rates) 11 - Reserved Function: Selects the required range of input sample rates.
4.2 Invert Signal (address 02h)
4.2.1 INVERT SIGNAL POLARITY (INV_XX)
Default = 0 0 - Disabled 1 - Enabled Function: When enabled, these bits invert the signal polarity for each of their respective channels. Mixing Control Pair 2 (Channels A2 & B2) (address 04h) Mixing Control Pair 3 (Channels A3 & B3) (address 05h) 76543210 Reserved Reserved INV_B3 INV_A3 INV_B2 INV_A2 INV_B1 INV_A1 00000000 76543210 Reserved Reserved Reserved Reserved PxATAPI3 PxATAPI2 PxATAPI1 PxATAPI0 00001001
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4.3.1 ATAPI CHANNEL MIXING AND MUTING (ATAPI)
Table 2 and Figure 24 for additional information. Note: All mixing functions occur prior to the digital volume control. Mixing only occurs in channel pairs.
4.4 Volume Control (addresses 06h - 0Bh)
4.4.1 MUTE (MUTE)
0000 M U T E M U T E
0001 M U T E R
0010 M U T E L
0011 M U T E [ ( L + R ) / 2 ]
0100 R M U T E
0101 R R
0110 R L
0111 R [ ( L + R ) / 2 ]
1000 L M U T E
1001 L R
1010 L L
1011 L [ ( L + R ) / 2 ]
Table 2. ATAPI Decode
4.4.2 VOLUME CONTROL (XX_VOL)
are equivalent to enabling the MUTE bit.
4.5 Mode Control 2 (address 0Dh)
4.5.1 SOFT RAMP AND ZERO CROSS CONTROL (SZC)
When Immediate Change is selected all level changes will be implemented immediately in one step. itored and implemented for each channel. tion is independently monitored and implemented for each channel. Table 3. Example Digital Volume Settings
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4.5.2 CONTROL PORT ENABLE (CPEN)
Default = 0 0 - Disabled 1 - Enabled Function: The Control Port will become active and reset to the default settings when this function is enabled.
4.5.3 POWER DOWN (PDN)
Default = 1 0 - Disabled 1 - Enabled Function: The entire device will enter a low-power state when this function is enabled, and the contents of the control registers are retained in this mode. The power-down bit defaults to ‘enabled’ on power-up and must be disabled before normal operation in Control Port mode can occur.
4.5.4 POPGUARD® TRANSIENT CONTROL (POPG)
Default = 1 0 - Disabled 1 - Enabled Function: The PopGuard® Transient Control allows the quiescent voltage to slowly ramp to and from 0 volts to the quiescent voltage during power-on or power-off when this function is enabled. Please see section 6.4 for implementation details.
4.5.5 FREEZE CONTROLS (FREEZE)
Default = 0 0 - Disabled 1 - Enabled Function: This function allows modifications to be made to the registers without the changes taking effect until the FREEZE is disabled. To make multiple changes in the control port registers take effect simulta- neously, enable the FREEZE bit, make all register changes, then disable the FREEZE bit.
4.5.6 MASTER CLOCK DIVIDE ENABLE (MCLKDIV)
Default = 0 0 - Disabled 1 - Enabled Function: The MCLKDIV bit enables a circuit which divides the externally applied MCLK signal by 2 prior to all other internal circuitry.
4.5.7 SINGLE VOLUME CONTROL (SNGLVOL)
Default = 0 0 - Disabled 1 - Enabled Function: The individual channel volume levels are independently controlled by their respective Volume Control Bytes when this function is disabled. The volume on all channels is determined by the A1 Channel Volume Control Byte, and the other Volume Control Bytes are ignored when this function is enabled.
4.6 Revision Register (Read Only) (address 0Dh)
4.6.1 REVISION INDICATOR (REV) [READ ONLY]
Default = none etc. Function: This read-only register indicates the revision level of the device. 76543210 Reserved Reserved Reserved Reserved REV3 REV2 REV1 REV0 0000XXXX
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- PIN DESCRIPTION Pin Name # Pin Description VLS 1 Serial Audio Interface Power (Input) - Determines the required signal level for the serial audio inter- face. Refer to the Recommended Operating Conditions for appropriate voltages. Applies to pins 2-7. SDIN1 SDIN2 SDIN3 Serial Audio Data Input (Input) - Input for two’s complement serial audio data. SDIN1 corresponds to AOUT1x, SDIN2 corresponds to AOUT2x and SDIN3 corresponds to AOUT3x. SCLK 5 Serial Clock (Input) - Serial clock for the serial audio interface. LRCK 6 Left / Right Clock (Input) - Determines which channel, Left or Right, is currently active on the serial audio data line. The frequency of the left/right clock must be at the audio sample rate, Fs. MCLK 7 Master Clock (Input) - Clock source for the delta-sigma modulator and digital filters. Table 6 illustrates several standard audio sample rates and the required master clock frequency. VD 8 Digital Power (Input) - Positive power supply for the digital section. Refer to the Recommended Operat- ing Conditions for appropriate voltages. GND 9 Ground (Input) - Ground reference. Should be connected to analog ground. RST 10 Reset (Input) - The device enters a low power mode and all internal registers are reset to their default settings when low. The control port cannot be accessed when Reset is low. VLC 14 Control Port Interface Power (Input) - Determines the required signal level for the control port and pro- vides power for bidirectional control port pins. Refer to the Recommended Operating Conditions for appropriate voltages. Applies to pins 10-13 and 15. FILT+ 16 Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling circuits. Requires the capacitive decoupling to GND as shown in the Typical Connection Diagram. Serial Audio Power VLS MUTEC1 Mute Control 1 Serial Data Input 1 SDIN1 AOUTA1 Analog Output A1 Serial Data Input 2 SDIN2 AOUTB1 Analog Output B1 Serial Data Input 3 SDIN3 MUTEC2 Mute Control 2 Serial Clock SCLK AOUTA2 Analog Output A2 Left/Right Clock LRCK AOUTB2 Analog Output B2 Master Clock MCLK VA Analog Power Digital Power VD GND Ground Ground GND AOUTA3 Analog Output A3 Reset RST AOUTB3 Analog Output B3 DIF1 / SCL/ CCLKDIF1/SCL/CCLK MUTEC3 Mute Control 3 DIF0 / SDA / CDINDIF0/SDA/CDIN VQ Quiescent Voltage Mode1 / AD0 / CS M1/AD0/CS FILT+ Positive Voltage Reference Control Port Power VLC M2 Mode 2 1514
the maximum specified in the Analog Characteristics and Specifications section. ating Conditions for appropriate voltages. requiring the absolute minimum in extraneous clicks and pops. resistor to the logic interface voltage in Two-Wire mode as shown in the Typical Connection Diagram. input data line for the control port interface in SPI format.
13 Address Bit 0 (Two-Wire) / Control Port Chip Select (SPI) (Input/Output) - AD0 is a chip address pin
Two-Wire format; CS is the chip select signal for SPI format. and serial data is defined by the Digital Interface Format selection. Refer to Table 4. Mode Selection (Input) - Determines the operational mode of the device as detailed in Table 5.
01 I2S, up to 24-bit data
Table 4. Digital Interface Formats - Stand Alone Mode Table 5. Mode Selection
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Table 6. Single-Speed Mode Common Clock Frequencies Table 7. Double-Speed Mode Common Clock Frequencies Table 8. Quad-Speed Mode Common Clock Frequencies
- APPLICATIONS
6.1 Grounding and Power Supply
As with any high resolution converter, the CS4360 requires careful attention to power supply and grounding arrangements to optimize performance. Figure 4 shows the recommended power arrange- ment with VA, VD, VLS and VLC connected to clean supplies. Decoupling capacitors should be lo- cated as close to the device package as possible. If desired, all supply pins may be connected to the same supply, but a decoupling capacitor should still be placed on each supply pin.
6.2 Oversampling Modes
The CS4360 operates in one of three oversampling modes based on the input sample rate. Mode selec- tion is determined by the FM pins in Stand-Alone mode or the FM bits in Control Port mode. Single- Speed mode supports input sample rates up to 50 kHz and uses a 128x oversampling ratio. Double- Speed mode supports input sample rates up to 100 kHz and uses an oversampling ratio of 64x. Quad- Speed mode supports input sample rates up to 200 kHz and uses an oversampling ratio of 32x.
6.3 Recommended Power-up Sequence
- Hold RST low until the power supply, master, and left/right clocks are stable. In this state, the control port is reset to its default settings and VQ will remain low. 2. Bring RST high. The device will remain in a low power state with VQ low and will initiate the Stand-Alone power-up sequence. The control port will be accessible at this time. If Control Port oper- ation is desired, write the CPEN bit prior to the completion of the Stand-Alone power-up se- quence, approximately 512 LRCK cycles in Sin- gle-Speed Mode (1024 LRCK cycles in Double- Speed Mode, and 2048 LRCK cycles in Quad- Speed Mode). Writing this bit will halt the Stand- Alone power-up sequence and initialize the control port to its default settings. The desired register set- tings can be loaded while keeping the PDN bit set to 1. 3. If Control Port Mode is selected via the CPEN bit, set the PDN bit to 0 which will initiate the pow- er-up sequence, which requires approximately 50 µS when the POPG bit is set to 0. If the POPG bit is set to 1, see Section 6.4 for total power-up timing.
6.4 Popguard ® Transient Control
The CS4360 uses a novel technique to minimize the effects of output transients during power-up and power-down. This technique, when used with external DC-blocking capacitors in series with the audio outputs, minimizes the audio transients com- monly produced by single-ended single-supply converters. When the device is initially powered-up, the audio outputs, AOUTAx and AOUTBx, are clamped to GND. Following a delay of approximately 1000 sample periods, each output begins to ramp toward the quiescent voltage. Approximately 10,000 left/right clock cycles later, the outputs reach VQ and audio output begins. This gradual voltage ramping allows time for the external DC-blocking capacitor to charge to the quiescent voltage, mini- mizing the power-up transient. To prevent transients at power-down, the device must first enter its power-down state. When this oc- curs, audio output ceases and the internal output buffers are disconnected from AOUTAx and AOUTBx. In their place, a soft-start current sink is substituted which allows the DC-blocking capaci- tors to slowly discharge. Once this charge is dissi- pated, the power to the device may be turned off and the system is ready for the next power-on. To prevent an audio transient at the next power-on, it is necessary to ensure that the DC-blocking ca- pacitors have fully discharged before turning off
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the power or exiting the power-down state. If not, a transient will occur when the audio outputs are ini- tially clamped to GND. The time that the device must remain in the power-down state is related to the value of the DC-blocking capacitance. For ex- ample, with a 3.3µF capacitor, the minimum pow- er-down time will be approximately 0.4 seconds. Use of the Mute Control function is recommended for designs requiring the absolute minimum in ex- traneous clicks and pops. Also, use of the Mute Control function can enable the system designer to achieve idle channel noise/signal-to-noise ratios which are only limited by the external mute circuit. See the CDB4360 data sheet for a suggested mute circuit. 7. CONTROL PORT INTERFACE The control port is used to load all the internal set- tings. The operation of the control port may be completely asynchronous with the audio sample rate. However, to avoid potential interference prob- lems, the control port pins should remain static if no operation is required. The CS4360 has MAP auto increment capability, enabled by the INCR bit in the MAP register, which is the MSB. If INCR is 0, then the MAP will stay constant for successive writes. If INCR is set to 1, then MAP will auto increment after each byte is written, allowing block reads or writes of succes- sive registers.
7.1 Enabling the Control Port
On the CS4360 the control port pins are shared with stand-alone configuration pins. To enable the control port, the user must set the CPEN bit. This is done by performing a Two-Wire or SPI write. Once the control port is enabled, these pins are ded- icated to control port functionality. To prevent audible artifacts the CPEN bit (see Sec- tion 4.5.2) should be set prior to the completion of the Stand-Alone power-up sequence, approximate- ly 512 LRCK cycles in Single-Speed Mode (1024 LRCK cycles in Double-Speed Mode, and 2048 LRCK cycles in Quad-Speed Mode). Writing this bit will halt the Stand-Alone power-up sequence and initialize the control port to its default settings. Note, the CPEN bit can be set any time after RST goes high; however, setting this bit after the Stand- Alone power-up sequence has completed can cause audible artifacts.
7.2 Format Selection
The control port has 2 formats: SPI and Two-Wire, with the CS4360 operating as a slave device. If Two-Wire operation is desired, AD0/CS should be tied to VLS or GND. If the CS4360 ever detects a high to low transition on AD0/CS after power-up and after the control port is activated, SPI format will be selected.
7.3 Two-Wire Format
In Two-Wire Format, SDA is a bidirectional data line. Data is clocked into and out of the part by the clock, SCL, with a clock to data relationship as shown in Figure 5. The receiving device should send an acknowledge (ACK) after each byte re- ceived. There is no CS pin. Pin AD0 form the par- tial chip address and should be tied to VLS or GND as required. The upper 6 bits of the 7 bit address field must be 001000. Note, MCLK is required during all two-wire trans- actions. The Two-Wire format is compatible with the I 2C protocol. Please see reference 2 for further details.
7.3.1 Writing in Two-Wire Format
To communicate with the CS4360, initiate a START condition of the bus. Next, send the chip address. The eighth bit of the address byte is the R/W bit (low for a write). The next byte is the Memory Address Pointer, MAP, which selects the register to be read or written. The MAP is then fol- lowed by the data to be written. To write multiple registers, continue providing a clock and data,
7.3.2 Reading in Two-Wire Format
7.4 SPI Format
7.4.1 Writing in SPI
001000 ADDR
Note: If operation is a write, this byte contains the Memory Address Pointer, MAP. Figure 5. Control Port Timing, Two-Wire Format Figure 6. Control Port Timing, SPI Format
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7.5 Memory Address Pointer (MAP)
7.5.1 INCR (AUTO MAP INCREMENT ENABLE)
Default = ‘0’ 0 - Disabled 1 - Enabled
7.5.2 MAP (MEMORY ADDRESS POINTER)
Default = ‘0000’ 76543210 INCR Reserved Reserved Reserved MAP3 MAP2 MAP1 MAP0 00000000
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Figure 13. High-Rate Transition Band (Detail) Figure 14. High-Rate Passband Ripple Figure 15. Output Test Load Figure 16. Maximum Loading
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Figure 21. CS4360 Format 4 - Right Justified 20-bit Data Figure 22. CS4360 Format 5 - Right Justified 18-bit Data Figure 23. De-Emphasis Curve
Figure 24. ATAPI Block Diagram
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- PARAMETER DEFINITIONS Total Harmonic Distortion + Noise (THD+N) The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth (typically 10Hz to 20kHz), including distortion components. Expressed in decibels. Dynamic Range The ratio of the full scale rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. Dynamic range is a signal-to-noise measurement over the specified bandwidth made with a -60 dBFS signal. 60 dB is then added to the resulting measurement to refer the measurement to full scale. This technique ensures that the distortion components are below the noise level and do not affect the measurement. This measurement technique has been accepted by the Audio Engineering So- ciety, AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307. Interchannel Isolation A measure of crosstalk between the left and right channels. Measured for each channel at the converter's output with all zeros to the input under test and a full-scale signal applied to the other channel. Units in decibels. Interchannel Gain Mismatch The gain difference between left and right channels. Units in decibels. Gain Error The deviation from the nominal full scale analog output for a full scale digital input. Gain Drift The change in gain value with temperature. Units in ppm/°C. 9. REFERENCES 1) “How to Achieve Optimum Performance from Delta-Sigma A/D & D/A Converters” by Steven Harris. Paper presented at the 93rd Convention of the Audio Engineering Society, October 1992. 2) CDB4360 Evaluation Board Datasheet 3) “The I2C Bus Specification: Version 2.0” Philips Semiconductors, December 1998. http://www.semiconductors.philips.com
- PACKAGE DIMENSIONS INCHES MILLIMETERS DIM MIN NOM MAX MIN NOM MAX JEDEC #: MS-013 Controlling Dimension is Millimeters 28L SOIC (300 MIL BODY) PACKAGE DRAWING D HE b A c L SEATING PLANE e
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Notes: 1. “D” and “E1” are reference datums and do not included mold flash or protrusions, but do include mold mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per side. 2. Dimension “b” does not include dambar protrusion/intrusion. Allowable dambar protrusion shall be 0.13 mm total in excess of “b” dimension at maximum material condition. Dambar intrusion shall not reduce dimension “b” by more than 0.07 mm at least material condition. 3. These dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips. INCHES MILLIMETERS NOTE DIM MIN NOM MAX MIN NOM MAX JEDEC #: MO-153 Controlling Dimension is Millimeters. 28L TSSOP (4.4 mm BODY) PACKAGE DRAWING E N 1 23 e b2 A1 A2 A D SEATING PLANE E11 L SIDE VIEW END VIEW TOP VIEW
- Notes •