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Features
Advanced Multi-bit Delta-Sigma Modulator 101 dB A-wt Dynamic Range -86 dB THD+N Single-ended Ground Centered Analog Architecture – No DC-blocking Capacitors Required – Integrated Inverting Charge Pump – Filtered Line-level Outputs –2 V RMS Full-scale Output Low-latency Digital Filtering Supports Sample Rates up to 192 kHz 24-bit I²S Input +5 V Analog Supply with Integrated Inverting Charge Pump and Regulator for Core Logic, and +1.8 V to +5 V Interface Power Supplies 50 mW Power Consumption 14-pin SOIC, Lead-free Assembly
Description
The CS4354 is a complete stereo digital-to-analog sys- tem including digital interpol ation, third-order multi-bit delta-sigma digital-to-analog conversion, digital de-em- phasis, analog filtering, and on-chip 2 V RMS line-level driver from a 5 V supply. The advantages of this architecture include ideal differ- ential linearity, no distortion mechanisms due to resistor matching errors, no linearity drift over time and temper- ature, high tolerance to clock jitter, and a minimal set of external components. The CS4354 is available in a 14-pin SOIC package in Commercial (-40°C to +85°C) grade. The CDB4354 Customer Demonstration Board is also available for de- vice evaluation and implementation suggestions. Please see “Ordering Information” on page 23 for com- plete details. These features are ideal fo r cost-sensitive, 2-channel audio systems including video game consoles, Blu-Ray Disc ® and DVD players, set-top boxes, digital TVs, and DAB/DMB devices. PCM Serial Audio Port Level Shifter I²S Serial Audio Input Multibit Modulator Interpolation Filters + HPF Left Channel Right Channel Power-On Reset Auto Speed Mode Detect Analog Supply (VA) +5 V Inverting Charge Pump 1.8V reg -VA Interface Supply(VL) +1.8V to +5V Ground-Centered,
2 Vrms Line Level
JULY '10 DS895A2 CS4354
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- PIN DESCRIPTIONS Pin Name Pin # Pin Description VL 1 Serial Audio Interface Power (Input) - Positive power for the serial audio interface. SDIN 2 Serial Audio Data Input (Input) - Input for two’s complement serial audio data. MCLK 3 Master Clock (Input) - Clock source for the delta-sigma modulator and digital filters. LRCK 4 Left / Right Clock (Input) - Determines which channel, Left or Right, is currently active on the serial audio data line. SCLK/DEM 5 Serial Clock (Input) - Serial clock for the serial audio interface. FILT+ 7 Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling circuits. AOUTA AOUTB Analog Outputs (Output) - The full-scale analog line output level is specified in the Analog Characteris- tics table. GND 6, 10 Ground (Input) - Ground reference. See Section 4.10 on page 18 for layout considerations. VA 11 Analog, Charge Pump, and Regulator Power (Input) - Positive power supply for the analog, inverting charge pump, and regulator for the digital core logic sections. FLYP FLYN Inverting Charge Pump Cap Positive/Negative Nodes (Output) - Positive and Negative nodes for the inverting charge pump’s flying capacitor. -VFILT 14 Inverting Charge Pump Filter Connection (Output) - Power supply from the inverting charge pump that provides the negative rail for the output amplifiers. VL -VFILT SDIN FLYN MCLK FLYP LRCK VA SCLK/DEM GND GND AOUTB FILT+ AOUTA
- CHARACTERISTICS AN D SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS GND = 0 V; all voltages with respect to ground.(Note 1) Notes: 1. Device functional operation is gu aranteed within these limits. Functionality is not guaranteed or implied outside of these limits. Operation outside of these limits may adversely affect device reliability. ABSOLUTE MAXIMUM RATINGS GND = 0 V; all voltages with respect to ground. WARNING: Operation at or beyond these limit s may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. Notes: 2. The maximum over/under voltage is limited by the input current except on the power supply pin. Parameters Symbol Min Typ Max Units DC Power Supply Analog power Interface power VA VL 4.75 1.4 5.0 1.8, 3.3, 5.0 5.25 5.25 V V Ambient Operating Temperature (Power Applied) -CSZ T A -40 - +85 °C Parameters Symb ol Min Max Units DC Power Supply Low Voltage Analog Power Interface Power VA VL -0.3 -0.3 6.0 6.0 V V Input Current, Any Pin Except Supplies I in -± 1 0 m A Digital Input Voltage (Note 2) Digital Interface V IN-L -0.3 VL+ 0.4 V Ambient Operating Temperature (Power Applied) T A -55 +125 °C Storage Temperature T stg -65 +150 °C
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DAC ANALOG CHARACTERISTICS Test conditions (unless otherwise specified): TA = 25 °C; VA = 5 V, VL = 3.3 V; GND = 0 V; FILT+, -VFILT, and FLYP/N capacitors as shown in Figure 5 on page 12; input test signal is a 997 Hz sine wave at 0 dBFS; measure- ment bandwidth 20 Hz to 20 kHz. Notes: 3. Measured at the output of the external low-pass filter on AOUTx as shown in Figure 5 on page 12. 4. Measured between the AOUTx and GND pins. 5. One LSB of triangular PDF dither is added to data. 6. Does not include attenuation due to Z OUT. Additional impedance between the AOUTx pin and the load will lower the voltage delivered to the load. 7. V PP is the controlling specification. VRMS specification valid for sine wave signals only. Note that for sine wave signals: Parameter Symbol Min Typ Max Unit Dynamic Performance, Fs = 48, 96, and 192 kHz (Notes 3, 5) Dynamic Range 24-bit A-Weighted unweighted 16-bit A-Weighted unweighted 101 dB dB dB dB Total Harmonic Distortion + Noise 24-bit 0 dB -20 dB -60 dB 16-bit 0 dB -20 dB -60 dB THD+N -86 -78 -38 -86 -73 -33 -80 -72 -32 dB dB dB dB dB dB Idle Channel Noise / Signal-to-Noise Ratio (A-wt) - 101 - dB Interchannel Isolation (1 kHz) - 100 - dB Analog Output (Note 4) Full Scale AOUTx Output Voltage (Notes 6, 7) 0.38•VA 0.40•VA 0.42•VA V RMS 1.07•VA 1.13•VA 1.19•VA V pp Interchannel Gain Mismatch - 0.1 - dB Output Offset - ±1 ±8 mV Gain Drift - 100 - ppm/°C Output Impedance Z OUT -1 0 0- Load Resistance R L 3-- k Load Capacitance C L -- 1 0 0 p F VRMS Vpp
COMBINED DIGITAL AND ON-CHIP ANALOG FILTER CHARACTERISTICS The filter characteristics have been normalized to the sample rate (Fs) and can be referenced to the desired sam- ple rate by multiplying the given characteristic by Fs. Reference level (0 dB) is set at 997 Hz. (Note 11) Notes: 8. Response is clock-dependent and will scale with Fs. 9. For Single- and Double-Speed Mode, the Measurement Bandwidth is from stopband to 3 Fs. For Quad-Speed Mode, the Measurement Bandwidth is from stopband to 1.34 Fs. 10. De-emphasis is available only in Single-Speed Mode. 11. Amplitude vs. frequency plots of this data are available in “Combined Digital and On-chip Analog Filter Response Plots” on page 19. Parameter Min Typ Max Unit Single-Speed Mode - 48 kHz Passband (Note 8) to -0.05 dB corner to -3 dB corner 1.796•10-4 1.947•10-5 0.470 0.500 Fs Fs Frequency Response 20 Hz to 20 kHz -0.05 - +0.05 dB StopBand 0.550 - - Fs StopBand Attenuation (Note 9) 80 dB - - dB High Pass Filter Settling Time (input signal goes to 95% of its final value) - 2.452•10 4/Fs - s Total Group Delay - 9.4/Fs - s De-emphasis Error (Note 10)(Relative to 1 kHz) Fs = 44.1 kHz - - ±0.14 dB Double-Speed Mode - 96 kHz Passband (Note 8) to -0.05 dB corner to -3 dB corner 8.980•10-5 9.736•10-6 0.290 0.500 Fs Fs Frequency Response 20 Hz to 20 kHz -0.05 - +0.05 dB StopBand 0.583 - - Fs StopBand Attenuation (Note 9) 82 dB - - dB High Pass Filter Settling Time (input signal goes to 95% of its final value) - 4.903•10 4/Fs - s Total Group Delay - 7.0/Fs - s Quad-Speed Mode - 192 kHz Passband (Note 8) to -0.05 dB corner to -3 dB corner 4.490•10-5 4.868•10-6 0.253 0.486 Fs Fs Frequency Response 20 Hz to 20 kHz -0.05 - +0.05 dB StopBand 0.630 - - Fs StopBand Attenuation (Note 9) 85 dB - - dB High Pass Filter Settling Time (input signal goes to 95% of its final value) - 9.807•10 4/Fs - s Total Group Delay - 4.9/Fs - s
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SWITCHING SPECIFICATIONS - SERIAL AUDIO INTERFACE 12. Not all sample rates are supported for all clock ratios. See Section 4.2 “Sample Rate Range/Operational Mode Detect” on page 13 for supported ratios and frequencies. SSM = Single-Speed Mode, DSM = Double-Speed Mode, QSM = Quad-Speed Mode. 13. SCLK period is defined by the SCLK / LRCK ratio. The SCLK / LRCK ratio may be either 32, 48, or 64. See Table 5 on page 14. 14. Parameters Symbol Min Typ Max Units MCLK Frequency 7.6 - 55.3 MHz MCLK Duty Cycle 45 - 55 % Input Sample Rate All MC LK/LRCK ratios combined (Note 12) (SSM) 256x, 384x, 512x, 768x, 1024x (DSM) 128x, 192x, 256x, 384x, 512x (QSM) 128x, 192x, 256x Fs 30 170 216 108 216 kHz kHz kHz kHz External SCLK Mode LRCK Duty Cycle 45 - 55 % SCLK Pulse Width Low t sclkl 20 - - ns SCLK Pulse Width High t sclkh 20 - - ns SCLK Duty Cycle 45 - 55 % SCLK rising to LRCK edge delay t slrd 20 - - ns LRCK edge to SCLK rising delay t slrs 20 - - ns SDIN valid to SCLK rising setup time t sdlrs 20 - - ns SCLK rising to SDIN hold time t sdh 20 - - ns Internal SCLK Mode LRCK Duty Cycle SCLK Period (Note 13) tsclkw -- n s MCLK falling to LRCK edge t mclkf -n s LRCK edge to SCLK rising t sclkr - (Note 14) -n s SDIN valid to SCLK rising setup time t sdlrs -- n s SCLK rising to SDIN hold time MCLK / LRCK = 1024, 512, 256, 128 tsdh ns MCLK / LRCK = 768, 384, 192 - - 50% 1 2M C L K 2M C L K 109 109– 109 109 109 tsclkr tsclkw
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Test conditions (unless otherwise specified): GND = 0 V; all voltages with respect to ground. Test conditions (unless otherwise specified): GND = 0 V; all voltages with respect to ground. Table 1. Power-On Reset Threshold Voltages Figure 4. Power-On Reset Threshold Sequence
ance between speed modes is small.
- During normal operation, SDIN = 997 Hz sine wave at 0 dBFS with load resistance R L = 3 k.
- Power-down is defined as all clock and data lines he ld static low. All digital inputs have a weak pull-
increase the power-down current.
- Valid with the recommended capacitor values as shown in the typical connection diagram in Section 5.
2.1 Digital I/O Pin Characteristics
exceed the corresponding power supply voltage. Table 2. Digital I/O Pin Characteristics
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- TYPICAL CONNECTION DIAGRAM
Figure 5. Typical Connection Diagram
4.1 Ground-Centered Line Outputs
between the AOUTx pin and the load will lower the voltage delivered to the load.
4.2 Sample Rate Range/Ope rational Mode Detect
Table 3. Sample rates outside the specified range for eac h mode are not supported. In addition to a valid for speed mode auto-detection; see Figure 9. Table 3. CS4354 Operational Mode Auto-Detect
4.3 System Clocking
The device requires external generation of the master (MCLK), left/right (LRCK) and serial (SCLK) clocks. dard audio sample rates and the required MCLK frequency, are illustrated in Table 4 on page 13. to “Switching Specifications - Serial Audio Interface” on page 8 for the maximum allowed clock frequencies. Table 4. Common MCLK and LRCK Frequencies
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4.4 Serial Clock
and internal serial clock generation modes. Refer to Figure 6 for a diagram of the I²S data format. and 4.4.2 describe this feature in detail.
4.4.1 External Serial Clock Mode
Clock Mode and de-emphasis filter are disabled (see Figure 9 for flow diagram).
4.4.2 Internal Serial Clock Mode
SCLK/LRCK frequency ratio is either 32, 48, or 64 depending on the speed mode and MCLK frequency. as multiples of LRCK frequency). Table 5. Internal SCLK Frequencies
4.4.2.1 De-Emphasis Control
44.1 kHz. The frequency response of the de-emphasis curve scales with changes in the sample rate, Fs. The de-emphasis error will increase for sample rates other than 44.1 kHz. information see “Internal Serial Clock Mode” on page 14. Figure 6. CS4354 Data Format (I²S)
De-emphasis selection is disabled in the external SCLK mode. Note: De-emphasis is only available in Single-Speed Mode.
4.5 Internal High-Pass Filter
“Switching Specifications - Serial Audio Interface” on page 8 for filter specifications.
4.6 Digital Interface Format
The device accepts audio samples in the industry standard I²S format only.
- SDIN is valid on the rising edge of SCLK. For more information about serial audio formats, refer to Cirrus
4.7 Internal Power-On Reset
required for the POR circuit to function. Figure 8. Internal Power-On Reset Circuit Figure 7. De-Emphasis Curve, Fs = 44.1 kHz
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digital circuitry. Once the VA supply reaches the secondary threshold, V on2, the POR circuit releases the internal reset. When power is removed and the VA voltage reaches a defined threshold, V off, the POR circuit asserts the internal reset low, resetting all of the digital circuitry. Note: For correct operation of the internal POR circuit, the voltage on VL must rise before or simulta- neously with VA.
4.8 Initialization
When power is first applied, the DAC enters a reset (l ow power) state at the beginning of the initialization sequence. In this state, the AOUTx pins are weakly pulled to ground and FILT+ is connected to GND. The device will remain in the reset state until V ON2 is reached. Once V ON2 is reached, the internal digital circuitry is reset and the DAC enters a power-down state until MCLK is applied. Once MCLK is valid, the device enters an initialization state in which the charge pump powers up and charg- es the capacitors for the negative voltage supply. Once LRCK is valid, the num ber of MCLK cycles is counted relative to the LRCK period to determine the MCLK/LRCK frequency ratio. Next, the device enters th e power-up state in which the interpolation filters and delta-sigma modulators are turned on, the internal voltage reference, FILT+, powers up to normal op- eration, the analog output pull-down resistors are removed, and power is applied to the output amplifiers. If a valid SCLK is applied, the device will clock in data according to the applied SCLK. If no SCLK is present, the device will clock in data using the derived internal SCLK (see Figure 3 on page 9) and will apply the de- emphasis filter according to Section 4.4.2.1 on page 14. After this power-up state sequence is complete, normal operation begins and analog output is generated. If valid MCLK, LRCK, and SCLK are applied to the DAC before V ON2 is reached, the total time from V ON2 to the analog audio output from AOUTx is less than 50 ms. See Figure 9 for a diagram of the device’s states and transition conditions.
Figure 9. Initialization and Power-Down Sequence Diagram
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4.9 Recommended Power-Up and Power-Down Sequences
4.9.1 Power-Up Sequence
Follow the power-up sequence below: 1. Apply power. 2. After the power supplies are stable, provide the correct MCLK, LRCK, and SCLK (only in External Serial Clock Mode) signals to progress from the ‘Power-Down State’ in the power-up sequence seen in Figure 9. Please refer to Section 4.4 on page 14 for common clock frequencies in the External Serial Clock Mode, and supported modes in the Internal Serial Clock Mode. The sequence will complete and audio will be output from the AOUTx pins within 50 ms after valid clocks are applied.
4.9.2 Power-Down Sequence
Follow the power-down sequence below: 1. For minimal pops, set the input digital data (SDIN) to zero for at least 8192 consecutive samples. 2. Remove the MCLK signal without applyi ng any glitched pulses to the MCLK pin. 3. Remove the power supply voltages. Note: A glitched pulse is any pulse that is shorter than the period defined by the minimum/maximum MCLK signal duty cycle specification and the nominal frequency of the input MCLK signal. A transient may occur on the analog outputs if the MCLK signal duty cycle specification is violated when the MCLK signal is removed during normal operation; see “Switching Specifications - Serial Audio Interface” on page 8.
4.10 Grounding and Power Supply Arrangements
As with any high-resolution converter, the CS4354 requires careful attention to power supply and grounding arrangements if its potential perf ormance is to be realized. The “Typical Connection Diagram” on page 12 shows the recommended power arrangements with VA and VL connected to clean supplies. It is strongly recommended that a single ground plane be used with the GND pins connected to the common plane; this is important because both pin 6 an d pin 10 provide analog ground reference to the CS4354. Should it be necessary to split the ground planes, the CS4354 should be placed entirely in the analog plane. In this con- figuration, it is critical that the digital and analog ground planes be tied together with a low-impedance con- nection, ideally a strip of copper on the printed circuit board, at a single point near the CS4354. All signals, especially clocks, should be kept away from the FILT+ pin in order to avoid unwanted coupling into the DAC.
4.10.1 Capacitor Placement
Decoupling capacitors should be placed as close to the device as possible, with the low-value ceramic capacitor being the closest. To further minimize imp edance, these capacitors should be located on the same PCB layer as the device. See DC Electrical Characteristics for the voltage present across pin pairs. This is useful for choosing appropriate capacitor volt age ratings and orientation if electrolytic capacitors are used. The CDB4354 evaluation board demonstrates the optimum layout and power supply arrangements.
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Figure 16. Double-Speed Transition Band (detail) Figure 17. Double-Speed Passband Ripple Figure 18. Quad-Speed Stopband Rejection Figure 19. Quad-Speed Transition Band Figure 20. Quad-Speed Transition Band (detail) Figure 21. Quad-Speed Passband Ripple
- PARAMETER DEFINITIONS Total Harmonic Distortion + Noise (THD+N) The ratio of the RMS value of the signal to the RMS sum of all other spectral components over the specified bandwidth (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels. Dynamic Range The ratio of the full-scale RMS value of the signal to the RMS sum of all other spectral components over the specified bandwidth. Dynamic range is a signal-to-noise measurement over the specified bandwidth made with a -60 dBFS signal. 60 dB is then added to the resulting measurement to refer the measurement to full scale. This technique ensures that the distortion components are below the noise level and do not affect the measurement. This measurement technique has been accepted by the Audio Engineering Society, AES17- 1991, and the Electronic Industries Association of Japan, EIAJ CP-307. Interchannel Isolation A measure of crosstalk between the left and right chan nels. Measured for each channel at the converter's output with all zeros to the input under test and a full-scale signal applied to the other channel. Units in deci- bels. Interchannel Gain Mismatch The gain difference between left and right channels. Units in decibels. Gain Drift The change in gain value with temperature. Units in ppm/°C.
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- PACKAGE INFORMATION
7.1 Dimensions
7.2 Thermal Characteristics
DIM MIN NOM MAX MIN NOM MAX A 0.0590 - 0.0708 1.397 - 1.549 A1 0.0040 - 0.0098 0.102 - 0.249 b 0.0138 - 0.0200 0.351 - 0.508 C 0.0075 - 0.0098 0.190 - 0.250 D 0.3380 - 0.3440 8.585 - 8.738 E 0.1520 - 0.1574 3.861 - 3.998 e - 0.050 BSC - - 1.270 BSC - H 0.2300 - 0.2440 5.842 - 6.198 L 0.0160 - 0.0350 0.406 - 0.889 0° - 8° 0° - 8° JEDEC #: MS-012 Controling Dimension is Millimeters Parameter Symbol Min Typ Max Units Junction to Ambient Thermal Impedance 2 Layer Board
4 Layer Board
JA - 110 °C/Watt e 14L SOIC (150 MIL BODY) PACKAGE DRAWING D HE b A c L SEATING PLANE
- ORDERING INFORMATION Product Description Package Pb-Free Grade Temp Range Container Order # CS4354 5 V Stereo Audio DAC with 2 VRMS Line Output 14-pin SOIC YES Commercial -40° to +85° C Rail CS4354-CSZ Tape & Reel CS4354-CSZR CDB4354 CS4354 Evaluation Board - - - - CDB4354
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- REVISION HISTORY Release Changes A1 (Sept ‘09) – Initial release. A2 (July ‘10) – Updated THD+N specification in DAC Analog Characteristics. – Updated dynamic range specification in DAC Analog Characteristics. – Updated idle channel noise/SNR specification in DAC Analog Characteristics. – Updated front page dynamic range and THD+N performance to match updated specifications. – Updated frequency response specification description in Combined Digital and On-Chip Analog Filter Characteristics so that frequency response limits are measured relative to 1 kHz. – Updated Power On Reset threshold values in Internal Power-On Reset Threshold Voltages. – Removed typical specification for LRCK and SCLK in Switching Specifications - Serial Audio Interface. – Updated power supply current specifications in DC Electrical Characteristics. – Updated pin voltage specification in DC Electrical Characteristics. – Corrected MCLK frequency in Table 4 from 33.8680 MHz to 33.8688 MHz. – Updated test condition bandwidth in DAC Analog Characteristics from 10 Hz - 20kHz to 20 Hz - 20kHz – Removed MCLK = 1152x LRCK mode support (per Rev B0 silicon). Updated specifications (LRCK min and corresponding MCLK min) in Switching Specifications - Serial Audio Interface, and applications information in Table 4 and Table 5. – Added (Note 16) to DC Electrical Characteristics. – Updated FILT+ description in Initialization. – Updated interchannel isolation specification in DAC Analog Characteristics. – Updated Table 3 to match specifications in Switching Specifications - Serial Audio Interface. – Removed High Pass Filter Characteristics section; appended updated specifications to Combined Digital and On-Chip Analog Filter Characteristics. – Updated passband and stopband specifications in Combined Digital and On-Chip Analog Filter Characteristics to reflect Rev B0 silicon. – Updated title and plots in Combined Digital and On-chip Analog Filter Response Plots to reflect Rev B0 silicon. – Updated typical output offset in DAC Analog Characteristics. – Updated timing diagram Figure 2 to reflect internal SCLK generation as shown in Figure 3. – Updated Typical Connection Diagram; VL capacitor now recommended by default.
Contacting Cirrus Logic Support For all product questions and inquiries, contact a Cirrus Logic Sales Representative. To find one nearest you, go to www.cirrus.com. IMPORTANT NOTICE “Advance” product information describes products that are in development and subject to development changes. Cirrus Logic, Inc. and its subsidiaries (“Cirrus”) be- lieve that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information t o verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the infor- mation only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROP- ERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRIT- ICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK AND CIR- RUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOM- ER’S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING AT- TORNEYS’ FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. Blu-Ray Disc is a registered trademark of SONY KABUSHIKI KAISHA CORPORATION.