CDB4353

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Technical content

Features

 Multi-bit Delta-Sigma Modulator  106 dB A-wt Dynamic Range  -93 dB THD+N  Single-ended Ground Centered Analog Architecture – No DC-blocking Capacitors Required – Integrated Step-up/Inverting Charge Pump – Filtered Line-level Outputs – Selectable 1 or 2 V RMS Full-scale Output  Low Clock-jitter Sensitivity  Low-latency Digital Filtering  Supports Sample Rates up to 192 kHz  24-bit Resolution  +3.3 V Charge Pump and Core Logic, +3.3 V Analog, and +0.9 to 3.3 V Interface Power Supplies  Low Power Consumption  24-pin QFN, Lead-free Assembly

Description

The CS4353 is a complete stereo digital-to-analog sys- tem including digital interpolation, fifth-order multi-bit delta-sigma digital-to-analog conversion, digital de-em- phasis, analog filtering, and on-chip 2 V RMS line-level driver from a 3.3 V supply. The advantages of this architecture include ideal differ- ential linearity, no distortion mechanisms due to resistor matching errors, no linearity drift over time and temper- ature, high tolerance to clock jitter, and a minimal set of external components. The CS4353 is available in a 24-pin QFN package in Commercial (-40°C to +85°C) grade. The CDB4353 Customer Demonstration Board is also available for de- vice evaluation and implementation suggestions. Please see “Ordering Information” on page 25 for com- plete details. These features are ideal fo r cost-sensitive, 2-channel audio systems including video game consoles, DVD players and recorders, A/V receivers, set-top boxes, digital TVs, mini-compone nt systems, and mixing consoles. PCM Serial Audio Port Level Shifter Serial Audio Input Multibit ΔΣ Modulator Interpolation Filters Digital Core Logic and Charge Pump Supply (VCP) +3.3 V Left Channel Right Channel Hardware Control Power-On Reset Hardware Control Reset Auto Speed Mode Detect Analog Supply (VA) +3.3 V Inverting Step-Up +VA_H -VA_H Interface Supply (VL) +0.9 V to +3.3 V Ground-Centered,

2 Vrms Line Level Outputs

DAC Pseudo Diff. Input JUN '09 DS803F1 CS4353

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1. PIN DESCRIPTIONS Pin Name Pin # Pin Description SCLK 1 Serial Clock (Input) - Serial clock for the serial audio interface. MCLK 2 Master Clock (Input) - Clock source for the delta-sigma modulator and digital filters. VL 3 Serial Audio Interface Power (Input) - Positive power for the serial audio interface DGND 4 Digital Ground (Input) - Ground reference for the digital section. FLYP+ FLYP- Step-up Charge Pump Cap Positive/Negative Nodes (Output) - Positive and Negative nodes for the step-up charge pump’s flying capacitor. VCP 6 Charge Pump and Digital Core Logic Power (Input) - Positive power supply for the step-up and invert- ing charge pumps as well as the digital core logic sections. VFILT+ 8 Step-up Charge Pump Filter Connection (Output) - Power supply from the step-up charge pump that provides the positive rail for the output amplifiers FLYN+ FLYN- Inverting Charge Pump Cap Positive/Negative Nodes (Output) - Positive and Negative nodes for the inverting charge pump’s flying capacitor. CPGND 10 Charge Pump Ground (Input) - Ground reference for the Charge Pump section. VFILT- 12 Inverting Charge Pump Filter Connection (Output) - Power supply from the inverting charge pump that provides the negative rail for the output amplifiers. AOUTB AOUTA Analog Outputs (Output) - The full-scale analog line output level is specified in the Analog Characteris- tics table. AOUT_REF 14 Pseudo Diff. Analog Output Reference (Input) - Ground reference for the analog output amplifiers. This pin must be at the same nominal DC voltage as the AGND pin. AGND 16 Analog Ground (Input) - Ground reference for the low voltage analog section. 9 10 11 12 192021222324 Top-Down (Through Package) View 24-Pin QFN Package SDIN LRCK I²S/LJ DEM 1_2VRMS RESET FLYP+ VFILT+ FLYN+ CPGND FLYN- SCLK MCLK VL DGND FLYP- VBIAS VA AGND AOUT_REF AOUTB Thermal Pad VCP VFILT- AOUTA

VA 17 Low Voltage Analog Power (Input) - Positive power supply for the analog section. VBIAS 18 Positive Voltage Reference (Output) - Positive reference voltage for the internal DAC. RESET 19 Reset (Input) - Optional connection for an external reset control. The device enters a powered-down state when this pin is set low (GND) OR when the VCP supply falls below the Voff threshold (see See “Internal Power-on Reset Threshold Voltages” on page 10.). This pin should be set high (VL) during nor- mal operation. 1_2VRMS 20 1 or 2 VRMS Select (Input) - Selects the analog output full-scale voltage. Setting this pin low (GND) selects 1 VRMS, while setting it high (VL) selects 2 VRMS. DEM 21 De-emphasis (Input) - Selects the standard 50 μs/15 μs digital de-emphasis filter response for 44.1 kHz sample rates when enabled. I²S/LJ 22 Digital Interface Format (Input) - Selects the serial audio interface format. Setting this pin low (GND) selects I²S, while setting it high (VL) selects Left-Justified. LRCK 23 Left / Right Clock (Input) - Determines which channel, Left or Right, is currently active on the serial audio data line. SDIN 24 Serial Audio Data Input (Input) - Input for two’s complement serial audio data. Thermal Pad - Thermal Relief Pad - This pad may be soldered to the board, however it MUST be electrically isolated from all board connections.

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1. CHARACTERISTICS A ND SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS AGND = DNGD = CPGND = 0 V; all voltages with respect to ground. Notes: 1. VCP and VA must be supplied with the same nominal voltage. Additional current draw will occur if the sup- ply voltages applied to VCP and VA differ by more than 0.5 V. ABSOLUTE MAXIMUM RATINGS AGND = DNGD = CPGND = 0 V; all voltages with respect to ground. WARNING: Operation at or beyond these limit s may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. Parameters Symbol Min Typ Max Units DC Power Supply Charge Pump and Digital Core power (Note 1) Low Voltage Analog power (Note 1) Interface power VCP VA VL 3.13 3.13 0.85 3.3 3.3 0.9 to 3.3 3.47 3.47 3.47 V V V Ambient Operating Temperature (Power Applied) T A -40 - +85 °C Parameters Symbol Min Max Units DC Power Supply Charge Pump and Digital Core Logic Power Low Voltage Analog Power Supply Voltage Difference Interface Power VCP VA |VCP - VA| VL -0.3 -0.3 -0.3 3.63 3.63 0.5 3.63 V V V V Input Current, Any Pin Except Supplies I in -± 1 0 m A Digital Input Voltage Digital Interface V IN-L -0.3 V L+ 0.4 V Analog Input Voltage AOUT_REF V IN-A -0.3 0.5 V Ambient Operating Temperature (Power Applied) T A -55 +125 °C Storage Temperature T stg -65 +150 °C

DAC ANALOG CHARACTERISTICS Test conditions (unless otherwise specified): TA = 25 °C; VCP = VA = 3.3 V; AOUT_REF = AGND = DGND = CPGND = 0 V; VBIAS, VFILT+/-, and FLYP/N+/- capacitors as shown in Figure 3 on page 12; input test signal is a 997 Hz sine wave at 0 dBFS; measurement bandwidth 10 Hz to 20 kHz. Notes: 2. Measured at the output of the ex ternal LPF on AOUTx as shown in Figure 3 on page 12. 3. One-half LSB of triangular PDF dither is added to data. 4. Measured with the specified minimum AC-Load Resistance present on the AOUTx pins. 5. Measured between the AOUTx and AOUT_REF pins. 6. External impedance between the AOUTx pin and the lo ad will lower the voltage delivered to the load. 7. V PP is the controlling specification. VRMS specification valid for sine wave signals only. Note that for sine wave signals: 8. Measured with AOUT_REF connecte d directly to ground. External impedance between AOUT_REF and ground will lower the AOUT_REF rejection. 1_2VRMS = 0 1_2VRMS = 1 Parameter Symbol Min Typ Max Min Typ Max Unit Dynamic Performance, Fs = 48, 96, and 192 kHz (Notes 2, 3, 4) Dynamic Range 24-bit A-Weighted unweighted 16-bit A-Weighted unweighted 100 100 106 103 dB dB dB dB Total Harmonic Distortion + Noise 24-bit 0 dB -20 dB -60 dB 16-bit 0 dB -20 dB -60 dB THD+N -93 -77 -37 -93 -75 -29 -87 -71 -31 -93 -83 -43 -93 -75 -35 -87 -77 -37 dB dB dB dB dB dB Idle Channel Noise / Signal-to-Noise Ratio (A-wt) - 100 - - 106 - dB Interchannel Isolation (1 kHz) - 115 - - 115 - dB Analog Output (Note 5) Max Current Draw from an AOUTx Pin I OUTmax -5 7 5- -5 7 5- μA Interchannel Gain Mismatch - 0.1 - - 0.1 - dB Output Offset - ±5 ±8 - ±5 ±8 mV Gain Drift - 100 - - 100 - ppm/°C Output Impedance Z OUT -1 0 0- -1 0 0- Ω AC-Load Resistance R L 5--5-- k Ω Load Capacitance C L - - 1000 - - 1000 pF AOUT_REF Rejection (Notes 8, 9) A O R-4 0- -4 0-d B Analog Reference Input AOUT_REF Input Voltage (Note 10) -- 0 . 2 -- 0 . 2 V p p VRMS Vpp

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1. SDIN = 0. AOUT_REF input test signal is a 60 Hz, 50 mVpp sine wave. Measured by applying the test signal into the AOUT_REF pin and measuring the resulting output amplitude on the AOUTx pin. Spec- ification calculated by: 10. Applying a DC voltage on the AOUT_REF pin w ill cause a DC offset on the DAC output. See Section 4.1.3 for more information. COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE The filter characteristics have been normalized to the sample rate (Fs) and can be referenced to the desired sam- ple rate by multiplying the given characteristic by Fs. Notes: 11. Response is clock-dependent and will scale with Fs. 12. For Single- and Double-Speed Mode, the Meas urement Bandwidth is from stopband to 3 Fs. For Quad-Speed Mode, the Measurement Bandwidth is from stopband to 1.34 Fs. 13. De-emphasis is available only in Single-Speed Mode. 14. Amplitude vs. Frequency plots of this data are available in “Digital Filter Response Plots” on page 21. Parameter Min Typ Max Unit Single-Speed Mode - 48 kHz Passband (Note 11) to -0.01 dB corner to -3 dB corner .454 .499 Fs Fs Frequency Response 10 Hz to 20 kHz -0.01 - +0.01 dB StopBand 0.547 - - Fs StopBand Attenuation (Note 12) 102 - - dB Total Group Delay (Fs = Sample Rate) - 9.4/Fs - s Intra-channel Phase Deviation - - ±0.56/Fs s Inter-channel Phase Deviation - - 0 s De-emphasis Error (Note 13)(Relative to 1 kHz) Fs = 44.1 kHz - - ±0.14 dB Double-Speed Mode - 96 kHz Passband (Note 11) to -0.01 dB corner to -3 dB corner .430 .499 Fs Fs Frequency Response 10 Hz to 20 kHz -0.01 - 0.01 dB StopBand .583 - - Fs StopBand Attenuation (Note 12) 80 - - dB Total Group Delay (Fs = Sample Rate) - 4.6/Fs - s Intra-channel Phase Deviation - - ±0.03/Fs s Inter-channel Phase Deviation - - 0 s Quad-Speed Mode - 192 kHz Passband (Note 11) to -0.01 dB corner to -3 dB corner .105 .490 Fs Fs Frequency Response 10 Hz to 20 kHz -0.01 - 0.01 dB StopBand .635 - - Fs StopBand Attenuation (Note 12) 90 - - dB Total Group Delay (Fs = Sample Rate) - 4.7/Fs - s High-Pass Filter Characteristics Passband (Note 11) to -0.05 dB corner to -3 dB corner 9.00x10-5 9.74x10-6 Fs Fs Passband Ripple - - 0.01 dB Phase Deviation @ 20 Hz - - 1.34 Deg Filter Settling Time (input signal goes to 95% of its final value) - 5x10 4/Fs - s AOR dB 20 log 10 AOUT _REF ⋅=

Figure 1. Serial Input Timing

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Test conditions (unless otherwise specified): AGND = DGND = CPGND = 0 V; all voltages with respect to ground. Test conditions (unless otherwise specified): AGND = DGND = CPGND = 0 V; all voltages with respect to ground. Figure 2. Power-on Reset Threshold Sequence

all voltages with respect to ground. ance between speed modes is small.

1. Power-down is defined as RESET pin = Low with all clock and data lines held static low. All digital inputs

down will slightly increase the power-down current.

1. Valid with the recommended capacitor value on VBIAS as shown in the typical connection diagram in
2. Typical voltage shown for “Initialization State”, see Section 4.8. Typical voltage may be up to 1.5 V lower

2.1 Digital I/O Pin Characteristics

exceed the corresponding power supply voltage. Table 1. Digital I/O Pin Characteristics

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1. TYPICAL CONNECTION DIAGRAM

Figure 3. Typical Connection Diagram

4.1 Line Outputs

4.1.1 Ground-centered Outputs

er supply voltages, and provides improved bandwidth frequency response.

4.1.2 Full-scale Output Amplitude Control

Characteristics table for the complete specifications of the full-scale output voltage.

4.1.3 Pseudo-differential Outputs

voltage on the AOUT_REF pin will cause a DC offset on the DAC output. Figure 4. Stereo Pseudo-differential Output

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4.2 Sample Rate Range/Operational Mode Detect

Table 2. Sample rates outside the specified range for each mode are not supported. In addition to a valid for speed mode auto-detection; see Figure 9. Table 2. CS4353 Operational Mode Auto-Detect

4.3 System Clocking

The device requires external generation of the master (MCLK), left/right (LRCK) and serial (SCLK) clocks. dard audio sample rates and the required MCLK frequency, are illustrated in Tables 3-5. to “Switching Specifications - Serial Audio Interface” on page 9 for the maximum allowed clock frequencies. Table 3. Single-speed Mode Standard Frequencies Table 4. Double-speed Mode Standard Frequencies Table 5. Quad-speed Mode Standard Frequencies

4.4 Digital Interface Format

SCLK must have at least 32 cycles per LRCK period in the Left-Justified format. nel Serial Audio Interface: A Tutorial, available at http://www.cirrus.com. Table 6. Digital Interface Format Figure 5. I²S, up to 24-bit Data Figure 6. Left-justified up to 24-bit Data

4.5 Internal High-Pass Filter

the Combined Interpolation & On-Chip Analog Filter Response table for filter specifications.

0 I²S, up to 24-bit Data 5

1 Left-Justified, up to 24-bit Data 6

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4.6 De-emphasis Control

44.1 kHz. The frequency response of the de-emphasi s curve scales with changes in the sample rate, Fs. The de-emphasis error will increase for sample rates other than 44.1 kHz. connected to GND, the de-emphasis filter is turned off. Note: De-emphasis is only available in Single-Speed Mode.

4.7 Internal Power-on Reset

connected to VL during power-up and power-down sequenc es if the external reset function is not needed. ages” on page 10). No external clocks are required for the POR circuit to function. Figure 8. Internal Power-on Reset Circuit internal reset low, resetting all of the digital circuitry. Figure 7. De-emphasis Curve, Fs = 44.1 kHz

4.8 Initialization

When power is first applied, the DAC enters a reset (l ow power) state at the beginning of the initialization sequence. In this state, the AOUTx pins are weakly pulled to ground and VBIAS is connected to VA. The device will remain in the reset state until the RESET pin is brought high. Once the RESET pin is high, the internal digital circuitry is reset and the DAC enters a power-down state until MCLK is applied. Alterna- tively, if no external reset control is required, the internal power-on reset can be used by tying the RESET pin to VL (see Section 4.7). Once MCLK is valid, the device enters an initialization state in which the charge pump powers up and charg- es the capacitors for both the positive and negative high-voltage supplies. Once LRCK and SCLK are valid, the number of MCLK cycles is counted relative to the LRCK period to de- termine the MCLK/LRCK frequency rati o. Next, the device enters the pow er-up state in which the interpo- lation and decimation filters and delta-sigma modula tors are turned on, the internal voltage reference, VBIAS, powers up to normal operation, the analog output pull-down resistors are removed, and power is applied to the output amplifiers. After this power-up state sequence is complete, normal operation begins and analog output is generated. If valid MCLK, LRCK, and SCLK are applied to the DAC before RESET is set high, the total time from RE- SET being set high to the analog audio output from AOUTx is less than 50 ms. See Figure 9 for a diagram of the device’s states and transition conditions.

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Figure 9. Initialization and Power-down Sequence Diagram

4.9 Recommended Power-up and Power-down Sequences

4.9.1 Power-up Sequences

4.9.1.1 External RESET Power-up Sequence

Follow the power-up sequence below if the external RESET pin is used: 1. Hold RESET low while the power supplies are turned on. 2. Set the I²S /LJ, 1_2VRMS, and DEM configuration pins to the desired state. 3. Provide the correct MCLK, LRCK, and SCLK signals locked to the appropriate frequencies as discussed in Section 4.3. 4. After the power supplies, co nfiguration pins, and clock signals are stable, bring RESET high. The device will initiate the power-up sequence seen in Figure 9. The sequence will complete and audio will be output from AOUTx within 50 ms after RESET is set high.

4.9.1.2 Internal Power-on Reset Power-up Sequence

Follow the power-up sequence below if the internal power-on reset is used: 1. Hold RESET high (connected to VL) while the power supplies are turned on. The power-on reset circuitry will function as described in Section 4.7. 2. Set the I²S /LJ, 1_2VRMS, and DEM configuration pins to the desired state. 3. After the power supplies and configuration pins are stable, provide the correct MCLK, LRCK, and SCLK signals to progress from the ‘Power-Down State’ in the power-up sequence seen in Figure 9. The sequence will complete and audio will be output from the AOUTx pins within 50 ms after valid clocks are applied.

4.9.2 Power-down Sequences

4.9.2.1 External RESET Power-down Sequence

Follow the power-down sequence below if the external RESET pin is used: 1. For minimal pops, set the input digital data to zero for at least 8192 consecutive samples. 2. Bring RESET low. 3. Remove the power supply voltages.

4.9.2.2 Internal Power-on Reset Power-down Sequence

Follow the power-down sequence below if the internal power-on reset is used: 1. For minimal pops, set the input digital data to zero for at least 8192 consecutive samples. 2. Remove the MCLK signal without applying any glitched pulses to the MCLK pin. 3. Remove the power supply voltages. Note: A glitched pulse is any pulse that is shorter than the period defined by the minimum/maximum MCLK signal duty cycle specification and the nominal frequency of the input MCLK signal. A transient may occur on the analog outputs if the MCLK signal duty cycle specification is violated when the MCLK signal is removed during normal operation; see “Switching Specifications - Serial Audio Interface” on page 9.

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4.10 Grounding and Power Supply Arrangements

As with any high-resolution converter, the CS4353 requires careful attention to power supply and grounding arrangements if its potential performance is to be realized. Figure 3 shows the recommended power ar- rangements, with VCP, VA, and VL connected to cle an supplies. It is strongly recommended that a single ground plane be used, with the DGND, CPGND, and AGND pins all connected to this common plane. Should it be necessary to split the ground planes, the DGND and CPGND pins should be connected to the digital ground plane and the AGND pin should be connected to the analog ground plane. In this configura- tion, it is critical that the digital and analog ground planes be tied together with a low-impedance connection, ideally a strip of copper on the printed circuit board, at a single point near the CS4353. All signals, especially clocks, should be kept away from the VBIAS pin in order to avoid unwanted coupling into the DAC.

4.10.1 Capacitor Placement

Decoupling capacitors should be placed as close to the device as possible, with the low-value ceramic capacitor being the closest. To further minimize imp edance, these capacitors should be located on the same PCB layer as the device. If desired, all supply pins may be connected to the same supply, but a decoupling capacitor should still be placed on each supply pin. See DC Electrical Characteristics for the voltage present across pin pairs. This is useful for choosing appropriate capacitor voltage ratings and ori- entation if electrolytic capacitors are used. The CDB4353 evaluation board demonstrates the optimum layout and power supply arrangements.

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Figure 16. Double-speed Transition Band (detail) Figure 17. Double-speed Passband Ripple Figure 18. Quad-speed Stopband Rejection Figure 19. Quad-speed Transition Band Figure 20. Quad-speed Transition Band (detail) Figure 21. Quad-s peed Passband Ripple

1. PARAMETER DEFINITIONS Total Harmonic Distortion + Noise (THD+N) The ratio of the RMS value of the signal to the RMS sum of all other spectral components over the specified bandwidth (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels. Dynamic Range The ratio of the full-scale RMS value of the signal to the RMS sum of all other spectral components over the specified bandwidth. Dynamic range is a signal-to-noise measurement over the specified bandwidth made with a -60 dBFS signal. 60 dB is then added to the resulting measurement to refer the measurement to full scale. This technique ensures that the distortion components are below the noise level and do not affect the measurement. This measurement technique has been accepted by the Audio Engineering Society, AES17- 1991, and the Electronic Industries Association of Japan, EIAJ CP-307. Interchannel Isolation A measure of crosstalk between the left and right chan nels. Measured for each channel at the converter's output with all zeros to the input under test and a full-scale signal applied to the other channel. Units in deci- bels. Interchannel Gain Mismatch The gain difference between left and right channels. Units in decibels. Gain Drift The change in gain value with temperature. Units in ppm/°C.

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1. PACKAGE DIMENSIONS Notes: 1. Dimensioning and tolerance per ASME Y 14.5M-1994. 2. Dimensioning lead width applie s to the metallized terminal and is measured betw een 0.15 mm and 0.30 mm from the terminal tip. INCHES MILLIMETERS NOTE DIM MIN NOM MAX MIN NOM MAX A - - 0.03937 - - 1.00 1 A1 0.00000 - 0.00197 0.00 - 0.05 1 D 0.15748 BSC 4.00 BSC 1 E 0.15748 BSC 4.00 BSC 1 Controlling Dimension is Millimeters Parameter Symbol Min Typ Max Units Junction to Ambient Thermal Impedance 2 Layer Board

4 Layer Board

θJA θJA °C/Watt °C/Watt PIN #1 CORNER LA eb D

1.00 REF

PIN #1 IDENTIFIER LASER MARKING E TOP VIEW SIDE VIEW BOTTOM VIEW 24L QFN (4.00 mm BODY) PACKAGE DRAWING

1. ORDERING INFORMATION 9. REVISION HISTORY Release Changes PP1 – Updated interchannel isolation specification in the DAC Analog Characteristics specification table. – Updated minimum Quad-Speed Mode SCLK period in the Switching Specifications - Serial Audio Interface table. – Updated power supply current and power dissipation specifications in the DC Electrical Characteristics table. – Updated the FLYN+ to FLYN- DC voltage in the DC Electrical Characteristics table. – Added “SDIN = 0” to the test conditions in the DC Electrical Characteristics table. – Updated Section 4.9.1.1 on page 19. – Updated output impedance specification in the DAC Analog Characteristics specification table. PP2 – Removed Automotive Grade. – Added Note 2 and reference to Note 4 in the Dynamic Performance section of the DAC Analog Characteristics table. – Changed “additional” to “external” in Note 6 and 8 on page 7. – Updated full scale output specification in the DAC Analog Characteristics table. – Updated Von2 and Voff specifications in the Internal Power-on Reset Threshold Voltages table. – Added HPF data to Combined Interpolation & On-Chip Analog Filter Response table. – Added Section 4.5 Internal High-Pass Filter. Product Description Package Pb-Free Grade Temp Range Container Order # CS4353 3.3 V Stereo Audio DAC with 2 VRMS Line Output 24-pin QFN YES Commercial -40° to +85° C Rail CS4353-CNZ Tape & Reel CS4353-CNZR CDB4353 CS4353 Evaluation Board - - - - CDB4353

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Contacting Cirrus Logic Support For all product questions and inquiries, contact a Cirrus Logic Sales Representative. To find one nearest you, go to www.cirrus.com. IMPORTANT NOTICE Cirrus Logic, Inc. and its subsidiaries (“Cirrus”) believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives con- sent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROP- ERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRIT- ICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK AND CIR- RUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOM- ER’S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING AT- TORNEYS’ FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners.