CS4340A CIRRUS | Alldatasheet
Document overview
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Technical content
Features
/circle6 101 dB Dynamic Range /circle6 -91 dB THD+N /circle6 +3.3 V or +5 V Power Supply /circle6 50 mW with 3.3 V supply /circle6 Low Clock Jitter Sensitivity /circle6 Filtered Line Level Outputs /circle6 On-Chip Digital De-emphasis for 44.1kHz /circle6 Popguard® Technology for Control of Clicks and Pops /circle6 Up to 200 kHz Sample Rates /circle6 Automatic Mode Detection for Sample Rates between 4 and 200 kHz /circle6 Pin Compatible with the CS4340
Description
The CS4340A is a complete stereo digital-to-analog sys- tem including digital interpolation, fourth-order delta- sigma digital-to-analog conversion, digital de-emphasis and switched capacitor analog filtering. The advantages of this architecture include: ideal differential linearity, no distortion mechanisms due to resistor matching errors, no linearity drift over time and temperature, and a high tolerance to clock jitter. The CS4340A accepts data at all standard audio sample rates up to 192 kHz, consumes very little power, oper- ates over a wide power supply range and is pin compatible with the CS4340, as described in section 3.1. These features are ideal for DVD audio players.
ORDERING INFORMATION
CS4340A-KS 16-pin SOIC, -10 to 70 °C CDB4340A Evaluation Board ∆Σ DAC Analog Filter Serial Audio Interface Interpolation Filter Analog Filter MUTEC AOUTL AOUTR RST LRCK SDIN MCLK External Mute Control SCLK DAC Interpolation Filter De-emphasis DEM DIF0 DIF1 OCT ‘02 DS590PP2
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3.7 Popguard
Contacting Cirrus Logic Support For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find one nearest you go to http://www.cirrus.com/corporate/contacts/sales.cfm IMPORTANT NOTICE "Preliminary" product information describes products that are in production, but for which full characterization data is not yet available. "Advance" product infor- mation describes products that are in development and subject to development changes. Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the infor- mation contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, tradesecrets or other intellectual property rights. Cirrus owns the copyrights of the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other parts of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. An export permit needs to be obtained from the competent authorities of the Japanese Government if any of the products or technologies described in thism a - terial and controlled under the "Foreign Exchange and Foreign Trade Law" is to be exported or taken out of Japan. An export license and/or quota needs tobe obtained from the competent authorities of the Chinese Government if any of the products or technologies described in this material is subject to the PRC Foreign Trade Law and is to be exported or taken out of the PRC. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANT- ED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trade- marks or service marks of their respective owners.
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- PIN DESCRIPTION Pin Name # Pin Description RST 1 Reset (Input) - Powers down device. SDIN 2 Serial Audio Data (Input) - Input for two’s complement serial audio data. SCLK 3 Serial Clock (Input) -Serial clock for the serial audio interface. LRCK 4 Left Right Clock (Input) - Determines which channel, Left or Right, is currently active on the serial audio data line. MCLK 5 Master Clock (Input) - Clock source for the delta-sigma modulator and digital filters. DIF1 DIF0 Digital Interface Format (Input) - Defines the required relationship between the Left Right Clock, Serial Clock and Serial Audio Data. DEM 8 De-emphasis Control (Input) - Selects the standard 15µs/50µs digital de-emphasis filter response for the 44.1 kHz sample rate. FILT+ 9 Positive Voltage Reference (Output) - Positive voltage reference for the internal sampling circuits. VQ 10 Quiescent Voltage (Output) - Filter connection for internal quiescent reference voltage. REF_GND 11 Reference Ground (Input) - Ground reference for the internal sampling circuits. AOUTR AOUTL Analog Outputs (Output) - The full scale analog output level is specified in the Analog Characteristics table. AGND 13 Analog Ground (Input) VA 14 Power (Input) - Positive power for the analog, digital and serial audio interface sections. MUTEC 16 Mute Control (Output) - Control signal for an optional mute circuit. 152 143 134 161 116 107 125 RST MUTEC SDIN AOUTL SCLK VA LRCK AGND MCLK AOUTR DIF1 REF_GND DIF0 VQ DEM FILT+
- TYPICAL CONNECTION DIAGRAM
Figure 1. Typical Connection Diagram
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3.1 Upgrading from the CS4340 to the CS4340A
double and quad-speed modes without external intervention. de-emphasis for 32 and 48 kHz, as does the CS4340.
3.2 Sample Rate Range/Operational Mode Detect
ple rates outside the specified range for each mode are not supported.
3.3 System Clocking
audio sample rates and the required MCLK frequency, are illustrated in Tables 2-4. Table 1. CS4340A Auto-Detect
3.4 Digital Interface Format
LRCK, SCLK and SDIN, see Figures 2-5. Table 2. Single-Speed Mode Standard Frequencies Table 3. Double-Speed Mode Standard Frequencies Table 4. Quad-Speed Mode Standard Frequencies
00 I2S, up to 24-bit data 02
01 Left Justified, up to 24-bit data 13
10 Right Justified, 24-bit Data 24
11 Right Justified, 16-bit Data 35
Table 5. Digital Interface Format - DIF1 and DIF0 Figure 2. CS4340A Format 0 - I 2Su pt o2 4 - B i tD a t a
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3.5 De-Emphasis
ple rate, Fs. Please see Table 6 for the desired de-emphasis control. Figure 3. CS4340A Format 1 - Left Justified up to 24-Bit Data Figure 4. CS4340A Format 2 - Right Justified, 24-Bit Data Figure 6. De-Emphasis Curve Table 6. De-Emphasis Control
0 Disabled
3.6 Power-up Sequence
Reliable power-up can be accomplished by keeping the device in reset until the power supply and config- uration pins are stable, and the clocks are locked to the appropriate frequencies discussed in section 3.3. It is also recommended that reset be enabled if the analog supply drops below the minimum specified oper- ating voltage to prevent power glitch related issues.
3.7 Popguard ® Transient Control
The CS4340A uses Popguard ® technology to minimize the effects of output transients during power-up and power-down. This technology, when used with external DC-blocking capacitors in series with the au- dio outputs, minimizes the audio transients commonly produced by single-ended single-supply converters. It is activated inside the DAC when RST is enabled/disabled and requires no other external control, aside from choosing the appropriate DC-blocking capacitors.
3.7.1 Power-up
When the device is initially powered-up, the audio outputs, AOUTL and AOUTR, are clamped to AGND. Following a delay of approximately 1000 sample periods, each output begins to ramp to- ward the quiescent voltage. Approximately 10,000 LRCK cycles later, the outputs reach V Q and audio output begins. This gradual voltage ramping allows time for the external DC-blocking capac- itors to charge to the quiescent voltage, minimizing the power-up transient.
3.7.2 Power-down
To prevent transients at power-down, the device must first enter its power-down state by enabling RST. When this occurs, audio output ceases and the internal output buffers are disconnected from AOUTL and AOUTR. In their place, a soft-start current sink is substituted which allows the DC- blocking capacitors to slowly discharge. Once this charge is dissipated, the power to the device may be turned off and the system is ready for the next power-on.
3.7.3 Discharge Time
To prevent an audio transient at the next power-on, it is necessary to ensure that the DC-blocking capacitors have fully discharged before turning on the power or exiting the power-down state. If not, a transient will occur when the audio outputs are initially clamped to AGND. The time that the device must remain in the power-down state is related to the value of the DC-blocking capacitance. For example, with a 3.3 µF capacitor, the minimum power-down time will be approximately 0.4 seconds.
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3.8 Mute Control
The Mute Control pin goes high during power-up initialization, reset, or if the MCLK to LRCK ratio is incorrect. The pin will also go high following the reception of 8192 consecutive audio samples of static 0 or -1 on both the left and right channels. A single sample of non-zero data on either channel will cause the Mute Control pin to go low. This pin is intended to be used as a control for an external mute circuit to pre- vent the clicks and pops that can occur in any single-ended single supply system. Use of the Mute Control function is not mandatory but recommended for designs requiring the absolute minimum in extraneous clicks and pops. Also, use of the Mute Control function can enable the system de- signer to achieve idle channel noise/signal-to-noise ratios which are only limited by the external mute cir- cuit. See the CDB4340A data sheet for a suggested mute circuit.
3.9 Grounding and Power Supply Arrangements
As with any high resolution converter, the CS4340A requires careful attention to power supply and grounding arrangements if its potential performance is to be realized. Figure 1 shows the recommended power arrangements, with VA connected to a clean supply. If the ground planes are split between digital ground and analog ground, REF_GND & AGND should be connected to the analog ground plane. Decoupling capacitors should be as close to the DAC as possible, with the low value ceramic capacitor being the closest. To further minimize impedance, these capacitors should be located on the same layer as the DAC. All signals, especially clocks, should be kept away from the FILT+ and VQ pins in order to avoid unwant- ed coupling into the modulators. The FILT+ and VQ decoupling capacitors, particularly the 0.1 µF, must be positioned to minimize the electrical path from FILT+ and REF_GND (as well as VQ and REF_GND), and should also be located on the same layer as the DAC. The CDB4340A evaluation board demonstrates the optimum layout and power supply arrangements.
- CHARACTERISTICS AND SPECIFICATIONS Typical performance characteristics are derived from measurements taken at T A =2 5 °C, VA = 3.3 V and VA = 5.0 V. Min/Max performance characteristics are guaranteed over the specified operating temperature and voltages.) ANALOG CHARACTERISTICS (CS4340A-KS) (Test conditions (unless otherwise specified): Input test signal is a 997 Hz sine wave; measurement bandwidth is 10 Hz to 20 kHz; test load R L =1 0k Ω,C L =1 0 pF (see Figure 7).) Parameter VA = 5.0V VA = 3.3V Min Typ Max Min Typ Max Unit Single-Speed Mode Fs = 48kHz Dynamic Range (Note 1) 18 to 24-Bit unweighted A-Weighted 16-Bit unweighted A-Weighted 101 dB dB dB dB Total Harmonic Distortion + Noise (Note 1) 18 to 24-Bit 0 dB -20 dB -60 dB 16-Bit 0 dB -20 dB -60 dB -91 -78 -38 -90 -72 -32 -85 -94 -74 -34 -91 -72 -32 -88 dB dB dB dB dB dB Double-Speed Mode Fs = 96kHz Dynamic Range (Note 1) 18 to 24-Bit unweighted A-Weighted 16-Bit unweighted A-Weighted 101 dB dB dB dB Total Harmonic Distortion + Noise (Note 1) 18 to 24-Bit 0 dB -20 dB -60 dB 16-Bit 0 dB -20 dB -60 dB -91 -78 -38 -90 -72 -32 -85 -94 -74 -34 -91 -72 -32 -88 dB dB dB dB dB dB Quad-Speed Mode Fs = 192kHz Dynamic Range (Note 1) 18 to 24-Bit unweighted A-Weighted 16-Bit unweighted A-Weighted 101 dB dB dB dB Total Harmonic Distortion + Noise (Note 1) 18 to 24-Bit 0 dB -20 dB -60 dB 16-Bit 0 dB -20 dB -60 dB -91 -78 -38 -90 -72 -32 -85 -94 -74 -34 -91 -72 -32 -88 dB dB dB dB dB dB
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Notes: 1. One-half LSB of triangular PDF dither is added to data. Figure 7. Output Test Load Figure 8. Maximum Loading
COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE (The filter characteristics and the X-axis of the response plots have been normalized to the sample rate (Fs) and can be referenced to the desired sample rate by multiplying the given characteristic by Fs.) Notes: 3. For Single-Speed Mode, the measurement bandwidth is 0.5465 Fs to 3 Fs. For Double-Speed Mode, the measurement bandwidth is 0.577 Fs to 1.4 Fs. 4. De-emphasis is only available in Single-Speed Mode. Parameter Min Typ Max Unit Single-Speed Mode - (4 kHz to 50 kHz sample rates) Passband to -0.05 dB corner to -3 dB corner 0.4535 0.4998 Fs Fs Frequency Response 10 Hz to 20 kHz -0.02 - +0.08 dB StopBand 0.5465 - - Fs StopBand Attenuation (Note 3) 50 - - dB Group Delay - 9/Fs - s Passband Group Delay Deviation 0 - 20 kHz - ±0.36/Fs - s De-emphasis Error (Relative to 1 kHz) Fs = 44.1 kHz (Note 4) - - +0.05/-0.14 dB Double-Speed Mode - (84 kHz to 100 kHz sample rates) Passband to -0.1 dB corner to -3 dB corner 0.4621 0.4982 Fs Fs Frequency Response 10 Hz to 20 kHz -0.06 - +0.2 dB StopBand 0.577 - - Fs StopBand Attenuation (Note 3) 55 - - dB Group Delay - 4/Fs - s Passband Group Delay Deviation 0 - 40 kHz 0-2 0k H z ±1.39/Fs ±0.23/Fs s s Quad-Speed Mode - (170 kHz to 200 kHz sample rates) Frequency Response 10 Hz to 20 kHz -1 - 0 dB Group Delay - 3/Fs - s
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Figure 9. Single-Speed Stopband Rejection Figure 10. Single-Speed Transition Band Figure 11. Single-Speed Transition Band (Detail) Figure 12. Single-Speed Passband Ripple Figure 13. Double-Speed Stopband Rejection Figure 14. Double-Speed Transition Band
Figure 15. Double-Speed Transition Band (Detail) Figure 16. Double-Speed Passband Ripple
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Notes: 5. Speed mode is detected automatically, based on the input sample rate. Figure 17. Serial Input Timing
DC ELECTRICAL CHARACTERISTICS (AGND = 0V; all voltages with respect to AGND.) DIGITAL INTERFACE SPECIFICATIONS (GND = 0 V; all voltages with respect to GND.) DIGITAL INPUT CHARACTERISTICS (AGND = 0V; all voltages with respect to AGND.) THERMAL CHARACTERISTICS AND SPECIFICATIONS Parameters Symbol Min Typ Max Units Normal Operation (Note 6) Power Supply Current VA = 5.0V VA = 3.3V IA - mA mA Power Dissipation VA = 5.0V VA = 3.3V 125 100 mW mW Power-down Mode (Note 7) Power Supply Current VA = 5.0V VA = 3.3V IA - µA µA Power Dissipation VA = 5.0V VA = 3.3V 0.3 0.1 mW mW All Modes of Operation Power Supply Rejection Ratio (Note 8) 1k H z 60 Hz PSRR - dB dB VQ Nominal Voltage Output Impedance Maximum allowable DC current source/sink 0.5VA 250 0.01 V kΩ mA Filt+ Nominal Voltage Output Impedance Maximum allowable DC current source/sink VA 250 0.01 V kΩ mA MUTEC Low-Level Output Voltage - 0 - V MUTEC High-Level Output Voltage - VA - V Maximum MUTEC Drive Current - 3 - mA Parameters Symbol Min Max Units 3.3 V Logic (2.7 V to 3.6 V DC Supply) High-Level Input Voltage V IH 2.0 - V Low-Level Input Voltage V IL -0 . 8 V 5.0 V Logic (4.5 V to 5.5 V DC Supply) High-Level Input Voltage V IH 2.0 - V Low-Level Input Voltage V IL -0 . 8 V Parameters Symbol Min Typ Max Units Input Leakage Current I in -- ± 1 0 µA Input Capacitance - 8 - pF Parameters Symbol Min Typ Max Units Package Thermal Resistance (multi-layer boards) θJA -7 4- °C/Watt Ambient Operating Temperature (Power Applied) T A -10 - +70 °C
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RECOMMENDED OPERATING SPECIFICATION ABSOLUTE MAXIMUM RATINGS (AGND = 0 V; all voltages with respect to AGND. Operation beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes.) Notes: 6. Normal operation is defined as RST = HI with a 997 Hz, 0dBFS input sampled at the highest Fs for each speed mode, and open outputs, unless otherwise specified. 7. Power Down Mode is defined as RST = LO with all clocks and data lines held static. 8. Valid with the recommended capacitor values on FILT+ and VQ as shown in Figure 1. Increasing the capacitance will also increase the PSRR. 9. Any pin except supplies. Parameters Symbol Min Typ Max Units DC Power Supply
3.3 V Nominal
5.0 V Nominal
VA 2.7 4.5 3.3 3.6 5.5 V V Parameters Symbol Min Max Units DC Power Supply VA -0.3 6.0 V Input Current (Note 9) Iin -± 1 0 m A Digital Input Voltage V IND -0.3 VA+0.4 V Ambient Operating Temperature (power applied) T A -55 125 °C Storage Temperature T stg -65 150 °C
- PARAMETER DEFINITIONS Total Harmonic Distortion + Noise (THD+N) The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth (typically 10Hz to 20kHz), including distortion components. Expressed in decibels. Dynamic Range The ratio of the full scale rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. Dynamic range is a signal-to-noise measurement over the specified bandwidth made with a -60 dBFS signal. 60 dB is then added to the resulting measurement to refer the measurement to full scale. This technique ensures that the distortion components are below the noise level and do not affect the measurement. This measurement technique has been accepted by the Audio Engineering So- ciety, AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307. Interchannel Isolation A measure of crosstalk between the left and right channels. Measured for each channel at the converter’s output with all zeros to the input under test and a full-scale signal applied to the other channel. Units in decibels. Interchannel Gain Mismatch The gain difference between left and right channels. Units in decibels. Gain Drift The change in gain value with temperature. Units in ppm/ °C. 6. REFERENCES 1) CDB4340A Evaluation Board Datasheet
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- PACKAGE DIMENSIONS INCHES MILLIMETERS DIM MIN NOM MAX MIN NOM MAX JEDEC #: MS-012 Controling Dimension is Millimeters e 16L SOIC (150 MIL BODY) PACKAGE DRAWING D HE b A c L ∝SEATING PLANE