CS4340 CIRRUS | Alldatasheet
Document overview
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Technical content
Features
lComplete Stereo DAC System: Interpolation, D/A, Output Analog Filtering l101 dB Dynamic Range l91 dB THD+N lLow Clock Jitter Sensitivity l+3 V to +5 V Power Supply lFiltered Line Level Outputs lOn-Chip Digital De-emphasis for 32, 44.1, and 48 kHz l30 mW with 3 V supply lPopguard® Technology for Control of Clicks and Pops
Description
The CS4340 is a complete stereo digital-to-analog sys- tem including digital interpolation, fourth-order delta- sigma digital-to-analog conversion, digital de-emphasis and switched capacitor analog filtering. The advantages of this architecture include: ideal differential linearity, no distortion mechanisms due to resistor matching errors, no linearity drift over time and temperature and a high tolerance to clock jitter. The CS4340 accepts data at audio sample rates from 2 kHz to 100 kHz, consumes very little power, and oper- ates over a wide power supply range. The features of the CS4340 are ideal for DVD players, CD players, set-top box and automotive systems.
ORDERING INFORMATION
CS4340-KS 16-pin SOIC, -10 to 70 °C CS4340-BS 16-pin SOIC, -40 to 85 °C CDB4340 Evaluation Board I ΔΣ DAC Analog Filter Serial Input Interface Interpolation Filter Analog Filter MUTEC AOUTL AOUTR RST LRCK SDATA MCLK ΔΣ External Mute Control SCLK/DEM1 DAC Interpolation Filter De-emphasis DEM0 DIF0 DIF1 NOV ‘00 DS297PP3
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4.4 Popguard
Contacting Cirrus Logic Support For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at: http://www.cirrus.com/corporate/contacts/ Preliminary product information describes products which are in production, but for which full characterization data is not yet available. Advance product infor- mation describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty of any kind (express or implied). No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, nor for infringements of patents or other rights of third parties. This document is the property of Cirrus Logic, Inc. and implies no license under patents, copyrights, trademarks, or trade secrets. No part of this publication may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc. Items from any Cirrus Logic website or disk may be printed for use by the user. However, no part of the printout or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc.Furthermore, no part of this publication may be used as a basis for manufacture or sale of any items without the prior written consent of Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trade- marks and service marks can be found at http://www.cirrus.com.
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- CHARACTERISTICS AND SPECIFICATIONS ANALOG CHARACTERISTICS (Test conditions (unless otherwise specified): TA = 25 °C; Logic "1" = VA = 5 V; Logic "0" = AGND;Full-Scale Output Sine Wave, 997 Hz; MCLK = 12.288 MHz; Fs for Base-rate Mode = 48 kHz, SCLK = 3.072 MHz, Measurement Bandwidth 10 Hz to 20 kHz, unless otherwise specified; Fs for High- Rate Mode = 96 kHz, SCLK = 6.144 MHz, Measurement Bandwidth 10 Hz to 40 kHz, unless otherwise specified. Test load R L = 10 kΩ , CL = 10 pF (see Figure 13) Notes: 1. CS4340-KS parts are tested at 25 °C and Min/Max performance numbers are guaranteed across the specified temperature range, TA. 2. One-half LSB of triangular PDF dither is added to data. Parameter Base-rate Mode High-Rate Mode Symbol Min Typ Max Min Typ Max Unit CS4340-KS Dynamic Performance for VA = 5 V (Note 1) Specified Temperature Range T A -10 - 70 -10 - 70 °C Dynamic Range (Note 2) 18 to 24-Bit unweighted A-Weighted 16-Bit unweighted A-Weighted 101 100 dB dB dB dB Total Harmonic Distortion + Noise (Note 2) 18 to 24-Bit 0 dB -20 dB -60 dB 16-Bit 0 dB -20 dB -60 dB THD+N -91 -78 -38 -90 -75 -35 -86 -89 -76 -36 -89 -74 -34 -84 dB dB dB dB dB dB Interchannel Isolation (1 kHz) - 102 - - 102 - dB CS4340-KS Dynamic Performance for VA = 3 V (Note 1) Specified Temperature Range T A -10 - 70 -10 - 70 °C Dynamic Range (Note 2) 18 to 24-Bit unweighted A-Weighted 16-Bit unweighted A-Weighted dB dB dB dB Total Harmonic Distortion + Noise (Note 2) 18 to 24-Bit 0 dB -20 dB -60 dB 16-Bit 0 dB -20 dB -60 dB THD+N -94 -74 -34 -93 -73 -33 -88 -92 -72 -32 -91 -72 -32 -87 dB dB dB dB dB dB Interchannel Isolation (1 kHz) - 102 - - 102 - dB
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ANALOG CHARACTERISTICS (Continued) Notes: 3. CS4340-BS parts are tested at the extremes of the specified temperature range and Min/Max performance numbers are guaranteed across the specified temperature range, TA. Typical numbers are taken at 25 °C. Parameter Base-rate Mode High-Rate Mode Symbol Min Typ Max Min Typ Max Unit CS4340-BS Dynamic Performance for VA = 5 V (Note 3) Specified Temperature Range T A -40 - 85 -40 - 85 °C Dynamic Range (Note 2) 18 to 24-Bit unweighted A-Weighted 16-Bit unweighted A-Weighted TBD TBD 101 TBD TBD 100 dB dB dB dB Total Harmonic Distortion + Noise (Note 2) 18 to 24-Bit 0 dB -20 dB -60 dB 16-Bit 0 dB -20 dB -60 dB THD+N -91 -78 -38 -90 -75 -35 TBD -89 -76 -36 -89 -74 -34 TBD dB dB dB dB dB dB Interchannel Isolation (1 kHz) - 102 - - 102 - dB CS4340-BS Dynamic Performance for VA = 3 V (Note 3) Specified Temperature Range T A -40 - 85 -40 - 85 °C Dynamic Range (Note 2) 18 to 24-Bit unweighted A-Weighted 16-Bit unweighted A-Weighted TBD TBD TBD TBD dB dB dB dB Total Harmonic Distortion + Noise (Note 2) 18 to 24-Bit 0 dB -20 dB -60 dB 16-Bit 0 dB -20 dB -60 dB THD+N -94 -74 -34 -93 -73 -33 TBD -92 -72 -32 -91 -72 -32 TBD dB dB dB dB dB dB Interchannel Isolation (1 kHz) - 102 - - 102 - dB
ANALOG CHARACTERISTICS (Continued) Notes: 4. Refer to Figure 14. 5. Filter response is guaranteed by design. 6. Response is clock dependent and will scale with Fs. Note that the response plots (Figures 5-12) have been normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs. 7. For Base-Rate Mode, the measurement bandwidth is 0.5465 Fs to 3 Fs. For High-Rate Mode, the measurement bandwidth is 0.577 Fs to 1.4 Fs. 8. De-emphasis is not available in High-Rate Mode. Parameters Symbol Min Typ Max Units Analog Output Full Scale Output Voltage 0.63•VA 0.7•VA 0.77•VA Vpp Quiescent Voltage V Q -0 . 5 • V A- V D C Interchannel Gain Mismatch - 0.1 - dB Gain Drift - 100 - ppm/°C AC-Load Resistance (Note 4) R L 3--k Ω Load Capacitance (Note 4) C L -- 1 0 0 p F Parameter Base-rate Mode High-Rate Mode Symbol Min Typ Max Min Typ Max Unit Combined Digital and On-chip Analog Filter Response (Note 5) Passband (Note 6) to -0.05 dB corner to -0.1 dB corner to -3 dB corner .4535 .4998 .4621 .4982 Fs Fs Fs Frequency Response 10 Hz to 20 kHz -.02 - +.08 -0.06 - 0.2 dB StopBand .5465 - - .577 - - Fs StopBand Attenuation (Note 7) 50 - - 55 - - dB Group Delay tgd - 9/Fs - - 4/Fs - s Passband Group Delay Deviation 0 - 40 kHz 0 - 20 kHz ±0.36/Fs ±1.39/Fs ±0.23/Fs s s De-emphasis Error Fs = 32 kHz (Relative to 1 kHz) Fs = 44.1 kHz Fs = 48 kHz +.2/-.1 +.05/-.14 +0/-.22 (Note 8) dB dB dB
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POWER AND THERMAL CHARACTERISTICS Notes: 9. Refer to Figure 15. 10. Valid with the recommended capacitor values on FILT+ and VQ as shown in Figure 4. Increasing the capacitance will also increase the PSRR. DIGITAL CHARACTERISTICS (for -KS parts TA = -10 to 70°C; for -BS parts TA = -40 to 85°C; CS4340-KS CS4340-BS Parameters Symbol Min Typ Max Min Typ Max Units Power Supplies Power Supply Current normal operation VA = 5 V power-down state IA IA TBD mA µA Power Dissipation (Note 9) VA = 5 V normal operation power-down 0.3 0.3 TBD mW mW Power Supply Current normal operation VA = 3 V power-down state IA IA TBD mA µA Power Dissipation (Note 9) VA = 3 V normal operation power-down 0.09 0.09 TBD mW mW Package Thermal Resistance θJA - 110 - - 110 - °C/Watt Power Supply Rejection Ratio (1 kHz) (Note 10) (60 Hz) PSRR - dB dB Parameters Symbol Min Typ Max Units High-Level Input Voltage VA = 5 V VA = 3 V VIH 2.0 2.0 V V Low-Level Input Voltage VA = 5 V VA = 3 V VIL - 0.8 0.8 V V Input Leakage Current I in -- ± 1 0 µA Input Capacitance - 8 - pF Maximum MUTEC Drive Current - 3 - mA
ABSOLUTE MAXIMUM RATINGS (AGND = 0 V; all voltages with respect to ground.) WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. RECOMMENDED OPERATING CONDITIONS (AGND = 0V; all voltages with respect to ground.) Parameters Symbol Min Max Units DC Power Supply VA -0.3 6.0 V Input Current, Any Pin Except Supplies I in - ±10 mA Digital Input Voltage V IND -0.3 VA+0.4 V Ambient Operating Temperature (power applied) T A -55 125 °C Storage Temperature T stg -65 150 °C Parameters Symbol Min Typ Max Units DC Power Supply VA 2.7 5.0 5.5 V
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SWITCHING CHARACTERISTICS (VA = 2.7 V - 5.5 V; Inputs: Logic 0 = 0 V, Logic 1 = VA, CL = 20 pF; for -KS parts TA = -10 to 70°C; for -BS parts TA = -40 to 85°C) Notes: 11. In Internal SCLK Mode, the Duty Cycle must be 50% +/− 1/2 MCLK Period. 12. The SCLK / LRCK ratio may be either 32, 48, or 64. This ratio depends on part type and MCLK/LRCK ratio. (See figures 16-19) Parameters Symbol Min Typ Max Units Input Sample Rate Base-Rate Mode High-Rate Mode Fs 2 100 kHz kHz MCLK Pulse Width High MCLK/LRCK = 512 10 - 1000 ns MCLK Pulse Width Low MCLK/LRCK = 512 10 - 1000 ns MCLK Pulse Width High MCLK / LRCK = 384 or 192 21 - 1000 ns MCLK Pulse Width Low MCLK / LRCK = 384 or 192 21 - 1000 ns MCLK Pulse Width High MCLK / LRCK = 256 or 128 31 - 1000 ns MCLK Pulse Width Low MCLK / LRCK = 256 or 128 31 - 1000 ns External SCLK Mode LRCK Duty Cycle (External SCLK only) 40 50 60 % SCLK Pulse Width Low t sclkl 20 - - ns SCLK Pulse Width High t sclkh 20 - - ns SCLK Period MCLK / LRCK = 512, 256 or 384 t sclkw --n s SCLK Period MCLK / LRCK = 128 or 192 t sclkw --n s SCLK rising to LRCK edge delay t slrd 20 - - ns SCLK rising to LRCK edge setup time t slrs 20 - - ns SDATA valid to SCLK rising setup time t sdlrs 20 - - ns SCLK rising to SDATA hold time t sdh 20 - - ns Internal SCLK Mode LRCK Duty Cycle (Internal SCLK only) (Note 11) - 50 - % SCLK Period (Note 12) t sclkw --n s SCLK rising to LRCK edge t sclkr -- µs SDATA valid to SCLK rising setup time t sdlrs --n s SCLK rising to SDATA hold time MCLK / LRCK = 512, 256 or 128 tsdh --n s SCLK rising to SDATA hold time MCLK / LRCK = 384 or 192 tsdh --n s tsclkw
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- TYPICAL CONNECTION DIAGRAM
Figure 4. Typical Connection Diagram
- PIN DESCRIPTION RST 1 Reset (Input) - The device enters a low power mode and all internal state machines are reset to the default settings when low. RST should be held low during power-up until the power supply, master and left/right clocks are stable. SDATA 2 Serial Audio Data (Input) - Two's complement MSB-first serial data is input on this pin. The data is clocked into SDATA via the serial clock and the channel is determined by the Left/Right clock. The required relationship between the Left/Right clock, serial clock and serial data is defined by the DIF1-0 pins. The options are detailed in Figures 16-19. SCLK 3 Serial Clock (Input) - Clocks the individual bits of the serial data into the SDATA pin. The required relationship between the Left/Right clock, serial clock and serial data is defined by the DIF1-0 pins. The options are detailed in Figures 16-19. The CS4340 supports both internal and external serial clock generation modes. Internal SCLK mode is used to gain access to extra de-emphasis modes. Internal Serial Clock Mode - In the Internal Serial Clock Mode, the serial clock is internally derived and synchronous with the master clock and left/right clock. The SCLK/LRCK frequency ratio is either 32, 48, or 64 depending upon the DIF1-0 pins as shown in Figures 16-19. Opera- tion in this mode is identical to operation with an external serial clock synchronized with LRCK. External Serial Clock Mode - The CS4340 will enter the External Serial Clock Mode whenever 16 low to high transitions are detected on the SCLK pin during any phase of the LRCK period. The device will revert to Internal Serial Clock Mode if no low to high transitions are detected on the SCLK pin for 2 consecutive periods of LRCK. 152 143 134 161 116 107 125 Reset RST MUTEC Mute Control Serial Data SDATA AOUTL Left Analog Output Serial Clock / De-emphasisSCLK /DEM1 VA Analog Power Left/Right Clock LRCK AGND Analog Ground Master Clock MCLK AOUTR Right Analog Output Digital Interface Format DIF1 REF_GND Reference Ground Digital Interface Format DIF0 VQ Quiescent Voltage De-emphasis DEM0 FILT+ Positive Voltage Reference
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Table 4. NOTE: De-emphasis is not available in High-Rate Mode. defined by the DIF1-0 pins. The options are detailed in Figures 16-19.
00 D i s a b l e d
Table 1. Internal Serial Clock Mode
0 Disabled
Table 2. External Serial Clock Mode Table 3. Common Master Clock Frequencies
mended value will typically provide 60 dB of PSRR at 1 kHz and 40 dB of PSRR at 60 Hz. 250 kΩ and any current drawn from this pin will alter device performance. Figure 4. VQ is not intended to supply external current. VQ has a typical source impedence of 250 kΩ and any current drawn from this pin will alter device performance. teristics specifications table. AGND 13 Ground (Input) - Ground Reference. VA 14 Analog Power (Input) - Analog power supply. Typically 3 to 5 VDC. for designs requiring the absolute minimum in extraneous clicks and pops.
00 I 2S, up to 24-bit data 0 16
Table 4. Digital Interface Format - DIF1 and DIF0
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- APPLICATIONS
4.1 Grounding and Power Supply
As with any high resolution converter, the CS4340 requires careful attention to power supply and grounding arrangements to optimize performance. Figure 4 shows the recommended power arrange- ment with VA connected to a clean supply. Decou- pling capacitors should be located as close to the device package as possible.
4.2 Oversampling Modes
The CS4340 operates in one of two oversampling modes. Base Rate Mode supports input sample rates up to 50 kHz while High Rate Mode supports input sample rates up to 100 kHz. The devices op- erate in Base Rate Mode (BRM) when MCLK/LRCK is 256, 384 or 512 and in High Rate Mode (HRM) when MCLK/LRCK is 128 or 192.
4.3 Recommended Power-up Sequence
RST should be held low until the power supply, master and left/right clocks are stable.
4.4 Popguard ® Transient Control
The CS4340 uses Popguard® technology to mini- mize the effects of output transients during power- up and power-down. This technique, when used with external DC-blocking capacitors in series with the audio outputs, minimizes the audio transients commonly produced by single-ended single-supply converters. When the device is initially powered-up, the audio outputs, AOUTL and AOUTR, are clamped to AGND. Following a delay of approximately 1000 sample periods, each output begins to ramp toward the quiescent voltage. Approximately 10,000 left/right clock cycles later, the outputs reach V Q and audio output begins. This gradual voltage ramping allows time for the external DC-blocking capacitor to charge to the quiescent voltage, mini- mizing the power-up transient. To prevent transients at power-down, the device must first enter its power-down state by setting the RST pin low. When this occurs, audio output ceas- es and the internal output buffers are disconnected from AOUTL and AOUTR. In their place, a soft- start current sink is substituted which allows the DC-blocking capacitors to slowly discharge. Once this charge is dissipated, the power to the device may be turned off and the system is ready for the next power-on. To prevent an audio transient at the next power-on, it is necessary to ensure that the DC-blocking ca- pacitors have fully discharged before turning off the power or exiting the power-down state. If not, a transient will occur when the audio outputs are ini- tially clamped to AGND. The time that the device must remain in the power-down state is related to the value of the DC-blocking capacitance. For ex- ample, with a 3.3 µF capacitor, the minimum pow- er-down time will be approximately 0.4 seconds. Use of the Mute Control function is recommended for designs requiring the absolute minimum in ex- traneous clicks and pops. Also, use of the Mute Control function can enable the system designer to achieve idle channel noise/signal-to-noise ratios which are only limited by the external mute circuit. See the CDB4340/41 data sheet for a suggested mute circuit.
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Figure 11. High-Rate Transition Band (Detail) Figure 12. High-Rate Passband Ripple Figure 13. Output Test Load Figure 14. Maximum Loading Figure 15. Power vs. Sample Rate (VA = 5V)
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Figure 18. CS4340 Format 2 Figure 19. CS4340 Format 3
40 kHz brickwall filter in the DSP Analyzer. Figure 20. De-Emphasis Curve
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Figure 21. FFT 0 dB input, BRM, VA = 3V Figure 22. FFT -60 dB input, BRM, VA = 3V Figure 23. FFT Idle Noise, BRM, VA = 3V Figure 24. Fade-to-Noise Linearity, BRM, VA = 3V Figure 25. THDN vs Ampl, BRM, VA = 3V Figure 26. THDN vs Freq, BRM, VA = 3V
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Figure 33. FFT 0 dB input, HRM, VA = 3V Figure 34. FFT -60 dB input, HRM, VA = 3V Figure 35. FFT Idle Noise, HRM, VA = 3V Figure 36. Fade-to-Noise Linearity, HRM, VA = 3V Figure 37. THDN vs Ampl, HRM, VA = 3V Figure 38. THDN vs Freq, HRM, VA = 3V
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- PARAMETER DEFINITIONS Total Harmonic Distortion + Noise (THD+N) A measure of crosstalk between the left and right channels. Measured for each channel at the converter's output with all zeros to the input under test and a full-scale signal applied to the other channel. Units in decibels. Dynamic Range The ratio of the full scale rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. Dynamic range is a signal-to-noise measurement over the specified bandwidth made with a -60 dBFS signal. 60 dB is then added to the resulting measurement to refer the measurement to full scale. This technique ensures that the distortion components are below the noise level and do not effect the measurement. This measurement technique has been accepted by the Audio Engineering So- ciety, AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307. Interchannel Isolation A measure of crosstalk between the left and right channels. Measured for each channel at the converter’s output with all zeros to the input under test and a full-scale signal applied to the other channel. Units in decibels. Interchannel Gain Mismatch The gain difference between left and right channels. Units in decibels. Gain Error The deviation from the nominal full scale analog output for a full scale digital input. Gain Drift The change in gain value with temperature. Units in ppm/°C. 9. REFERENCES 1) "How to Achieve Optimum Performance from Delta-Sigma A/D & D/A Converters" by Steven Harris. Paper presented at the 93rd Convention of the Audio Engineering Society, October 1992. 2) CDB4340 Evaluation Board Datasheet
- PACKAGE DIMENSIONS INCHES MILLIMETERS DIM MIN NOM MAX MIN NOM MAX JEDEC #: MS-012 Controling Dimension is Millimeters e 16L SOIC (150 MIL BODY) PACKAGE DRAWING D HE b A c L ∝SEATING PLANE