CDB4272

CS4272 CIRRUS | Alldatasheet

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Copyright © Cirrus Logic, Inc. 2005 (All Rights Reserved) Cirrus Logic, Inc. www.cirrus.com CS4272 24-Bit, 192 kHz Stereo Audio CODEC D/A Features !High Performance – 114 dB Dynamic Range – -100 dB THD+N !Up to 192 kHz Sampling Rates !Differential Analog Architecture !Volume Control with Soft Ramp – 1 dB Step Size – Zero Crossing Click-free Transitions !Selectable Digital Filters – Fast and Slow Roll Off !ATAPI Mixing Functions !Selectable Serial Audio Interface Formats – Left Justified up to 24-bit – I2S up to 24-bit – Right Justified 16-, 18-, 20-, and 24-Bit !Control Output for External Muting !Selectable 50/15 µs De-emphasis A/D Features !High Performance – 114 dB Dynamic Range – -100 dB THD+N !Up to 192 kHz Sampling Rates !Differential Analog Architecture !Multi-bit Delta Sigma Conversion !High-pass Filter or DC Offset Calibration !Low-Latency Digital Anti-alias Filtering !Automatic Dithering of 16-bit Data !Selectable Serial Audio Interface Formats – Left Justified up to 24-bit – I2S up to 24-bit System Features !Direct Interface with 5V to 2.5V Logic Levels !Internal Digital Loopback !On-chip Oscillator !Stand-Alone or Control Port Functionality

2.5 V to 5 V

∆Σ Modulator ∆Σ Modulator Low-Latency Anti-Alias Filter External Mute Control Register / Hardware Configuration Internal Voltage Reference Internal Oscillator Volume Control Mixer Selectable Interpolation Filter Selectable Interpolation Filter Reset Left Differential Output Right Differential Output Switched Capacitor DAC and Filter Multibit Oversampling ADC Multibit Oversampling ADC Low-Latency Anti-Alias Filter High Pass Filter & DC Offset Calibration High Pass Filter & DC Offset Calibration PCM Serial Interface / Loopback Left Differential Input Right Differential Input Volume Control Level Translator Level Translator Serial Audio Input Serial Audio Output

3.3 V to 5 V

AUGUST '05 DS593F1

Stand-Alone Mode Feature Set !System Features – Serial Audio Port Master or Slave Operation – Internal Oscillator for Master Clock !D/A Features – Auto-mute on Static Samples – 44.1 kHz 50/15 µs De-emphasis Available – Selectable Serial Audio Interface Formats "Left Justified up to 24-bit "I2S up to 24-bit !A/D Features – Automatic Dithering for 16-bit Data – High-pass Filter – Selectable Serial Audio Interface Formats "Left Justified up to 24-bit "I2S up to 24-bit Software Mode Feature Set !System Features – Serial Audio Port Master or Slave Operation – Internal Oscillator for Master Clock – Internal Digital Loopback Available !D/A Features – Selectable Auto-mute – Selectable Interpolation Filters – Selectable 32-, 44.1-, and 48-kHz De-emphasis Filters – Configurable ATAPI Mixing Functions – Configurable Volume and Muting Controls – Selectable Serial Audio Interface Formats "Left Justified up to 24-bit "I2S up to 24-bit "Right Justified 16, 18, 20, and 24-bit !A/D Features – Selectable Dithering for 16-bit Data – Selectable High-pass Filter or DC Offset Calibration – Selectable Serial Audio Interface Formats "Left Justified up to 24-bit "I2S up to 24-bit General Description The CS4272 is a high-performance, integrated audio CODEC. The CS4272 performs stereo analog-to-digital (A/D) and digital-to-analog (D/A) conversion of up to 24-bit serial values at sample rates up to 192 kHz. The D/A offers a volume control that operates with a 1 dB step size. It incorporates selectable soft ramp and zero crossing transition functions to eliminate clicks and pops. The D/A’s integrated digital mixing functions allow a va- riety of output configurations ranging from a channel swap to a stereo-to-mono downmix. Standard 50/15 µs de-emphasis is available for sam- pling rates of 32, 44.1, and 48 kHz for compatibility with digital audio programs mastered using the 50/15 µs pre- emphasis technique. Integrated level translators allow easy interfacing be- tween the CS4272 and other devices operating over a wide range of logic levels. An on-chip oscillator eliminates the need for an external crystal oscillator circuit. This can reduce overall design cost and conserve circuit board space. The CS4272 au- tomatically uses the on-chip oscillator in the absence of an applied master clock, making this feature easy to use. Independently addressable high-pass filters are avail- able for the right and left channel of the A/D. This allows the A/D to be used in a wide variety of applications where one audio channel and one DC measurement channel is desired. The CS4272’s wide dynamic range, negligible distor- tion, and low noise make it ideal for applications such as A/V receivers, DVD-R, CD-R, digital mixing consoles, effects processors, set-top box systems, and automo- tive audio systems.

Ordering Information

Description

Order # CS4272 24-Bit, 192 kHz Stereo Audio CODEC 28-pin TSSOP YES Commercial -10° to +70° C Tube CS4272-CZZ Tape & Reel CS4272-CZZR Automotive -40° to +85° C Tube CS4272-DZZ Tape & Reel CS4272-DZZR CDB4272 CS4272 Evaluation Board No CDB4272

PIN DESCRIPTIONS - SOFTWARE MODE XTO BMUTEC XTI AOUTB- MCLK AOUTB+ LRCK AOUTA+ SCLK AOUTA- SDOUT AMUTEC SDIN FILT+ DGND AGND VD VA VL AINB- SCL/CCLK AINB+ SDA/CDIN AINA+ AD0/CS AINA- RST VCOM 28-Pin TSSOP

1,2 Crystal Connections (Input/Output) - I/O pins for an external crystal which may be used to generate MCLK. See “Crystal Applications (XTI/XTO)” on page 24 or “Crystal Applications (XTI/XTO)” on page 27. MCLK Master Clock (Input/Output) -Clock source for the delta-sigma modulators. See “Crystal Applications (XTI/XTO)” on page 24 or “Crystal Applications (XTI/XTO)” on page 27. LRCK Left Right Clock (Input/Output) - Determines which channel, Left or Right, is currently active on the serial audio data line. SCLK Serial Clock (Input/Output) - Serial clock for the serial audio interface. SDOUT Serial Audio Data Output (Output) - Output for two’s complement serial audio data. SDIN Serial Audio Data Input (Input) - Input for two’s complement serial audio data. DGND Digital Ground (Input) - Ground reference for the internal digital section. VD Digital Power (Input) - Positive power for the internal digital section. VL Logic Power (Input) - Positive power for the digital input/output interface. SCL/CCLK Serial Control Port Clock (Input) - Serial clock for the serial control port. SDA/CDIN Serial Control Data (Input/Output) - SDA is a data I/O in I²C mode. CDIN is the input data line for the control port interface in SPI mode. AD0/CS Address Bit 0 (I²C) / Control Port Chip Select (SPI) (Input) - AD0 is a chip address pin in I²C mode; CS is the chip select signal for SPI format. RST Reset (Input) - The device enters a low power mode when this pin is driven low. VCOM Common Mode Voltage (Output) - Filter connection for internal common mode voltage. AINA- AINA+ AINB+ AINB- 16, 17, 18, Differential Analog Input (Input) - The full scale differential input signals are presented to the delta- sigma modulators. The full scale level is specified in the ADC Analog Characteristics specification table. VA Analog Power (Input) - Positive power for the internal analog section. AGND Analog Ground (Input) - Ground reference for the internal analog section. FILT+ Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling circuits. AMUTEC Channel A Mute Control (Output) - This pin is active during power-up initialization, reset, muting, when master clock to left/right clock frequency ratio is incorrect, or power-down. AOUTA- AOUTA+ AOUTB+ AOUTB- 24, 25, 26, Differential Analog Audio Output (Output) - The full scale differential output level is specified in the DAC Analog Characteristics specification table. BMUTEC Channel B Mute Control (Output) - This pin is active during power-up initialization, reset, muting, when master clock to left/right clock frequency ratio is incorrect, or power-down.

PIN DESCRIPTIONS - STAND-ALONE MODE XTO BMUTEC XTI AOUTB- MCLK AOUTB+ LRCK AOUTA+ SCLK AOUTA- SDOUT (M/S) AMUTEC SDIN FILT+ DGND AGND VD VA VL AINB- AINB+ AINA+ I2S/LJ AINA- RST VCOM 28-Pin TSSOP

1,2 Crystal Connections (Input/Output) - I/O pins for an external crystal which may be used to generate the master clock. See “Crystal Applications (XTI/XTO)” on page 24 or “Crystal Applications (XTI/XTO)” on page 27. MCLK Master Clock (Input/Output) -Clock source for the delta-sigma modulators. See “Crystal Applications (XTI/XTO)” on page 24 or “Crystal Applications (XTI/XTO)” on page 27. LRCK Left Right Clock (Input/Output) - Determines which channel, Left or Right, is currently active on the serial audio data line. SCLK Serial Clock (Input/Output) - Serial clock for the serial audio interface. SDOUT (M/S) Serial Audio Data Output (Output) - Output for two’s complement serial audio data. This pin must be pulled-up or pulled-down to select Master or Slave Mode. See “Master/Slave Mode” on page 24. SDIN Serial Audio Data Input (Input) - Input for two’s complement serial audio data. DGND Digital Ground (Input) - Ground reference for the internal digital section. VD Digital Power (Input) - Positive power for the internal digital section. VL Logic Power (Input) - Positive power for the digital input/output interface. Mode Select 0 (Input) - In conjunction with M1, selects operating mode. Functionality is described in the Hardware Mode Speed Configuration table. Mode Select 1 (Input) - In conjunction with M0, selects operating mode. Functionality is described in the Hardware Mode Speed Configuration table. I2S/LJ Serial Audio Interface Select (Input) - Selects either the left-justified or I2S format for the Serial Audio Interface. RST Reset (Input) - The device enters a low power mode when this pin is driven low. VCOM Common Mode Voltage (Output) - Filter connection for internal common mode voltage. AINA- AINA+ AINB+ AINB- 16, 17, 18, Differential Analog Input (Input) - The full scale differential input signals are presented to the delta- sigma modulators. The full scale level is specified in the ADC Analog Characteristics specification table. VA Analog Power (Input) - Positive power for the internal analog section. AGND Analog Ground (Input) - Ground reference for the internal analog section. FILT+ Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling circuits. AMUTEC Channel A Mute Control (Output) - This pin is active during power-up initialization, reset, muting, when master clock to left/right clock frequency ratio is incorrect, or power-down. AOUTA- AOUTA+ AOUTB+ AOUTB- 24, 25, 26, Differential Analog Audio Output (Output) - The full scale differential output level is specified in the Analog Characteristics specification table. BMUTEC Channel B Mute Control (Output) - This pin is active during power-up initialization, reset, muting, when master clock to left/right clock frequency ratio is incorrect, or power-down.

CHARACTERISTICS AND SPECIFICATIONS (All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical performance characteristics and specifications are derived from measurements taken at nominal supply voltages and TA = 25°C.) SPECIFIED OPERATING CONDITIONS (AGND = 0 V; all voltages with respect to ground.) ABSOLUTE MAXIMUM RATINGS (GND = 0 V, All voltages with respect to ground.) (Note 1) Notes: Operation beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. Any pin except supplies. Transient currents of up to ±100 mA on the analog input pins will not cause SCR latch-up. Parameters Symbol Min Nom Max Units DC Power Supplies: Positive Analog Positive Digital Positive Logic VA VD VL 4.75 3.1 2.37 5.0 3.3 3.3 5.25 5.25 5.25 V V V Ambient Operating Temperature (Power Applied) Commercial Grade Automotive Grade TA -10 -40 +70 +85 Parameter Symbol Min Typ Max Units DC Power Supplies: Analog Logic Digital VA VL VD -0.3 -0.3 -0.3 +6.0 +6.0 +6.0 V V V Input Current (Note 2) Iin ±10 mA Analog Input Voltage VIN GND-0.3 VA+0.3 V Digital Input Voltage VIND -0.3 VL+0.3 V Ambient Operating Temperature (Power Applied) TA -50 +95 Storage Temperature Tstg -65 +150

DAC ANALOG CHARACTERISTICS - COMMERCIAL GRADE (Notes 3 to 7) Notes: One-half LSB of Triangular PDF dither is added to data. Performance measurements taken with a full-scale 997 Hz sine wave under Test load RL = 3 kΩ, CL = 10 pF Measurement bandwidth is 10 Hz to 20 kHz. Logic “0” = GND = 0V; Logic “1” = VL; VL = VA unless otherwise noted. VFS is tested under load RL but does not include attenuation due to ZOUT Parameter Symbol Min Typ Max Unit Dynamic Performance Dynamic Range 24-Bits A-Weighted unweighted 16-Bits unweighted 108 105 114 111 dB dB dB Total Harmonic Distortion + Noise 0 dB -20 dB -60 dB THD+N -100 -91 -51 -94 -45 dB dB dB Idle Channel Noise / Signal-to-Noise Ratio 114 dB Interchannel Isolation (1 kHz) 100 dB DC Accuracy Interchannel Gain Mismatch ICGM 0.1 dB Gain Drift 100 ppm/°C Analog Output Characteristics and Specifications Full Scale Differential Output Voltage VFS 0.91xVA 0.96xVA 1.01xVA Vpp Output Resistance (note 7) Zout 100 Ω Minimum AC-Load Resistance RL kΩ Maximum Load Capacitance CL 100 pF

DAC ANALOG CHARACTERISTICS - AUTOMOTIVE GRADE (Notes 3 to 7) Parameter Symbol Min Typ Max Unit Dynamic Performance Dynamic Range 24-Bits A-Weighted unweighted 16-Bits unweighted 106 103 114 111 dB dB dB Total Harmonic Distortion + Noise 0 dB -20 dB -60 dB THD+N -100 -91 -51 -92 -43 dB dB dB Idle Channel Noise / Signal-to-Noise Ratio 114 dB Interchannel Isolation (1 kHz) 100 dB DC Accuracy Interchannel Gain Mismatch ICGM 0.1 dB Gain Drift 100 ppm/°C Analog Output Characteristics and Specifications Full Scale Differential Output Voltage VFS 0.91xVA 0.96xVA 1.01xVA Vpp Output Resistance (note 7) Zout 100 Ω Minimum AC-Load Resistance RL kΩ Maximum Load Capacitance CL 100 pF

DAC COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE (Note 12) Parameter Fast Roll-Off Unit Min Typ Max Single Speed Mode - 48 kHz Passband (Note 9) to -0.01 dB corner to -3 dB corner .454 .499 Fs Fs Frequency Response 10 Hz to 20 kHz -0.01 +0.01 dB StopBand .547 Fs StopBand Attenuation (Note 10) dB Group Delay 12/Fs s De-emphasis Error (Note 11) Fs = 32 kHz (Relative to 1kHz) Fs = 44.1 kHz Fs = 48 kHz ±0.23 ±0.14 ±0.09 dB dB dB Double Speed Mode - 96 kHz Passband (Note 9) to -0.01 dB corner to -3 dB corner .430 .499 Fs Fs Frequency Response 10 Hz to 20 kHz -0.01 0.01 dB StopBand .583 Fs StopBand Attenuation (Note 10) dB Group Delay 4.6/Fs s Quad Speed Mode - 192 kHz Passband (Note 9) to -0.01 dB corner to -3 dB corner .105 .490 Fs Fs Frequency Response 10 Hz to 20 kHz -0.01 0.01 dB StopBand .635 Fs StopBand Attenuation (Note 10) dB Group Delay 4.7/Fs s

DAC COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE (cont) (Note 12) Notes: Slow Roll-Off interpolation filter is only available in control port mode. Response is clock dependent and will scale with Fs. Note that the response plots (Figures 21 to 44) have been normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs. 10. Single and Double Speed Mode Measurement Bandwidth is from stopband to 3 Fs. Quad Speed Mode Measurement Bandwidth is from stopband to 1.34 Fs. 11. De-emphasis is available only in Single Speed Mode; Only 44.1 kHz De-emphasis is available in Stand- Alone Mode. 12. Plots of this data are contained in the “Appendix” on page 47. See Figure 21 through Figure 44. Parameter Slow Roll-Off (Note 8) Unit Min Typ Max Single Speed Mode - 48 kHz Passband (Note 9) to -0.01 dB corner to -3 dB corner 0.417 0.499 Fs Fs Frequency Response 10 Hz to 20 kHz -0.01 +0.01 dB StopBand .583 Fs StopBand Attenuation (Note 10) dB Group Delay 6.5/Fs s De-emphasis Error (Note 11) Fs = 32 kHz (Relative to 1 kHz) Fs = 44.1 kHz Fs = 48 kHz ±0.23 ±0.14 ±0.09 dB dB dB Double Speed Mode - 96 kHz Passband (Note 9) to -0.01 dB corner to -3 dB corner .296 .499 Fs Fs Frequency Response 10 Hz to 20 kHz -0.01 0.01 dB StopBand .792 Fs StopBand Attenuation (Note 10) dB Group Delay 3.9/Fs s Quad Speed Mode - 192 kHz Passband (Note 9) to -0.01 dB corner to -3 dB corner .104 .481 Fs Fs Frequency Response 10 Hz to 20 kHz -0.01 0.01 dB StopBand .868 Fs StopBand Attenuation (Note 10) dB Group Delay 4.2/Fs s

ADC ANALOG CHARACTERISTICS - COMMERCIAL GRADE Measurement Bandwidth is 10 Hz to 20 kHz unless otherwise specified. Input is 1 kHz sine wave. Notes: 13. Referred to the typical full-scale input voltage. Notes: 14. Measured between AIN+ and AIN- Parameter Symbol Min Typ Max Unit Single Speed Mode Fs = 48 kHz Dynamic Range A-weighted unweighted 108 105 114 111 dB dB Total Harmonic Distortion + Noise (Note 13) -1 dB -20 dB -60 dB THD+N -100 -91 -51 -94 dB dB dB Double Speed Mode Fs = 96 kHz Dynamic Range A-weighted unweighted 40 kHz bandwidth unweighted 108 105 114 111 108 dB dB dB Total Harmonic Distortion + Noise (Note 13) -1 dB -20 dB -60 dB 40 kHz bandwidth -1 dB THD+N -100 -91 -51 -97 -94 dB dB dB dB Quad Speed Mode Fs = 192 kHz Dynamic Range A-weighted unweighted 40 kHz bandwidth unweighted 108 105 114 111 108 dB dB dB Total Harmonic Distortion + Noise (Note 13) -1 dB -20 dB -60 dB 40 kHz bandwidth -1 dB THD+N -100 -91 -51 -97 -94 dB dB dB dB Dynamic Performance for All Modes Interchannel Isolation 110 dB Interchannel Phase Deviation 0.0001 Degree DC Accuracy Interchannel Gain Mismatch 0.1 dB Gain Error Gain Drift ±100 ppm/°C Offset Error HPF enabled HPF disabled 100 LSB LSB Analog Input Characteristics Full-scale Input Voltage 1.07xVA 1.13xVA 1.19xVA Vpp Input Impedance (Differential) (Note 14) kΩ Common Mode Rejection Ratio CMRR dB

ADC ANALOG CHARACTERISTICS - AUTOMOTIVE GRADE Measurement Bandwidth is 10 Hz to 20 kHz unless otherwise specified. Input is 1 kHz sine wave.) Notes: 15. Referred to the typical full-scale input voltage. Notes: 16. Measured between AIN+ and AIN- Parameter Symbol Min Typ Max Unit Single Speed Mode Fs = 48 kHz Dynamic Range A-weighted unweighted 106 103 114 111 dB dB Total Harmonic Distortion + Noise (Note 15) -1 dB -20 dB -60 dB THD+N -100 -91 -51 -92 dB dB dB Double Speed Mode Fs = 96 kHz Dynamic Range A-weighted unweighted 40 kHz bandwidth unweighted 106 103 114 111 108 dB dB dB Total Harmonic Distortion + Noise (Note 15) -1 dB -20 dB -60 dB 40 kHz bandwidth -1 dB THD+N -100 -91 -51 -97 -92 dB dB dB dB Quad Speed Mode Fs = 192 kHz Dynamic Range A-weighted unweighted 40 kHz bandwidth unweighted 106 103 114 111 108 dB dB dB Total Harmonic Distortion + Noise (Note 15) -1 dB -20 dB -60 dB 40 kHz bandwidth -1 dB THD+N -100 -91 -51 -97 -92 dB dB dB dB Dynamic Performance for All Modes Interchannel Isolation 110 dB Interchannel Phase Deviation 0.0001 Degree DC Accuracy Interchannel Gain Mismatch 0.1 dB Gain Error Gain Drift ±100 ppm/°C Offset Error HPF enabled HPF disabled 100 LSB LSB Analog Input Characteristics Full-scale Input Voltage 1.07xVA 1.13xVA 1.19xVA Vpp Input Impedance (Differential) (Note 16) kΩ Common Mode Rejection Ratio CMRR dB

ADC DIGITAL FILTER CHARACTERISTICS (Note 19) Notes: 17. The filter frequency response scales precisely with Fs. 18. Response shown is for Fs equal to 48 kHz. Filter characteristics scale with Fs. 19. Plots of this data are contained in the “Appendix” on page 47. See Figure 45 through Figure 56. Parameter Symbol Min Typ Max Unit Single Speed Mode Passband (-0.1 dB). (Note 17) 0.47 Fs Passband Ripple. ±0.035 dB Stopband. (Note 17) 0.58 Fs Stopband Attenuation. -95 dB Group Delay. tgd 12/Fs s Double Speed Mode Passband (-0.1 dB). (Note 17) 0.45 Fs Passband Ripple. ±0.035 dB Stopband. (Note 17) 0.68 Fs Stopband Attenuation. -92 dB Group Delay. tgd 9/Fs s Quad Speed Mode Passband (-0.1 dB). (Note 17) 0.24 Fs Passband Ripple. ±0.035 dB Stopband. (Note 17) 0.78 Fs Stopband Attenuation. -97 dB Group Delay. tgd 5/Fs s High Pass Filter Characteristics Frequency Response -3.0 dB. -0.13 dB. (Note 18) Hz Hz Phase Deviation @ 20 Hz. (Note 18) Deg Passband Ripple. dB Filter Settling Time. 105/Fs s

DC ELECTRICAL CHARACTERISTICS (GND = 0 V, all voltages with respect to ground. MCLK=12.288 MHz; Master Mode) Notes: 20. Power Down Mode is defined as RST = Low with all clocks and data lines held static. 21. Valid with the recommended capacitor values on FILT+ and VCOM as shown in the Typical Connection Diagram. DIGITAL CHARACTERISTICS Parameter Symbol Min Typ Max Unit Power Supply Power Supply Current VA (Normal Operation) VL,VD = 5 V VL,VD = 3.3 V IA ID ID 41.5 mA mA mA Power Supply Current VA (Power-Down Mode)(Note 20) VL,VD=5 V IA ID 0.025 1.76 mA mA Power Consumption VL, VD=5 V (Normal Operation) VL, VD = 3.3 V (Power-Down Mode) 433 305 510 358 mW mW mW Power Supply Rejection Ratio (1 kHz) (Note 21) PSRR dB Common Mode Nominal Common Mode Voltage VCOM 0.48xVA VDC Maximum DC Current Source/Sink from VCOM µA VCOM Output Impedance kΩ FILT+ FILT+ Nominal Voltage FILT+ VA VDC MUTEC MUTEC Low-Level Output Voltage V MUTEC High-Level Output Voltage VA V Maximum MUTEC Drive Current mA Parameter Symbol Min Typ Max Units High-Level Input Voltage (% of VL) VIH 70% V Low-Level Input Voltage (% of VL) VIL 30% V High-Level Output Voltage at Io = 2 mA VOH VL - 1.0 V Low-Level Output Voltage at Io = 2 mA VOL 0.4 V Input Leakage Current Iin ±10 µA

SWITCHING CHARACTERISTICS - SERIAL AUDIO PORT (Logic "0" = GND = 0 V; Logic "1" = VL, CL = 20 pF) Notes: 22. In Control Port Mode, the Ratio[1:0] bits must be configured according to tables 8 and 9 on pages 28 and 29. Parameter Symbol Min Typ Max Unit Sample Rate Single Speed Mode Double Speed Mode Quad Speed Mode Fs Fs Fs 100 100 200 kHz kHz kHz MCLK Specifications MCLK Frequency Stand-Alone Mode (note 22) Control Port Mode fmclk fmclk 1.024 1.024 25.600 51.200 MHz MHz MCLK Input Pulse Width High/Low Stand-Alone Mode (note 22) Control Port Mode tclkhl tclkhl ns ns MCLK Output Duty Cycle Master Mode LRCK Duty Cycle SCLK Duty Cycle SCLK falling to LRCK edge tslr -10 ns SCLK falling to SDOUT valid tsdo ns SDIN valid to SCLK rising setup time tsdis ns SCLK rising to SDIN hold time tsdih ns Slave Mode LRCK Duty Cycle SCLK Period (note 22) Single Speed Mode Double Speed Mode Quad Speed Mode tsclkw tsclkw tsclkw s s s SCLK Pulse Width High tsclkh ns SCLK Pulse Width Low tsclkl ns SCLK falling to LRCK edge tslr -10 ns SCLK falling to SDOUT valid tsdo ns SDIN valid to SCLK rising setup time tsdis ns SCLK rising to SDIN hold time tsdih ns Crystal Oscillator Specifications (XTI/XTO) Crystal Frequency Range fosc 16.384 25.600 MHz 128 )Fs 128 )Fs )Fs

Data must be held for sufficient time to bridge the 300 ns transition time of SCL. Bus Free Time Between Transmissions. Start Condition Hold Time (prior to first clock pulse). Setup Time for Repeated Start Condition. SDA Hold Time from SCL Falling. SDA Setup time to SCL Rising. Rise Time of Both SDA and SCL Lines. Fall Time of Both SDA and SCL Lines. Setup Time for Stop Condition. Figure 6. I²C Mode Control Port Timing

tspi only needed before first falling edge of CS after RST rising edge. tspi = 0 at all other times. Data must be held for sufficient time to bridge the transition time of CCLK. RST Rising Edge to CS Falling. CS High Time Between Transmissions. CDIN to CCLK Rising Setup Time. CCLK Rising to DATA Hold Time. Figure 7. SPI Control Port Timing

¤ See "Master/Slave Mode Selection". Figure 8. CS4272 Typical Connection Diagram

stable. When using the CS4272 with internally generated MCLK, hold RST low until the power supply is stable. The CS4272 supports operation in either Master Mode or Slave Mode. mended that SCLK be 64x Fs to maximize system performance. pull-up to VL on the SDOUT (M/S) pin. Configuration of clock ratios in each of these modes will be outlined in the Tables 3 and 4. modes as shown in Table 1 below. shown in the Typical Connection Diagram on page 23. This crystal must oscillate at the frequency shown in Table 2. MCLK pin prior to 1 ms from the release of RST. externally with an appropriate speed clock. Table 1. Speed Modes Table 2. Crystal Frequencies

MCKL/LRCK and SCLK/LRCK ratios may be used. These ratios are shown in the Tables 3 and 4 below. Table 3. Clock Ratios - Stand Alone Mode With External Crystal Table 4. Clock Ratios - Stand Alone Mode Without External Crystal

applies only to the serial audio output of the ADC and will not affect DAC performance. See Figure 9. The operational amplifiers in the input circuitry driving the CS4272 may generate a small DC offset into the ADC. a DC level, possibly yielding "clicks" when switching between devices in a multichannel system. decimation filter. This function cannot be disabled in Stand-Alone Mode. In Stand-Alone Mode, the fast roll-off interpolation filter is used. Filter specifications can be found in Section 3. Plots of the data are contained in the “Appendix” on page 47. placing a 10 kΩ pull-down to DGND on the I2S/LJ pin will select the left justified format. Table 5. CS4272 Stand-Alone Mode Control Figure 9. ADC 16-Bit Auto-Dither

stable. When using the CS4272 with internally generated MCLK, hold RST low until the power supply is stable. In this state, the Control Port is reset to its default settings. generated MCLK is being used, it will appear on the MCLK pin prior to 1 ms from the release of RST. ating this Control Port write. The desired register settings can be loaded while keeping the PDN bit set. Clear the PDN bit to initiate the power-up sequence. This power-up sequence requires approximately 85 µS. The CS4272 supports operation in either Master Mode or Slave Mode. mended that SCLK be 64x Fs to maximize system performance. Configuration of clock ratios in each of these modes will be outlined in the Tables 8 and 9. the status of the M/S bit in the Mode Control 1 register (01h). modes as shown in Table 6 below. prior to 1 ms from the release of RST. Table 6. Speed Modes

externally with an appropriate speed clock. be set in order to obtain them are shown in Tables 8 and 9 below. For the Ratio1 and Ratio0 bits listed above, “d” indicates that any value may written. Table 7. Crystal Frequencies Table 8. Clock Ratios - Control Port Mode With External Crystal

For the Ratio0 bit listed above, “d” indicates that any value may written. Table 9. Clock Ratios - Control Port Mode Without External Crystal

ed to the input of the DAC. This mode may be activated by setting the LOOP bit in the Mode Control 2 register (07h). the ADC_DIF bit in register 06h. devices are downstream of the ADC. This bit should not be set when using word lengths greater than 16 bits. on the output will be retained and the Mute Control pin for that channel will become active during the mute period. ume and Mixing Control register. The AMUTE bit is set by default. recording a DC level, possibly yielding "clicks" when switching between devices in a multichannel system. Disabling the high pass filter and freezing the stored DC offset. Figure 10. Example of Dither for 16-Bit Data with 24-Bit Left Justified Format

roll-off filter is selected. Filter specifications can be found in Section 3. Plots of the data are contained in the “Appendix” on page 47. 44.1 kHz, and 48 kHz sampling rates. See Table 13 for de-emphasis selection in Control Port Mode.

5.2.10 Oversampling Modes

sampling ratio of 32x. See Table 11 for Control Port Mode settings. The CS4272 includes on-chip digital de-emphasis. Figure 11 shows the de-emphasis curve for Fs equal to 44.1 kHz. ization as a means of noise reduction. De-emphasis is only available in Single Speed Mode. Figure 11. De-Emphasis Curve

low. See Figure 16 below for a suggested active-low mute circuit. begin sampling on the same clock edge. nect the CS4272 digital outputs only to CMOS inputs. Figure 16. Suggested Active-Low Mute Circuit

be output after the chip address. lowing block reads or writes of successive registers. Table 10. Memory Address Pointer (MAP) Note: If operation is a write, this byte contains the Memory Address Pointer, MAP. Figure 18. Control Port Timing, I²C Mode

1. REGISTER QUICK REFERENCE This table shows the register names and their associated default values. Addr Function 01h Mode Control 1 Ratio1 Ratio0 M/S DAC_DIF2 DAC_DIF1 DAC_DIF0 02h DAC Control AMUTE FILT_SEL DEM1 DEM0 RMP_UP RMP_DN INV_B INV_A 03h DAC Volume & Mixing Control Reserved B=A Soft ZeroCross ATAPI3 ATAPI2 ATAPI1 ATAPI0 04h DAC Ch A Vol- ume Control MUTE VOL6 VOL5 VOL4 VOL3 VOL2 VOL1 VOL0 05h DAC Ch B Vol- ume Control MUTE VOL6 VOL5 VOL4 VOL3 VOL2 VOL1 VOL0 06h ADC Control Reserved Reserved Dither16 ADC_DIF0 MUTEA MUTEB HPFDisableA HPFDisableB 07h Mode Control 2 Reserved Reserved Reserved LOOP MUTECA=B FREEZE CPEN PDN 08h Chip ID PART3 PART2 PART1 PART0 REV3 REV2 REV1 REV0

All registers are read/write in I²C mode and write only in SPI mode, unless otherwise noted 8.1 Mode Control 1 - Address 01h 8.1.1 Functional Mode (Bits 7:6) Function: Selects the required range of input sample rates. 8.1.2 Ratio Select (Bits 5:4) Function: These bits are used to select the clocking ratios in Control Port Mode. Please refer to Table 8, “Clock Ratios - Control Port Mode With External Crystal,” on page 28 or Table 9, “Clock Ratios - Control Port Mode Without External Crystal,” on page 29 for information on which of these bits to set to obtain spe- cific clock ratios. 8.1.3 Master / Slave Mode (Bit 3) Function: This bit selects either master or slave operation. Setting this bit will select master mode, while clearing this bit will select slave mode. 8.1.4 DAC Digital Interface Format (Bits 2:0) Function: The required relationship between LRCK, SCLK and SDIN for the DAC is defined by the DAC Digital Interface Format and the options are detailed in Table 12 and Figures 3-5. Ratio1 Ratio0 M/S DAC_DIF2 DAC_DIF1 DAC_DIF0 Table 11. Functional Mode Selection Table 12. DAC Digital Interface Formats Left Justified, up to 24-bit data (default) I2S, up to 24-bit data Right Justified, 16-bit Data Right Justified, 24-bit Data Right Justified, 20-bit Data Right Justified, 18-bit Data Reserved Reserved

8.2 DAC Control - Address 02h 8.2.1 Auto-Mute (Bit 7) Function: When set, enables the Auto-Mute function. See “Auto-Mute” on page 30. 8.2.2 Interpolation Filter Select (Bit 6) Function: This Function allows the user to select whether the Interpolation Filter has a fast or slow roll off. When set, this bit selects the slow roll off filter, when cleared it selects the fast roll off filter. The - 3 dB corner is approximately the same for both filters, but the slope of the roll off is greater for the fast roll off filter. 8.2.3 De-Emphasis Control (Bits 5:4) Function: Implementation of the standard 50/15 µs digital de-emphasis filter response, Figure 19, requires re- configuration of the digital filter to maintain the proper filter response for 32, 44.1 or 48 kHz sample rates. NOTE: De-emphasis is available only in Single-Speed Mode. See Table 13 below. AMUTE FILT_SEL DEM1 DEM0 RMP_UP RMP_DN INV_A INV_B Table 13. De-Emphasis Mode Selection Disabled (default) 44.1 kHz de-emphasis 48 kHz de-emphasis 32 kHz de-emphasis Gain dB -10dB 0dB Frequency T2 = 15 µs T1=50 µs 3.183 kHz 10.61 kHz Figure 19. De-Emphasis Curve

8.2.4 Soft Volume Ramp-Up After Error (Bit 3) Function: An un-mute will be performed after executing a filter mode change, after a MCLK/LRCK ratio change or error, and after changing the Functional Mode. When this bit is set, this un-mute is effected, similar to attenuation changes, by the Soft and ZeroCross bits in the DAC Volume & Mixing Control register. When cleared, an immediate un-mute is performed in these instances. Note: For best results, it is recommended that this feature be used with the RMP_DN bit. 8.2.5 Soft Ramp-Down Before Filter Mode Change (Bit 2) Function: A mute will be performed prior to executing a filter mode change. When this bit is set, this mute is effected, similar to attenuation changes, by the Soft and ZeroCross bits in the DAC Volume & Mixing Control register. When cleared, an immediate mute is performed prior to executing a filter mode change. Note: For best results, it is recommended that this feature be used in conjunction with the RMP_UP bit. 8.2.6 Invert Signal Polarity (Bits 1:0) Function: When set, this bit activates an inversion of the signal polarity for the appropriate channel. This is use- ful if a board layout error has occurred, or other situations where a 180 degree phase shift is desirable. 8.3 DAC Volume & Mixing Control - Address 03h 8.3.1 Channel B Volume = Channel A Volume (Bit 6) Function: The AOUTA and AOUTB volume levels are independently controlled by the A and the B Channel Vol- ume Control Bytes when this function is disabled. The volume on both AOUTA and AOUTB are de- termined by the A Channel Volume Control Byte and the B Channel Byte is ignored when this function is enabled. Volume and muting functions are effected by the Soft Ramp and ZeroCross functions be- low. 8.3.2 Soft Ramp or Zero Cross Enable (Bits 5:4) Function: Soft Ramp Enable Soft Ramp allows level changes, both muting and attenuation, to be implemented by incrementally ramping, in 1/8 dB steps, from the current level to the new level at a rate of 1 dB per 8 left/right clock periods. See Table 14 on page 41. Zero Cross Enable Zero Cross Enable dictates that signal level changes, either by attenuation changes or muting, will occur on a signal zero crossing to minimize audible artifacts. The requested level change will occur after a time-out period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample rate) if the signal does not encounter a zero crossing. The zero cross function is independently mon- Reserved B=A Soft ZeroCross ATAPI3 ATAPI2 ATAPI1 ATAPI0

itored and implemented for each channel. See Table 14 on page 41. independently monitored and implemented for each channel. See Table 14 on page 41. Table 14. Soft Cross or Zero Cross Mode Selection Figure 20. ATAPI Block Diagram

active if either MUTE register is enabled and the MUTECB=A bit (register 7) is enabled. The digital volume control allows the user to attenuate the signal in 1 dB increments from 0 to -127 dB. ed by the Soft and ZeroCross bits in the DAC Volume & Mixing Control register (see section 8.3.2). Table 15. ATAPI Decode Table 16. Digital Volume Control Example Settings

8.6 ADC Control - Address 06h 8.6.1 Dither for 16-Bit Data (Bit 5) Function: When set, this bit activates the Dither for 16-Bit Data feature as described in “Dither for 16-Bit Data” on page 30. 8.6.2 ADC Digital Interface Format (Bit 4) Function: The required relationship between LRCK, SCLK and SDOUT for the ADC is defined by the ADC Dig- ital Interface Format. The options are detailed in Table 17 and may be seen in Figure 3 and 4. 8.6.3 ADC Channel A & B Mute (Bits 3:2) Function: When this bit is set, the output of the ADC for the selected channel will be muted. 8.6.4 Channel A & B High Pass Filter Disable (Bits 1:0) Function: When this bit is set, the internal high-pass filter for the selected channel will be disabled.The current DC offset value will be frozen and continue to be subtracted from the conversion result. See “High Pass Filter and DC Offset Calibration” on page 30. 8.7 Mode Control 2 - Address 07h 8.7.1 Digital Loopback (Bit 4) Function: When this bit is set, an internal digital loopback from the ADC to the DAC will be enabled. Please refer to “Internal Digital Loopback” on page 30. 8.7.2 AMUTEC = BMUTEC (Bit 3) Function: When this function is enabled, the individual controls for AMUTEC and BMUTEC are internally con- nected through an AND gate prior to the output pins. Therefore, the external AMUTEC and BMUTEC pins will go active only when the requirements for both AMUTEC and BMUTEC are valid. Reserved Reserved Dither16 ADC_DIF MUTEA MUTEB HPFDisableA HPFDisableB Table 17. ADC Digital Interface Formats Left Justified, up to 24-bit data (default) I2S, up to 24-bit data Reserved Reserved Reserved LOOP MUTECA=B FREEZE CPEN PDN

8.7.3 Freeze (Bit 2) Function: This function allows modifications to the control port registers without the changes taking effect until FREEZE is disabled. To make multiple changes in the Control Port registers take effect simultaneous- ly, set the FREEZE bit, make all register changes, then clear the FREEZE bit. 8.7.4 Control Port Enable (Bit 1) Function: This bit is cleared by default, allowing the device to power-up in Stand-Alone Mode. Control Port Mode can be accessed by setting this bit. This will allow the operation of the device to be controlled by the registers and the pin definitions will conform to Control Port Mode. See “Recommended Power- Up Sequence - Access to Control Port Mode” on page 27. 8.7.5 Power Down (Bit 0) Function: The device will enter a low-power state whenever this bit is set. The power-down bit is set by default and must be cleared before normal operation in Control Port Mode can occur. The contents of the control registers are retained when the device is in power-down. 8.8 Chip ID - Register 08h This is a Read-Only register. 8.8.1 Chip ID (Bits 7:4) Function: Chip ID code for the CS4272. Permanently set to 0000b (0h). 8.8.2 Chip Revision (Bits 3:0) Function: Chip Revision code for the CS4272. Revision A is coded as 0000b (0h). Revision B is coded as 0000b (0h). PART3 PART2 PART1 PART0 REV3 REV2 REV1 REV0

The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. Dynamic Range is a signal-to-noise ratio measurement over the specified bandwidth made with a -60 dBFS signal. 60 dB is added to resulting measurement to refer the measurement to full-scale. This technique ensures that the distortion components are below the noise level and do not affect the measurement. This measurement technique has been accepted by the Audio Engineering Society, AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307. Expressed in decibels. Total Harmonic Distortion + Noise The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels. Measured at -1 and -20 dBFS as suggested in AES17-1991 Annex A. Frequency Response A measure of the amplitude response variation from 10 Hz to 20 kHz relative to the amplitude response at 1 kHz. Units in decibels. Interchannel Isolation A measure of crosstalk between the left and right channels. Measured for each channel at the converter's output with no signal to the input under test and a full-scale signal applied to the other channel. Units in decibels. Interchannel Gain Mismatch The gain difference between left and right channels. Units in decibels. Gain Error The deviation from the nominal full-scale analog output for a full-scale digital input. Gain Drift The change in gain value with temperature. Units in ppm/°C. Offset Error

10.PACKAGE DIMENSIONS Notes: 1. “D” and “E1” are reference datums and do not included mold flash or protrusions, but do include mold mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per side. Dimension “b” does not include dambar protrusion/intrusion. Allowable dambar protrusion shall be 0.13 mm total in excess of “b” dimension at maximum material condition. Dambar intrusion shall not reduce dimension “b” by more than 0.07 mm at least material condition. These dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips. THERMAL CHARACTERISTICS AND SPECIFICATIONS Notes: θJA is specified according to JEDEC specifications for multi-layer PCBs. INCHES MILLIMETERS NOTE DIM MIN NOM MAX MIN NOM MAX A 0.47 1.20 0.002 0.004 0.006 0.05 0.10 0.15 0.03150 0.035 0.04 0.80 0.90 1.00 b 0.00748 0.0096 0.012 0.19 0.245 0.30 2,3 D

0.378 BSC

0.382 BSC

0.386 BSC

9.60 BSC

9.70 BSC

9.80 BSC

E 0.248 0.2519 0.256 6.30 6.40 6.50 0.169 0.1732 0.177 4.30 4.40 4.50 e

0.026 BSC

0.65 BSC

L 0.020 0.024 0.029 0.50 0.60 0.75 JEDEC #: MO-153 Controlling Dimension is Millimeters. Parameters Symbol Min Typ Max Units Package Thermal Resistance (Note 4) 28-TSSOP θJA θJC °C/Watt °C/Watt Allowable Junction Temperature 135 28L TSSOP (4.4 mm BODY) PACKAGE DRAWING E N 1 2 3 e A D SEATING PLANE E11 L SIDE VIEW END VIEW TOP VIEW

Table 18. Revision History

• Updated Figure 8 on page 23.
• Updated Table 9 on page 29.
• Updated the DC Electrical Characteristics table on page 17.
• Updated the DAC Analog Filter Response tables on pages 10 and 11.
• Updated the ADC Digital Filter Characteristics table on page 16.

Add lead-free device ordering info.

• Updated Ordering Information on page 2.

suffix independent temperature grade information. ordering-suffix independent temperature grade information. ordering-suffix independent temperature grade information.

• Updated the DC Electrical Characteristics table on page 17.

istics - Serial Audio Port table on page 18.

• Corrected error in the Memory Address Pointer table on page 36.
• Updated Chip ID register description on page 44.

For all product questions and inquiries contact a Cirrus Logic Sales Representative. or for creating any work for resale. ARISE IN CONNECTION WITH THESE USES. marks or service marks of their respective owners. SPI is a trademark of Motorola, Inc.