CDB4270

CS4270_06 CIRRUS | Alldatasheet

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Copyright © Cirrus Logic, Inc. 2006 (All Rights Reserved)http://www.cirrus.com Preliminary Product Information This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice. 24-Bit, 192 kHz Stereo Audio CODEC D/A Features  High Performance – 105 dB Dynamic Range – -95 dB THD+N  Selectable Serial Audio Interface Formats – Left-Justified up to 24-bit – I²S up to 24-bit – Right-Justified 16-, and 24-Bit  Control Output for External Muting  On-Chip Digital De-Emphasis  Popguard® Technology  Multi-bit ∆Σ Conversion  Digital Volume Control  Single-Ended Output A/D Features  High Performance – 105 dB Dynamic Range – -95 dB THD+N  Multi-bit ∆Σ Conversion  High-Pass Filter to Remove DC Offsets  Selectable Serial Audio Interface Formats – Left-Justified up to 24-bit – I²S up to 24-bit  Single-Ended Input System Features  Direct Interface with Logic Levels 1.8 V to 5 V  Internal Digital Loopback  Stand-Alone or Control Port Functionality  Single-Ended Analog Architecture  Supports all Audio Sample Rates from 4 kHz to 216 kHz  3.3 V or 5 V Core Supply Control Port Supply

1.8 V to 5 V

3.3 V to 5 V

Multi-bit ∆Σ Modulators External Mute Control Mute Signals2 2 2 Switch-Cap ADC Single-Ended Inputs Digital Filters High-Pass Filter PCM Serial Audio Output MAY '06 DS686PP1 CS4270

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Stand-Alone Mode Feature Set  System Features – Serial Audio Port Master or Slave Operation – Single-, Double-, or Quad-Speed Operation  D/A Features – Auto-Mute on Static Samples – 44.1 kHz 50/15 µs De-emphasis Available – Selectable Serial Audio Interface Formats

• Left-Justified up to 24-bit
• I²S up to 24-bit A/D Features – High-Pass Filter – Selectable Serial Audio Interface Formats
• Left-Justified up to 24-bit
• I²S up to 24-bit Software Mode Feature Set  System Features – Serial Audio Port Master or Slave Operation – Internal Digital Loopback Available  D/A Features – Selectable Auto-mute – 44.1-kHz De-emphasis Filters – Configurable Muting Controls – Volume Control – Selectable Serial Audio Interface Formats
• Left-Justified up to 24-bit
• I²S up to 24-bit
• Right-Justified 16, and 24-bit A/D Features – Selectable High-Pass Filter or DC Offset Calibration – Selectable Serial Audio Interface Formats
• Left-Justified up to 24-bit
• I²S up to 24-bit General Description The CS4270 is a high-performance, integrated audio CODEC. The CS4270 performs stereo analog-to-digital (A/D) and digital-to-analog (D/A) conversion of up to 24-bit serial values at sample rates up to 216 kHz. Standard 50/15 µs de-emphasis is available for sam- pling rates of 44.1 kHz for compatibility with digital audio programs mastered using the 50/15 µs pre-emphasis technique. Integrated level translators allow easy interfacing be- tween the CS4270 and other devices operating over a wide range of logic levels. Independently addressable high-pass filters are avail- able for the right and left channel of the A/D. This allows the A/D to be used in a wide variety of applications where one audio channel and one DC measurement channel is desired. The CS4270 is available in a 24-pin TSSOP package in both Commercial (-10° to +70° C) and Automotive grades (-40° to +85° C). The CDB4270 Customer Dem- onstration board is also available for device evaluation and implementation suggestions. Please refer to “Ordering Information” on page 47 for complete order- ing information. The CS4270’s wide dynamic range, negligible distor- tion, and low noise make it ideal for applications such as DVD-recorders, digital televisions, set-top boxes, ef- fects processors, and automotive audio systems.

6.2 I²C

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Figure 11. Format 2, Right-Justified 16-Bit Data. (Available in Control Port Mode only)

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1. PIN DESCRIPTIONS - SOFTWARE MODE Pin Name # Pin Description SDIN 1 Serial Audio Data Input (Input) - Input for two’s complement serial audio data. LRCK 2 Left Right Clock (Input/Output) - Determines which channel, Left or Right, is currently active on the serial audio data line. MCLK 3 Master Clock (Input) - Clock source for the delta-sigma modulator and digital filters. SCLK 4 Serial Clock (Input/Output) - Serial clock for the serial audio interface. VD 5 Digital Power (Input) - Positive power supply for the digital section. DGND 6 Digital Ground (Input) - Ground reference for the internal digital section. SDOUT 7 Serial Audio Data Output (Output) - Output for two’s complement serial audio data. VLC 8 Control Port Power (Input) - Determines the signal level for the Control Port. SDA/CDOUT 9 Serial Control Data (Input/Output) - SDA is a data I/O in I²C® Mode. CDOUT is the output data line for the Control Port interface in SPI® Mode. SCL/CCLK 10 Serial Control Port Clock (Input) - Serial clock for the serial Control Port. AD0/CS 11 Address Bit 0 (I²C) / Control Port Chip Select (SPI) (Input) - AD0 is a chip address pin in I²C Mode. CS is the chip select signal for SPI format. AD1/CDIN 12 Address Bit 1 (I²C) / Serial Control Data (Input) - AD1 is a chip address pin in I²C Mode. CDIN is the input data line for the Control Port interface in SPI Mode. AD2 13 Address Bit 2 (I²C) (Input) - AD2 is a chip address pin in I²C Mode. RST 14 Reset (Input) - The device enters a low power mode when low. AINA AINB Analog Input (Input) - The full-scale analog input level is specified in the ADC Analog Characteristics specification table. VQ 17 Quiescent Voltage (Output) - Filter connection for internal quiescent voltage. FILT+ 18 Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling circuits. VA 19 Analog Power (Input) - Positive power for the analog sections. AGND 20 Analog Ground (Input) - Ground reference. Must be connected to analog ground. MUTEA MUTEB Mute Control (Output) - Each pin is active during power-up initialization, reset, muting, when master clock to left/right clock frequency ratio is incorrect, or power-down. AOUTA AOUTB Analog Audio Output (Output) - The full-scale output level is specified in the DAC Analog Character- istics specification table. SDIN LRCK MCLK SCLK VD DGND SDOUT VLC SDA/CDOUT SCL/CCLK AD0/CS AD1/CDIN MUTEB AOUTB AOUTA MUTEA AGND VA FILT+ VQ AINB AINA RST AD2

1. PIN DESCRIPTIONS - STAND-ALONE MODE Pin Name # Pin Description SDIN 1 Serial Audio Data Input (Input) - Input for two’s complement serial audio data. LRCK 2 Left Right Clock (Input/Output) - Determines which channel, Left or Right, is currently active on the serial audio data line. MCLK 3 Master Clock (Input) - Clock source for the delta-sigma modulator and digital filters. SCLK 4 Serial Clock (Input/Output) - Serial clock for the serial audio interface. VD 5 Digital Power (Input) - Positive power supply for the digital section. DGND 6 Digital Ground (Input) - Ground reference for the internal digital section. SDOUT (M/S) 7 Serial Audio Data Output (Output) - Output for two’s complement serial audio data. This pin must be pulled-up or pulled-down to select Master or Slave Mode. VLC 8 Control Port Power (Input) - Determines the signal level for the Control Port. 10 Mode Selection (Input) - Determines the operational mode of the device. I²S/LJ 11 Serial Audio Interface Select (Input) - Selects either the Left-Justified or I²S format for the Serial Audio Interface. MDIV1 MDIV2 13 MCLK Divide (Input) - Configures MCLK divider to divide by 1, 1.5, 2, or 4. RST 14 Reset (Input) - The device enters a low power mode when low. AINA AINB Analog Input (Input) - The full-scale analog input level is specified in the ADC Analog Characteristics specification table. VQ 17 Quiescent Voltage (Output) - Filter connection for internal quiescent voltage. FILT+ 18 Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling circuits. VA 19 Analog Power (Input) - Positive power for the analog sections. AGND 20 Analog Ground (Input) - Ground reference. Must be connected to analog ground. MUTEA MUTEB Mute Control (Output) - Each pin is active during power-up initialization, reset, muting, when master clock to left/right clock frequency ratio is incorrect, or power-down. AOUTA AOUTB Analog Audio Output (Output) - The full-scale output level is specified in the DAC Analog Characteris- tics specification table. SDIN LRCK MCLK SCLK VD DGND SDOUT VLC I²S/LJ MDIV1 MUTEB AOUTB AOUTA MUTEA AGND VA FILT+ VQ AINB AINA RST MDIV2

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1. TYPICAL CONNECTION DIAGRAM

Figure 1. CS4270 Typical Connection Diagram

1. CHARACTERISTICS AND SPECIFICATIONS (All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical performance characteristics and specifications are derived from measurements taken at nominal supply voltages and TA = 25°C.) SPECIFIED OPERATING CONDITIONS (AGND = 0 V; all voltages with respect to ground.) ABSOLUTE MAXIMUM RATINGS (AGND = DGND = 0 V, All voltages with respect to ground.) (Note 1) Notes: 1. Operation beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. 2. Any pin except supplies. Transien t currents of up to ±100 mA on the analog input pins will not cause SRC latch-up. THERMAL CHARACTERISTICS 3. θJA is specified according to JEDEC specifications for multi-layer PCBs. Parameters Symbol Min Nom Max Units DC Power Supplies: Analog Digital Control Port Interface VA VD VLC 3.1 3.1 1.7 5.0 3.3 3.3 5.25 5.25 5.25 V V V Ambient Operating Temperature (Power Applied) Commercial Automotive TA -10 -40 +70 +85 Parameter Symbol Min Typ Max Units DC Power Supplies: Analog Digital Control Port Interface VA VD VLC -0.3 -0.3 -0.3 +6.0 +6.0 +6.0 V V V Input Current (Note 2) Iin -10 - +10 mA Analog Input Voltage VIN AGND-0.7 - VA+0.7 V Digital Input Voltage Control Port Interface Digital Interface VIND-C VIND-D -0.3 -0.3 -V L C + 0 . 3 VD+0.3 V V Ambient Operating Temperature (Power Applied) TAC -50 - +95 °C Storage Temperature Tstg -65 - +150 °C Parameters Symbol Min Typ Max Units Allowable Junction Temperature -- 1 3 5 °C Junction to Ambient Thermal Impedance (Note 3) (Multi-layer PCB) TSSOP (Single-layer PCB) TSSOP θJA-M θJA-S 105 °C/W °C/W

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DAC ANALOG CHARACTERISTICS - COMMERCIAL GRADE (Full-Scale Output Sine Wave, 997 Hz (Note 4), Fs = 48/96/192 kHz; Test load RL = 3 kΩ, CL = 10 pF (see Figure 2). Measurement Bandwidth 10 Hz to 20 kHz, unless otherwise specified.) DAC ANALOG CHARACTERISTICS - AUTOMOTIVE GRADE (Full-Scale Output Sine Wave, 997 Hz (Note 4), Fs = 48/96/192 kHz; Test load RL = 3 kΩ, CL = 10 pF (see Figure 2). Measurement Bandwidth 10 Hz to 20 kHz, unless otherwise specified.) 4. One-half LSB of triangular PDF dither added to data. Parameter VA = 5 V VA = 3.3 V Min Typ Max Min Typ Max Unit Dynamic Range 18 to 24-Bit A-weighted unweighted 16-Bit A-weighted unweighted 105 102 103 100 dB dB dB dB Total Harmonic Distortion + Noise 18 to 24-Bit 0 dB -20 dB -60 dB 16-Bit 0 dB -20 dB -60 dB -89 -76 -36 -87 -67 -27 -83 -70 -30 -81 -61 -21 -89 -76 -36 -87 -67 -27 -83 -70 -30 -81 -61 -21 dB dB dB dB dB dB Parameter VA = 5 V VA = 3.3 V Min Typ Max Min Typ Max Unit Dynamic Range 18 to 24-Bit A-weighted unweighted 16-Bit A-weighted unweighted 105 102 103 100 dB dB dB dB Total Harmonic Distortion + Noise 18 to 24-Bit 0 dB -20 dB -60 dB 16-Bit 0 dB -20 dB -60 dB -89 -76 -36 -87 -67 -27 -79 -66 -26 -77 -57 -17 -89 -76 -36 -87 -67 -27 -79 -66 -26 -77 -57 -17 dB dB dB dB dB dB

Figure 2. Output Test Load Figure 3. Maximum Loading

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DAC COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE (The filter characteristics have been normalized to the sample rate (Fs) and can be referenced to the desired sam- ple rate by multiplying the given characteristic by Fs.) (See Note 5) 5. Amplitude vs. Frequency plots of this data are available in Section 9. “Filter Plots” on page 41. See Figures 24 through 47. 6. Response is clock dependent and will scale with Fs. 7. For Single-Speed Mode, the Measuremen t Bandwidth is 0.5465 Fs to 3 Fs. For Double-Speed Mode, the Measurement Bandwidth is 0.577 Fs to 1.4 Fs. For Quad-Speed Mode, the Measurement Bandwidth is 0.7 Fs to 1 Fs. 8. De-emphasis is available only in Single-Speed Mode. Parameter Symbol Min Typ Max Unit Single-Speed Mode Passband (Note 6) to -0.1 dB corner to -3 dB corner .35 .4992 Fs Fs Frequency Response 10 Hz to 20 kHz -.175 - +.01 dB StopBand .5465 - - Fs StopBand Attenuation (Note 7) 50 - - dB Group Delay tgd - 10/Fs - s De-emphasis Error (Note 8) Fs = 32 kHz Fs = 44.1 kHz Fs = 48 kHz +1.5/+0 +.05/-.25 -.2/-.4 dB dB dB Double-Speed Mode Passband (Note 6) to -0.1 dB corner to -3 dB corner .22 .501 Fs Fs Frequency Response 10 Hz to 20 kHz -.15 - +.15 dB StopBand .5770 - - Fs StopBand Attenuation (Note 7) 55 - - dB Group Delay tgd - 5/Fs - s Quad-Speed Mode Passband (Note 6) to -0.1 dB corner to -3 dB corner 0.110 0.469 Fs Fs Frequency Response 10 Hz to 20 kHz -.12 - +0 dB StopBand 0.7 - - Fs StopBand Attenuation (Note 7) 51 - - dB Group Delay tgd - 2.5/Fs - s

ADC ANALOG CHARACTERISTICS - COMMERCIAL GRADE Measurement bandwidth is 10 Hz to 20 kHz unless otherwise specified. Figure 18 input circuit, 1 kHz sine wave in. 9. Referred to the typical full-scale input voltage. Dynamic Performance for Commercial Grade VA = 5 V VA = 3.3 V Single-Speed Mode Fs = 48 kHz Symbol Min Typ Max Min Typ Max Unit Dynamic Range A-weighted unweighted 105 102 102 dB dB Total Harmonic Distortion + Noise (Note 9) -1 dB -20 dB -60 dB THD+N -95 -82 -42 -90 -92 -79 -39 -87 dB dB dB Double-Speed Mode Fs = 96 kHz Dynamic Range A-weighted unweighted 40 kHz bandwidth unweighted 105 102 102 dB dB dB Total Harmonic Distortion + Noise (Note 9) -1 dB -20 dB -60 dB 40 kHz bandwidth -1 dB THD+N -95 -82 -42 -95 -90 -92 -79 -39 -87 -87 dB dB dB dB Quad-Speed Mode Fs = 192 kHz Dynamic Range A-weighted unweighted 40 kHz bandwidth unweighted 105 102 102 dB dB dB Total Harmonic Distortion + Noise (Note 9) -1 dB -20 dB -60 dB 40 kHz bandwidth -1 dB THD+N -95 -82 -42 -95 -90 -92 -79 -39 -87 -87 dB dB dB dB Dynamic Performance for Commercial Grade - All Modes Parameter Min Typ Max Unit Interchannel Isolation - 90 - dB DC Accuracy Interchannel Gain Mismatch - 0.1 - dB Gain Error -3 - +3 % Gain Drift - ±100 - ppm/°C Analog Input Characteristics Full-Scale Input Voltage 0.53*VA 0.56*VA 0.58*VA Vpp Input Impedance - 300 - kΩ

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ADC ANALOG CHARACTERISTICS - AUTOMOTIVE GRADE Measurement Bandwidth is 10 Hz to 20 kHz unless otherwise specified. Figure 18 input circuit, 1 kHz sine wave in. 10. Referred to the typica l full-scale input voltage. Dynamic Performance for Automotive Grade VA = 5 V VA = 3.3 V Single-Speed Mode Fs = 48 kHz Symbol Min Typ Max Min Typ Max Unit Dynamic Range A-weighted unweighted 105 102 102 dB dB Total Harmonic Distortion + Noise (Note 10) -1 dB -20 dB -60 dB THD+N -95 -82 -42 -90 -92 -79 -39 -87 dB dB dB Double-Speed Mode Fs = 96 kHz Dynamic Range A-weighted unweighted 40 kHz bandwidth unweighted 105 102 102 dB dB dB Total Harmonic Distortion + Noise (Note 10) -1 dB -20 dB -60 dB 40 kHz bandwidth -1 dB THD+N -95 -82 -42 -95 -90 -92 -79 -39 -87 -87 dB dB dB dB Quad-Speed Mode Fs = 192 kHz Dynamic Range A-weighted unweighted 40 kHz bandwidth unweighted 105 102 102 dB dB dB Total Harmonic Distortion + Noise (Note 10) -1 dB -20 dB -60 dB 40 kHz bandwidth -1 dB THD+N -95 -82 -42 -95 -90 -92 -79 -39 -87 -87 dB dB dB dB Dynamic Performance for Automotive Grade - All Modes Parameter Min Typ Max Unit Interchannel Isolation - 90 - dB DC Accuracy Interchannel Gain Mismatch - 0.1 - dB Gain Error -3 - +3 % Gain Drift - ±100 - ppm/°C Analog Input Characteristics Full-Scale Input Voltage 0.53*VA 0.56*VA 0.58*VA Vpp Input Impedance - 300 - kΩ

ADC DIGITAL FILTER CHARACTERISTICS (Measurement Bandwidth is 10 Hz to 20 kHz unless otherwise specified) (Note 11) 11. Plots of this data are contained in Section 9. “Filter Plots” on page 41. See Figures 24 through 47. 12. The filter frequency response scales precisely with Fs. 13. Response shown is for Fs equal to 48 kHz. Filter characteristics scale with Fs. Parameter Symbol Min Typ Max Unit Single-Speed Mode Passband (-0.1 dB) (Note 12) 0 - 0.49 Fs Passband Ripple - - 0.035 dB Stopband (Note 12) 0.57 - - Fs Stopband Attenuation 70 - - dB Group Delay tgd - 12/Fs - s Double-Speed Mode Passband (-0.1 dB) (Note 12) 0 - 0.49 Fs Passband Ripple - - 0.05 dB Stopband (Note 12) 0.56 - - Fs Stopband Attenuation 69 - - dB Group Delay tgd -9 / F s- s Quad-Speed Mode Passband (-0.1 dB) (Note 12) 0 - 0.26 Fs Passband Ripple - - 0.05 dB Stopband (Note 12) 0.50 - - Fs Stopband Attenuation 60 - - dB Group Delay tgd -5 / F s- s High-Pass Filter Characteristics Frequency Response -3.0 dB -0.13 dB (Note 13) Hz Hz Phase Deviation @ 20 Hz (Note 13) -1 0- d e g Passband Ripple --0 d B

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DC ELECTRICAL CHARACTERISTICS (TA = 25° C; AGND=DGND=0, all voltages with respect to ground; MLCK=12.288 MHz; Master Mode) 14. Power Down Mode is defined as RST = Low with all clocks and data lines held static. 15. Valid with the recommended capacitor values on FILT+ and VQ as shown in the Typical Connection Diagram. DIGITAL CHARACTERISTICS 16. Serial Port signals include: SCLK, LRCK, SDOUT, SDIN Control Port signals include: SDA/CDOUT, SCL/CCLK, AD1/CDIN, AD0/CS, RST Parameter Symbol Min Typ Max Unit Power Supply Power Supply Current VA = 5 V (Normal Operation) VA = 3.3 V VD, VLC = 5 V VD, VLC = 3.3 V IA IA ID ID mA mA mA mA Power Supply Current VA = 5 V (Power-Down Mode) (Note 14) VD, VLC = 5 V IA ID 1.51 0.45 mA mA Power Consumption VA = 5 V, VD = VLC= 3.3 V Normal Operation VA = 5 V, VD = VLC = 5 V Normal Operation Power-Down Mode (Note 14) 221 255 9.8 296 323 mW mW mW Power Supply Rejection Ratio (1 kHz) (Note 15) PSRR - 55 - dB Common Mode Voltage Nominal Common Mode Voltage VQ - VA/2 - VDC Maximum DC Current Source/Sink from VQ -1 - µA VQ Output Impedance -2 5 - k Ω Positive Voltage Reference FILT+ Nominal Voltage FILT+ - VA - VDC Maximum DC Current Source/Sink from FILT+ -1 0 - µA FILT+ Output Impedance -1 8 - k Ω Mute Control MUTEA, MUTEB Low-Level Output Voltage -0 - V MUTEA, MUTEB High-Level Output Voltage -V A - V Maximum MUTEA & MUTEB Drive Current -3 - m A Parameter (Note 16) Symbol Min Typ Max Units High-Level Input Voltage Serial Port Control Port VIH 0.7xVD 0.7xVLC V V Low-Level Input Voltage Serial Port Control Port VIL - 0.2xVD 0.2xVLC V V High-Level Output Voltage at Io = 2 mA Serial Port Control Port MUTEA, MUTEB VOH VD - 1.0 VLC - 1.0 VA - 1.0 V V V Low-Level Output Voltage at Io = 2 mA VOL -- 0 . 4 V Input Leakage Current Iin -10 - 10 µA

SWITCHING CHARACTERISTICS - SERIAL AUDIO PORT (Logic "0" = AGND = 0 V; Logic "1" = VD, CL = 20 pF) 17. In Control Port Mode, MCLK Frequency and Functional Mode Select bits must be configured according to Table 5, Table 8, and Table 12. 18. t sclkw = tsclkh + tsclkl in Figures 5 and 7. Parameter Symbol Min Typ Max Unit Sample Rate Single-Speed Mode Double-Speed Mode Quad-Speed Mode Fs Fs Fs 100 108 216 kHz kHz kHz MCLK Specifications MCLK Frequency tand-Alone Mode (Note 17) Control Port Mode fmclk fmclk 1.024 1.024 55.296 55.296 MHz MHz MCLK Duty Cycle 40 50 60 ns Master Mode LRCK Duty Cycle -5 0- % SCLK Period (Note 18) tsclkw -- s SCLK Duty Cycle -5 0- % SCLK falling to LRCK edge tmslr -20 - 20 ns SCLK falling to SDOUT valid tsdo - - 32 ns SDIN valid to SCLK rising setup time tsdis 16 - - ns SCLK rising to SDIN hold time tsdih 20 - - ns Slave Mode LRCK Duty Cycle 40 50 60 % SCLK Period (Note 17) Single-Speed Mode Double-Speed Mode Quad-Speed Mode tsclkw tsclkw tsclkw s s s SCLK Duty Cycle 45 50 55 ns SCLK falling to LRCK edge tslrd -20 - 20 ns SDOUT valid before SCLK rising tstp 10 - - ns SDOUT valid after SCLK rising thld 5-- n s SDIN valid to SCLK rising setup time tsdis 16 - - ns SCLK rising to SDIN hold time tsdih 20 - - ns

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Figure 4. Master Mode, Left-Justified SAI Figure 5. Slave M ode, Left-Justified SAI Figure 6. Master Mode, I²S SAI Figure 7. Slave Mode, I²S SAI Figure 8. Master and Slave Mode SDIN vrs. SCLK

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1. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.

Figure 12. I²C Mode Control Port Timing

1. t spi only needed before first falling edge of CS after RST rising edge. tspi = 0 at all other times.
2. Data must be held for sufficient time to bridge the transition time of CCLK.

Figure 13. SPI Control Port Timing

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5.1 Stand-Alone Mode

5.1.1 Recommended Po wer-Up Sequence

supplies drop below the minimum specified operating voltages to prevent power glitch related issues.

5.1.2 Master/Slave Mode

The CS4270 supports operation in either Master Mode or Slave Mode. to Fs and SCLK is equal to 64x Fs. In Slave Mode, LRCK and SCLK are inputs, requiring external generation that is synchronous to MCLK. It is recommended that SCLK be 48x or 64x Fs to maximize system performance. 47 kΩ resistor. Master Mode may be accessed by placing a 47 kΩ pull-up to VD on the SDOUT (M/S) pin. Configuration of clock ratios in each of these modes is outlined in Table 2.

5.1.3 System Clocking

Table 1. Speed Modes

5.1.4 Clock Ratio Selection

ratios may be used. These ratios are shown in the Table 2.

5.1.5 Interpolation Filter

tion 4. Plots of the data are contained in Section 9. “Filter Plots” on page 41.

5.1.6 High-Pass Filter

the output of the decimation filter This function cannot be disabled in Stand-Alone Mode. Table 2. Clock Ratios - Stand-Alone Mode

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5.1.7 Mode Selection & De-Emphasis

pin becomes De-emphasis select. Stand-alone definitions of the mode pins are shown in Table 3.

5.1.8 Serial Audio Inte rface Format Selection

I²S format, while placing a 10 kΩ pull-down to DGND on the I²S/LJ pin will select the Left-Justified format.

5.2 Control Port Mode

5.2.1 Recommended Power-Up Sequen ce - Access to Control Port Mode

1. Pull RST low until the power supply, MCLK, and LRCK are stable.
2. Release RST . The Control Port will be accessible.
3. Set the power down bit (register 0x02h, bit 0) to “1” for 1 ms minimum within 10 ms after releasing

RST and then set to “0” prior to reading or writing to other registers.

1. Initiate a SPI or I²C transaction as described in Section 6.1 or Section 6.2, respectively.

5.2.2 Master / Slave Mode Selection

The CS4270 supports operation in either Master Mode or Slave Mode. to Fs and SCLK is equal to 64x Fs. In Slave Mode, LRCK and SCLK are inputs, requiring external generation that is synchronous to MCLK. It is recommended that SCLK be 48x or 64x Fs to maximize system performance. Configuration of clock ratios in each of these modes will be outlined in the Table 10 and Table 9. changing the status of the M/S bits in the Functional Control Register (03h). Table 3. CS4270 Stand-Alone Mode Control

5.2.3 System Clocking

speed modes as shown in Table 4.

5.2.4 Clock Ratio Selection

Port Register Bits are shown in Table 5, Table 9 and Section 8.3 on page 36. Table 4. Speed Modes Table 5. Clock Ratios - Control Port Mode

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5.2.5 Internal Digital Loopback

the ADC & DAC Ctrl register (04h). When this bit is set, the status of the DAC_DIF(4:3) bits in register 04h will be disregarded by the CS4270. set, data will be present on the SDOUT pin in the format selected in the ADC_DIF(0) bit in register 04h.

5.2.6 Auto-Mute

by the Soft and ZeroCross bits in the Transition and Control register. The Auto Mute bit is set by default.

5.2.7 High-Pass Filter a nd DC Offset Calibration

DC level, possibly yielding "clicks" when switching between devices in a multichannel system.

1. Running the CS4270 with the high-pass filter enabled until the filter settles. See the Digital Filter

Characteristics for filter settling time.

1. Disabling the high-pass filter and freezing the stored DC offset.

calibration point and the CS4270. Table 5. Clock Ratios - Control Port Mode (Continued)

5.2.8 De-Emphasis

One de-emphasis mode is available via the Control Port and is optimized for 44.1 kHz sampling rate.

5.2.9 Oversampling Modes

5.3 De-Emphasis Filter

Section 5.2.8 for Control Port Mode. equalization as a means of noise reduction. De-emphasis is only available in Single-Speed Mode. Figure 14. De-Emphasis Curve

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5.4 Analog Connections

5.4.1 Input Connections

at the modulator sampling frequency, but also act as a charge source for the internal sampling circuits. avoided since these can degrade signal linearity. attenuation, and input impedance. Table 6 shows the design equation used to determine these values. imized and THD+N degrades for source impedance greater than 1 kΩ. See Figure 16 and 17 below. Figure 15. CS4270 Recommended Analog Input Network Figure 16. A/D THD+N Performance vrs. Input Source Resistance

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5.4.2 Output Connections

recommended external analog circuitry is shown in Figure 19.

5.5 Mute Control

an external mute circuit in order to add off-chip mute capability. the corresponding MUTE pin to deactivate. circuit. The MUTE pins are active-low. See Figure 20 for a suggested active-low mute circuit. Figure 18. CS4270 Example Analog Input Network Figure 19. CS4270 Recommended Analog Output Filter

5.6 Synchronization of Multiple Devices

edge of MCLK. This will ensure that all converters begin sampling on the same clock edge.

5.7 Grounding and Power Supply Decoupling

CS4270 digital outputs only to CMOS inputs. Figure 20. Suggested Active-Low Mute Circuit

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Port pins should remain static if no operation is required. low transition on AD0/CS after power-up, SPI Mode will be selected. the proper serial mode can be selected.

6.1 SPI ™ Mode

clocked in on the rising edge of CCLK. designated by the MAP. See Table 9 on page 36. is written, allowing block writes to successive registers. Figure 21. Control Port Timing, SPI Mode

6.2 I²C ® Mode

is a read, then the contents of the register pointed to by the MAP will be output after the chip address. is written, allowing block reads or writes of successive registers. Table 7. Memory Address Pointer

1001 ADDR

Note: If operation is a write, this byte contains the Memory Address Pointer, MAP. Figure 22. Control Port Timing, I²C Mode

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1. REGISTER QU ICK REFERENCE This table shows the register names and their associated default values. Addr Function 7 6 5 4 3 2 1 0 11 0 0 0 0 0 1 02h Power Control Freeze Reserved PDN_ADC Reserved Reserved Reserved PDN_DAC PDN 00 0 0 0 0 0 0 03h Funct Mode Reserved Reserved FM_&_M/S _Mode1 FM_&_M/S_ Mode0 MCLK freq<2> MCLK freq<1> MCLK freq<0> PopGuard Disable 00 1 1 0 0 0 0 04h Serial Format ADC HPF Freeze A ADC HPF Freeze B Digital Loopback DAC_DIF1 DAC_DIF0 Reserved Reserved ADC_DIF0 00 0 0 0 0 0 0 05h Transition Control DAC Single Vol soft_dac zc_dac Invert ADC ch B Invert ADC ch A Invert DAC ch B Invert DAC ch A De-Emph 01 1 0 0 0 0 0 06h Mute Reserved Reserved Auto Mute Mute ADC SP ch B Mute ADC SP ch A Mute Polarity Mute DAC ch B Mute DAC ch A 00 1 0 0 0 0 0 07h Vol Ctrl AOUTA dacA vol<7> dacA vol<6> dacA vol<5> dacA vol<4> dacA vol<3> dacA vol<2> dacA vol<1> dacA vol<0> 00 0 0 0 0 0 0 08h Vol Ctrl AOUTB dacB vol<7> dacB vol<6> dacB vol<5> dacB vol<4> dacB vol<3> dacB vol<2> dacB vol<1> dacB vol<0> 00 0 0 0 0 0 0

1. REGISTER DESCRIPTION All registers are read/write in I²C Mode and SPI Mode, unless otherwise noted

8.1 Chip ID - Address 01h

Function: This register is Read-Only. Bits 7 through 4 are the part number ID which is 1100b (01h) and the remaining bits (b3:b0) are for the chip revision.

8.2 Power Control - Address 02h

8.2.1 Freeze (Bit 7)

Function: This function allows modifications to be made to certain Control Port bits without the changes taking effect until the Freeze bit is disabled. To make multiple changes to these bits take effect simultaneously, set the Freeze bit, make all changes, then clear the Freeze bit. The bits affected by the Freeze function are listed below: – Register 05h (Bits 7:0) – Register 06h (Bits 7:0) – Register 07h (Bits 7:0) – Register 08h (Bits 7:0)

8.2.2 PDN_ADC (Bit 5)

Function: The ADC portion of the device will enter a low-power state whenever this bit is set.

8.2.3 PDN_DAC (Bit 1)

Function: The DAC portion of the device will enter a low-power state whenever this bit is set.

8.2.4 Power Down (Bit 0)

Function: The device will enter a low-power state whenever this bit is set. The contents of the control registers are retained when the device is in power-down. 76543210 76543210 Freeze Reserved PDN_ADC Reserved Reserved Reserved PDN_DAC PDN

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8.3 Mode Control - Address 03h

8.3.1 ADC Functional Mode & Mast er / Slave Mode (Bits 5:4)

Port Slave Mode, the CS4270 auto-detects speed mode.

8.3.2 Ratio Select (Bits 3:1)

These bits are used to select the clocking ratios.

8.3.3 Popguard Disable (Bit 0)

when set. Popguard is enabled by default.

8.4 ADC and DAC Control - Address 04h

8.4.1 ADC HPF Freeze A (Bit 7)

Pass Filter and DC Offset Calibration” on page 26.

00 Single-Speed Mode: 4 to 54 kHz sample rates

01 Double-Speed Mode: 50 to 108 kHz sample rates

10 Quad-Speed Mode: 100 to 216 kHz sample rates

11 Slave Mode (default)

Table 8. Functional Mode Selection Table 9. MCLK Divider Configuration

8.4.2 ADC HPF Freeze B (Bit 6)

Pass Filter and DC Offset Calibration” on page 26.

8.4.3 Digital Loopback (Bit 5)

Section 5.2.5 “Internal Digital Loopback” on page 26.

8.4.4 DAC Digital Interf ace Format (Bits 4:3)

The DAC Digital Interface Format and the options are detailed in Table 10 and Figures 9 through 11.

8.4.5 ADC Digital Inte rface Format (Bit 0)

Interface Format. The options are detailed in Table 11 and may be seen in Figures 9 and 10. Table 10. DAC Digital Interface Formats

0 Left-Justified, up to 24-bit data (default) 0 9

1 I²S, up to 24-bit data 1 10

Table 11. ADC Digital Interface Formats

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8.5 Transition Control - Address 05h

8.5.1 DAC Single Volume (Bit 7)

enabled. Volume and muting functions are affected by the Soft Ramp and ZeroCross functions below.

8.5.2 Soft Ramp or Zero Cross Enable (Bits 6:5)

ing, in 1/8 dB steps, from the current level to the new level at a rate of 1 dB per 8 left/right clock periods. for each channel. See Table 9 on page 36. itored and implemented for each channel. See Table 9 on page 36.

8.5.3 Invert Signal Polarity (Bits 4:1)

a board layout error has occurred or in other situations where a 180 degree phase shift is desirable. Table 12. Soft Cross or Zero Cross Mode Selection

8.5.4 De-Emphasis Control (Bit 0)

the filter response. NOTE: De-emphasis is available only in Single-Speed Mode.

8.6 Mute Control - Address 06h

8.6.1 Auto-Mute (Bit 5)

When set, enables the Auto-Mute function. Section 5.2.6 “Auto-Mute” on page 26.

8.6.2 ADC Channel A & B Mute (Bits 4:3)

When this bit is set, the output of the ADC for the selected channel will be muted.

8.6.3 Mute Polarity (Bit 2)

8.6.4 DAC Channel A & B Mute (Bits 1:0)

When this bit is set, the output of the DAC for the selected channel will be muted. Figure 23. De-Emphasis Curve

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8.7 DAC Channel A Volume Control - Address 07h

See Section 8.8 DAC Channel B Volume Control - Address 08h.

8.8 DAC Channel B Volume Control - Address 08h

The digital volume control allows the user to attenuate the signal in 0.5 dB increments from 0 to -127 dB. Cross bits in the Transition Control register (see Section 8.5.2). Table 13. Digital Volume Control

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Figure 30. DAC Double-Speed Transition Band (detail) Figure 31. DAC Double-Speed Passband Ripple Figure 32. DAC Quad-Speed Stopband Rejection Figure 33. DAC Quad-Speed Transition Band Figure 34. DAC Quad-Speed Transition Band (detail) Figure 35. DAC Quad-Speed Passband Ripple

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Figure 42. ADC Double-Speed Transition Band (detail) Figure 43. ADC Double-Speed Passband Ripple Figure 44. ADC Quad-Speed Stopband Rejection Figure 45. ADC Quad-Speed Stopband (detail) Figure 46. ADC Quad-Speed Transition Band (detail) Figure 47. ADC Quad-Speed Passband Ripple

10.PARAMETER DEFINITIONS Dynamic Range The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. Dynamic Range is a signal-to-noise ratio measurement over the specified bandwidth made with a -60 dBFS signal. 60 dB is added to resulting measurement to refer the meas urement to full-scale. This technique ensures that the distortion components are below the noise level and do not affect the measurement. This measurement technique has been accepted by the Audio Engineering Society, AES17-1991, and the Electronic Industries Association of Ja- pan, EIAJ CP-307. Expressed in decibels. Total Harmonic Distortion + Noise The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth (typically 10 Hz to 20 kHz), including distortion component s. Expressed in decibels. Measured at -1 and -20 dBFS as suggested in AES17-1991 Annex A. Frequency Response A measure of the amplitude response variation from 10 Hz to 20 kHz relative to the amplitude response at 1 kHz. Units in decibels. Interchannel Isolation A measure of crosstalk between the left and right channel s. Measured for each channel at the converter's output with no signal to the input under test and a full-scale signal applied to the other channel. Units in decibels. Interchannel Gain Mismatch The gain difference between left and right channels. Units in decibels. Gain Error The deviation from the nominal full-scale analog output for a full-scale digital input. Gain Drift The change in gain value with temperature. Units in ppm/°C. Offset Error

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11.PACKAGE DIMENSIONS Notes: 1. “D” and “E1” are reference datums and do not incl uded mold flash or protrusions, but do include mold mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per side. 2. Dimension “b” does not include dambar protrusi on/intrusion. Allowable dambar protrusion shall be 0.13 mm total in excess of “b” dimension at maximum material condition. Dambar intrusion shall not re- duce dimension “b” by more than 0.07 mm at least material condition. 3. These dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips. INCHES MILLIMETERS NOTE DIM MIN NOM MAX MIN NOM MAX JEDEC #: MO-153 Controlling Dimension is Millimeters. 24L TSSOP (4.4 mm BODY) PACKAGE DRAWING E N 1 23 e b2 A1 A2 A D SEATING PLANE E11 L SIDE VIEW END VIEW TOP VIEW

12.ORDERING INFORMATION 13.REVISION HISTORY Product Description Package Pb-Free Grade Temp Range Container Order # CS4270 24-Bit 192 kHz Stereo Audio CODEC 24-TSSOP YES Commercial -10° to +70° C Rail CS4270-CZZ Tape & Reel CS4270-CZZR CS4270 24-Bit 192 kHz Stereo Audio CODEC 24-TSSOP YES Automotive -40° to +85° C Rail CS4270-DZZ Tape & Reel CS4270-DZZR CDB4270 CS4270 Evaluation Board -- - - - CDB4270 Release Changes A1 Initial Release

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– Update Release after B0 chip validation – Changed value of A/D shunt capacitor from 2200 pF to 220 pF in Figure 18 – Added “single ended input” to “A/D Features” on page 1 and “single ended output” to “D/A Features” on page 1 – Added “3.3 V or 5 V core supply” to “System Features” on page 1 – Added package/grade & ordering info to “General Description” on page 2 – Changed note 2. in Figure 1 – Moved ordering info to Section 12 – Moved Typical Connection Diagram to Section 3 – Removed SOIC data from Thermal Characteristics Table on page 9 – Changed DAC THD+N specs in “DAC Analog Characteristics - Commercial Grade” on page 10 and “DAC Analog Characteristics - Automotive Grade” on page 10 – Changed DAC Full Scale Output Voltage specs in “DAC Analog Characteristics - all Modes” on page 11 – Revised specifications in “DAC Combined Interpolation & on-Chip Analog FIlter Response” on page 12 – Changed A/D THD+N and Full Scale Input Voltage specs in “ADC Analog Characteristics - Commercial Grade” on page 13 and “ADC Analog Characteristics - Automotive Grade” on page 14 – Specified A/D input circuit for performance specs in “ADC Analog Characteristics - Commercial Grade” on page 13 and “ADC Analog Characteristics - Automotive Grade” on page 14 – Revised specifications in “ADC Digital Filter CharacteristicS” on page 15 – Changed PSRR spec in “DC Electrical Characteristics” on page 16 – Revised Serial Audio Port specifications and acronyms in “Switching Characteristics - Serial Audio Port” on page 17 – Replaced serial port timing diagrams with Figure 4, Figure 5, Figure 6, Figure 7 and Figure 8, revised Note 17 and Note 18. – Revised power up sequence text in “Recommended Power-Up Sequence - Access to Control Port Mode” on page 24 – Changed text in “Input Connections” on page 28 to specify maximum source impedance for A/D performance specifications in the A/D Specification Tables – Added “A/D THD+N Performance vrs. Input Source Resistance” on page 28 and “A/D Dynamic Range vrs. Input Source Resistance” on page 29 – Revised text in “Input Connections” on page 28 that describes A/D input attenuator (resistor divider) circuit –R e p l a c e d Figure 18 on page 30 – Moved Parameter Definitions to Section 10 – Moved “Filter Plots” to Section 9 and updated all plots – Moved “Package Dimensions” to Section 11 and updated dimensions data Release Changes

Contacting Cirrus Logic Support For all product questions and inquiries, contact a Cirrus Logic Sales Representative. To find the one nearest to you, go to www.cirrus.com. IMPORTANT NOTICE "Preliminary" product information describes products that are in production, but for which full characterization data is not yet available. Cirrus Logic, Inc. and its sub- sidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of re levant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this informa- tion, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROP- ERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DE- VICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER’S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICA- TIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS’ FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, the Cirrus Logic logo designs, and Popguard are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. I²C is a registered trademark of Philips Semiconductor. SPI is a trademark of Motorola, Inc.