CDB42448

Cirrus Logic

108 dB, 192 kHz 6-in, 8-out CODEC

Manufacturer: Cirrus Logic

Document: 70 Pages / 1Mb

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CS42448 CIRRUS | Alldatasheet

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Preliminary Product Information This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice. Copyright © Cirrus Logic, Inc. 2005 (All Rights Reserved) Cirrus Logic, Inc. http://www.cirrus.com

FEATURES

z Six 24-bit A/D, Eight 24-bit D/A Converters z ADC Dynamic Range – 105 dB Differential – 102 dB Single-ended z DAC Dynamic Range – 108 dB Differential – 105 dB Single-ended z ADC/DAC THD+N – -98 dB Differential – -95 dB Single-ended z Compatible with Industry-standard Time Division Multiplexed (TDM) Serial Interface z System Sampling Rates up to 192 kHz z Programmable ADC High-pass Filter for DC Offset Calibration z Logarithmic Digital Volume Control z I²C & SPI™ Host Control Port z Supports Logic Levels Between 5 V and 1.8 V z Popguard® Technology GENERAL DESCRIPTION The CS42448 CODEC provides six multi-bit analog-to-digi- tal and eight multi-bit digital-to-analog Delta-sigma converters. The CODEC is capable of operation with either differential or single-ended inputs and outputs, in a 64-pin LQFP package. Six fully differential, or single-ended, inputs are available on stereo ADC1, ADC2, and ADC3. When operating in Single- ended Mode, an internal MUX before ADC3 allows selec- tion from up to four single-ended inputs. Digital volume control is provided for each ADC channel, with selectable overflow detection. All eight DAC channels provide digital volume control and can operate with differential or single-ended outputs. An auxiliary serial input is available for an additional two channels of PCM data. The CS42448 is ideal for audio systems requiring wide dy- namic range, negligible distortion and low noise, such as A/V receivers, DVD receivers, and automotive audio systems.

ORDERING INFORMATION

See page 67. Control Port & Serial Audio Port Supply =

1.8 V to 5 V

Digital Supply =

3.3 V to 5 V

Analog Supply = ADC1&2 High Pass Filter Differential or Single-Ended Analog Inputs Digital Filters *Optional MUX allows selection from up to 4 single-ended inputs. Multibit Oversampling ADC3 High Pass Filter Digital Filters 4:2* Auxilliary Serial Audio Input Volume Controls Differential or Single-Ended Outputs Digital Filters Multibit DAC1-4 and Analog Filters Modulators Interrupt ADC Overflow & Clock Error Interrupt Level Translator I2C/SPI Software Mode Control Data CS42448 FEB ‘05 DS648PP2 108 dB, 192 kHz 6-in, 8-out CODEC

Address Bit [0]/ Chip Select (Input) - Chip address bit in I2C Mode. Control signal used to select the chip in SPI mode. AD1/CDIN Address Bit [1]/ SPI Data Input (Input) - Chip address bit in I2C Mode. Input for SPI data. RST Reset (Input) - The device enters a low power mode and all internal registers are reset to their default settings when low. VLC Control Port Power (Input) - Determines the required signal level for the control port. See “Digital I/O Pin Characteristics” on page 9. ADC_LRCK ADC Left/Right Clock (Input/Output) - Determines which channel, Left or Right, is currently active on the ADC serial audio data line. Signals the start of a new TDM frame in the TDM digital inter- face format. VD 6, 24 Digital Power (Input) - Positive terminal of the power supply for the digital section. DGND 7, 23, Digital Ground (Input) - Ground terminal of the power supply for the digital section. VLS Serial Port Interface Power (Input) - Determines the required signal level for the serial interfaces. See “Digital I/O Pin Characteristics” on page 9. ADC_SCLK ADC Serial Clock (Input/Output) - Serial clock for the ADC serial audio interface. Input frequency must be 256xFs in the TDM digital interface format. MCLK Master Clock (Input) - Clock source for the Delta-Sigma modulators and digital filters. ADC_SDOUT1 ADC_SDOUT2 ADC_SDOUT3 Serial Audio Data Output (Output) - Outputs for two’s complement serial audio data. 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 DAC_SDIN1 ADC_SCLK ADC_LRCK VLC SCL/CCLK AD1/CDIN INT VQ FILT+_ADC VD VLS MCLK DAC_SDIN4 DAC_SDIN3 DAC_SDIN2 DGND AIN1- AIN1+ MUTEC AOUT7+ AOUT7- AOUT6- AOUT6+ AOUT5+ AOUT5- 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 AOUT1- AOUT2- AOUT2+ AOUT1+ AGND VA AOUT3- AOUT4- AOUT4+ AOUT3+ AOUT8- AOUT8+ AIN5-/AIN5B AIN5+/AIN5A FILT+_DAC RST ADC_SDOUT3 ADC_SDOUT2 ADC_SDOUT1 SDA/CDOUT AD0/CS VD DGND AIN2- AIN2+ AIN6+/AIN6A AIN6-/AIN6B DAC_LRCK DAC_SCLK AUX_SCLK AUX_LRCK AUX_SDIN DGND AIN4+ AIN4- AIN3+ AIN3- VA AGND CS42448

DAC_SDIN1 DAC_SDIN2 DAC_SDIN3 DAC_SDIN4 DAC Serial Audio Data Input (Input) - Input for two’s complement serial audio data. DAC_SCLK DAC Serial Clock (Input/Output) - Serial clock for the DAC serial audio interface. Input frequency must be 256xFs in the TDM digital interface format. DAC_LRCK DAC Left/Right Clock (Input/Output) - Determines which channel, Left or Right, is currently active on the DAC serial audio data line. Signals the start of a new TDM frame in the TDM digital inter- face format. AUX_LRCK Auxiliary Left/Right Clock (Output) - Determines which channel, Left or Right, is currently active on the Auxiliary serial audio data line. Derived from the ADC serial port and equals Fs. AUX_SCLK Auxiliary Serial Clock (Output) - Serial clock for the Auxiliary serial audio interface. AUX_SDIN Auxiliary Serial Input (Input) - Provides an additional serial input for two’s complement serial audio data. Used only in the TDM digital interface format. AOUT1 +,- AOUT2 +,- AOUT3 +,- AOUT4 +,- AOUT5 +,- AOUT6 +,- 26,25 27,28 30,29 31,32 34,33 36,37 Differential Analog Output (Output) - The full-scale analog output level is specified in the Analog Characteristics table. Each leg of the differential outputs may also be used single-ended. AGND 42,56 Analog Ground (Input) - VQ Quiescent Voltage (Output) - Filter connection for internal quiescent reference voltage. VA 44,53 Analog Power (Input) - Positive power supply for the analog section. See “Digital I/O Pin Charac- teristics” on page 9. AIN1 +,- AIN2 +,- AIN3 +,- AIN4 +,- AIN5 +,- AIN6 +,- 46,45 48,47 50,49 52,51 58,57 60,59 Differential Analog Input (Input) - Signals are presented differentially or single-ended to the Delta-Sigma modulators. The full-scale input level is specified in the Analog Characteristics speci- fication table. See below for a description of AIN5-AIN6 in Single-Ended Mode. AIN5 A,B AIN6 A,B 58,57 60,59 Single-Ended Analog Input (Input) - When stereo ADC3 is in Single-Ended Mode, an internal analog mux allows selection between 2 channels for both analog inputs AIN5 and AIN6 (see sec- tion 4.2.2 for details). The unused leg of each input is internally connected to common mode. The full-scale input level is specified in the Analog Characteristics table. MUTEC Mute Control (Output) - Used as a control for external mute circuits to prevent the clicks and pops that can occur in any single supply system. FILT+_DAC Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling circuits of the DAC. FILT+_ADC Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling circuits of the ADC. INT Interrupt (Output) - Signals either an ADC overflow condition has occurred in one or more of the ADC inputs, or a clocking error has occurred in the DAC/ADC as specified in the Interrupt register. SCL/CCLK Serial Control Port Clock (Input) - Serial clock for the control port interface. SDA/CDOUT Serial Control Data I/O (Input/Output) - Input/Output for I2C data. Output for SPI data.

should adhere to the corresponding power rail and should not exceed the maximum ratings. Table 1. I/O Power Rails

See the ADC Input Filter section in the Appendix.
See the DAC Output Filter section in the Appendix.

Figure 1. Typical Connection Diagram

CHARACTERISTICS AND SPECIFICATIONS (All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical per- formance characteristics and specifications are derived from measurements taken at nominal supply voltages and TA = 25° C.) SPECIFIED OPERATING CONDITIONS (AGND=DGND=0 V, all voltages with respect to ground.) ABSOLUTE MAXIMUM RATINGS (AGND = DGND = 0 V; all voltages with respect to ground.) WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. Notes: Analog input/output performance will slightly degrade at VA = 3.3 V. The ADC_SDOUT may not meet timing requirements in TDM, Double-Speed Mode. Any pin except supplies. Transient currents of up to ±100 mA on the analog input pins will not cause SCR latch-up. The maximum over/under voltage is limited by the input current. Parameters Symbol Min Typ Max Units DC Power Supply Analog 3.3 V (Note 1) 5.0 V VA 3.14 4.75 3.3 3.47 5.25 V V Digital 3.3 V 5.0 V VD 3.14 4.75 3.3 3.47 5.25 V V Serial Audio Interface

1.8 V (Note 2)

2.5 V 3.3 V 5.0 V VLS 1.71 2.37 3.14 4.75 1.8 2.5 3.3 1.89 2.63 3.47 5.25 V V V V Control Port Interface 1.8 V 2.5 V 3.3 V 5.0 V VLC 1.71 2.37 3.14 4.75 1.8 2.5 3.3 1.89 2.63 3.47 5.25 V V V V Ambient Temperature Commercial -CQZ Automotive -DQZ TA -10 -40 +70 +85 Parameters Symbol Min Max Units DC Power Supply Analog Digital Serial Port Interface Control Port Interface VA VD VLS VLC -0.3 -0.3 -0.3 -0.3 6.0 6.0 6.0 6.0 V V V V Input Current (Note 3) Iin ±10 mA Analog Input Voltage (Note 4) VIN AGND-0.7 VA+0.7 V Digital Input Voltage Serial Port Interface (Note 4) Control Port Interface VIND-S VIND-C -0.3 -0.3 VLS+ 0.4 VLC+ 0.4 V V Ambient Operating Temperature CS42448-CQZ (power applied) CS42448-DQZ TA -20 -50 +85 +95 Storage Temperature Tstg -65 +150

ANALOG INPUT CHARACTERISTICS (CS42448-CQZ) (Test Conditions (unless otherwise specified): VLS = VLC = VD = 3.3 V, VA = 5 V; Full scale input sine wave: 1 kHz through the active input filter on page 56; Measurement Bandwidth is 10 Hz to 20 kHz unless otherwise specified.) Differential Single-Ended Parameter Min Typ Max Min Typ Max Unit Single Speed Mode Fs=48 kHz Dynamic Range A-weighted unweighted 105 102 102 dB dB Total Harmonic Distortion + Noise -1 dB (Note 5) -20 dB -60 dB -98 -82 -42 -92 -95 -79 -39 -89 dB dB dB Double Speed Mode Fs=96 kHz Dynamic Range A-weighted unweighted 40 kHz bandwidth unweighted 105 102 102 dB dB dB Total Harmonic Distortion + Noise -1 dB (Note 5) -20 dB -60 dB 40 kHz bandwidth -1 dB -98 -82 -42 -90 -92 -95 -79 -39 -90 -89 dB dB dB dB Quad Speed Mode Fs=192 kHz Dynamic Range A-weighted unweighted 40 kHz bandwidth unweighted 105 102 102 dB dB dB Total Harmonic Distortion + Noise -1 dB (Note 5) -20 dB -60 dB 40 kHz bandwidth -1 dB -98 -82 -42 -87 -92 -95 -79 -39 -87 -89 dB dB dB dB All Speed Modes ADC1-3 Interchannel Isolation dB ADC3 MUX Interchannel Isolation dB DC Accuracy Interchannel Gain Mismatch 0.1 0.1 dB Gain Drift ±100 ±100 ppm/°C Analog Input Full-scale Input Voltage 1.06*VA 1.12*VA 1.18*VA 0.53*VA 0.56*VA 0.59*VA Vpp Differential Input Impedance (Note 6) kΩ Single-Ended Input Impedance (Note 7) kΩ Common Mode Rejection Ratio (CMRR) dB

ANALOG INPUT CHARACTERISTICS (CS42448-DQZ) (Test Conditions (unless otherwise specified):VLS = VLC = VD = 3.3 V, VA = 5 V; Full scale input sine wave: 1 kHz through the active input filter on page 56; Measurement Bandwidth is 10 Hz to 20 kHz unless otherwise specified.) Notes: Referred to the typical full-scale voltage. Measured between AINx+ and AINx-. Measured between AINxx and AGND. Differential Single-Ended Parameter Min Typ Max Min Typ Max Unit Single Speed Mode Fs=48 kHz Dynamic Range A-weighted unweighted 105 102 102 dB dB Total Harmonic Distortion + Noise -1 dB (Note 5) -20 dB -60 dB -98 -82 -42 -90 -95 -79 -39 -87 dB dB dB Double Speed Mode Fs=96 kHz Dynamic Range A-weighted unweighted 40 kHz bandwidth unweighted 105 102 102 dB dB dB Total Harmonic Distortion + Noise -1 dB (Note 5) -20 dB -60 dB 40 kHz bandwidth -1 dB -98 -82 -42 -87 -90 -95 -79 -39 -87 -87 dB dB dB dB Quad Speed Mode Fs=192 kHz Dynamic Range A-weighted unweighted 40 kHz bandwidth unweighted 105 102 102 dB dB dB Total Harmonic Distortion + Noise -1 dB (Note 5) -20 dB -60 dB 40 kHz bandwidth -1 dB -98 -82 -42 -87 -90 -95 -79 -39 -87 -87 dB dB dB dB All Speed Modes ADC1-3 Interchannel Isolation dB ADC3 MUX Interchannel Isolation dB DC Accuracy Interchannel Gain Mismatch 0.1 0.1 dB Gain Drift ±100 ±100 ppm/°C Analog Input Full-scale Input Voltage 1.04*VA 1.12*VA 1.20*VA 0.52*VA 0.56*VA 0.60*VA Vpp Differential Input Impedance (Note 6) kΩ Single-Ended Input Impedance (Note 7) kΩ Common Mode Rejection Ratio (CMRR) dB

ADC DIGITAL FILTER CHARACTERISTICS Notes: Filter response is guaranteed by design. Response is clock dependent and will scale with Fs. Note that the response plots (Figures 32 to 43) have been normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs. Parameter (Note 8, 9) Min Typ Max Unit Single Speed Mode (Note 9) Passband (Frequency Response) to -0.1 dB corner 0.4896 Fs Passband Ripple 0.08 dB Stopband 0.5688 Fs Stopband Attenuation dB Total Group Delay 12/Fs s Double Speed Mode (Note 9) Passband (Frequency Response) to -0.1 dB corner 0.4896 Fs Passband Ripple 0.16 dB Stopband 0.5604 Fs Stopband Attenuation dB Total Group Delay 9/Fs s Quad Speed Mode (Note 9) Passband (Frequency Response) to -0.1 dB corner 0.2604 Fs Passband Ripple 0.16 dB Stopband 0.5000 Fs Stopband Attenuation dB Total Group Delay 5/Fs s High Pass Filter Characteristics Frequency Response -3.0 dB -0.13 dB Hz Hz Phase Deviation @ 20 Hz Deg Passband Ripple dB Filter Settling Time 105/Fs s

ANALOG OUTPUT CHARACTERISTICS (CS42448-CQZ) (Test Conditions (unless otherwise specified):VLS = VLC = VD = 3.3 V, VA = 5 V; Measurement Bandwidth is 10 Hz to 20 kHz unless otherwise specified; Full scale 997 Hz output sine wave (see Note 11); Single-ended test load: RL = 3 kΩ, CL = 10 pF.) Parameter Differential Min Typ Max Single-Ended Min Typ Max Unit Single-Speed Mode Fs = 48 kHz Dynamic Range 18 to 24-Bit A-weighted unweighted 16-Bit A-weighted unweighted 102 108 105 105 102 dB dB dB dB Total Harmonic Distortion + Noise 18 to 24-Bit 0 dB -20 dB -60 dB 16-Bit 0 dB -20 dB -60 dB -98 -85 -45 -93 -76 -36 -92 -95 -82 -42 -90 -73 -33 -89 dB dB dB dB dB dB Double-Speed Mode Fs = 96 kHz Dynamic Range 18 to 24-Bit A-weighted unweighted 16-Bit A-weighted unweighted 102 108 105 105 102 dB dB dB dB Total Harmonic Distortion + Noise 18 to 24-Bit 0 dB -20 dB -60 dB 16-Bit 0 dB -20 dB -60 dB -98 -85 -45 -93 -76 -36 -92 -95 -82 -42 -90 -73 -33 -89 dB dB dB dB dB dB Quad-Speed Mode Fs = 192 kHz Dynamic Range 18 to 24-Bit A-weighted unweighted 16-Bit A-weighted unweighted 102 108 105 105 102 dB dB dB dB Total Harmonic Distortion + Noise 18 to 24-Bit 0 dB -20 dB -60 dB 16-Bit 0 dB -20 dB -60 dB -98 -85 -45 -93 -76 -36 -92 -95 -82 -42 -90 -73 -33 -89 dB dB dB dB dB dB

Interchannel Isolation (1 kHz) 100 100 dB Analog Output Full Scale Output 1.235•VA 1.300•VA 1.365•VA 0.618•VA 0.650•VA 0.683•VA Vpp Interchannel Gain Mismatch 0.1 0.25 0.1 0.25 dB Gain Drift ±100 ±100 ppm/°C Output Impedance 100 100 Ω DC Current draw from an AOUT pin (Note 10) µA AC-Load Resistance (RL) (Note 12) kΩ Load Capacitance (CL) (Note 12) 100 100 pF

ANALOG OUTPUT CHARACTERISTICS (CS42448-DQZ) (Test Conditions (unless otherwise specified): VLS = VLC = VD = 3.3 V, VA = 5 V; Measurement Bandwidth is 10 Hz to 20 kHz unless otherwise specified; Full scale 997 Hz output sine wave (see Note 11); Single-ended test load: RL = 3 kΩ, CL = 10 pF.) Parameter Differential Min Typ Max Single-Ended Min Typ Max Unit Single-Speed Mode Fs = 48 kHz Dynamic Range 18 to 24-Bit A-weighted unweighted 16-Bit A-weighted unweighted 100 108 105 105 102 dB dB dB dB Total Harmonic Distortion + Noise 18 to 24-Bit 0 dB -20 dB -60 dB 16-Bit 0 dB -20 dB -60 dB -98 -85 -45 -93 -76 -36 -90 -95 -82 -42 -90 -73 -33 -87 dB dB dB dB dB dB Double-Speed Mode Fs = 96 kHz Dynamic Range 18 to 24-Bit A-weighted unweighted 16-Bit A-weighted unweighted 100 108 105 105 102 dB dB dB dB Total Harmonic Distortion + Noise 18 to 24-Bit 0 dB -20 dB -60 dB 16-Bit 0 dB -20 dB -60 dB -98 -85 -45 -93 -76 -36 -90 -95 -82 -42 -90 -73 -33 -87 dB dB dB dB dB dB Quad-Speed Mode Fs = 192 kHz Dynamic Range 18 to 24-Bit A-weighted unweighted 16-Bit A-weighted unweighted 100 108 105 105 102 dB dB dB dB Total Harmonic Distortion + Noise 18 to 24-Bit 0 dB -20 dB -60 dB 16-Bit 0 dB -20 dB -60 dB -98 -85 -45 -93 -76 -36 -90 -95 -82 -42 -90 -73 -33 -87 dB dB dB dB dB dB

COMBINED DAC INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE Notes: 13. Response is clock dependent and will scale with Fs. Note that the response plots (Figures 44 to 55) have been normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs. 14. Single and Double Speed Mode Measurement Bandwidth is from Stopband to 3 Fs. Quad Speed Mode Measurement Bandwidth is from Stopband to 1.34 Fs. 15. De-emphasis is only available in Single Speed Mode. Parameter (Note 8, 13) Min Typ Max Unit Single Speed Mode Passband (Frequency Response) to -0.05 dB corner to -3 dB corner 0.4780 0.4996 Fs Fs Frequency Response 10 Hz to 20 kHz -0.2 +0.08 dB StopBand 0.5465 Fs StopBand Attenuation (Note 14) dB Group Delay 10/Fs s De-emphasis Error (Note 15) Fs = 32 kHz Fs = 44.1 kHz Fs = 48 kHz +1.5/+0 +0.05/-0.25 -0.2/-0.4 dB dB dB Double Speed Mode Passband (Frequency Response) to -0.1 dB corner to -3 dB corner 0.4650 0.4982 Fs Fs Frequency Response 10 Hz to 20 kHz -0.2 +0.7 dB StopBand 0.5770 Fs StopBand Attenuation (Note 14) dB Group Delay 5/Fs s Quad Speed Mode Passband (Frequency Response) to -0.1 dB corner to -3 dB corner 0.397 0.476 Fs Fs Frequency Response 10 Hz to 20 kHz -0.2 +0.05 dB StopBand 0.7 Fs StopBand Attenuation (Note 14) dB Group Delay 2.5/Fs s

After powering up the CS42448, RST should be held low after the power supplies and clocks are settled. See Table 10 on page 46 and Table 11 on page 47 for suggested MCLK frequencies. When operating in TDM interface format, VLS is limited to nominal 2.5 V to 5.0 V operation only. and Time Division Multiplexed interface formats only. “LRCK” and “SCLK” shall refer to the ADC and DAC left/right clock and serial clock, respectively. Figure 6. Serial Audio Interface Master Mode Timing

Figure 7. Serial Audio Interface Slave Mode Timing

Data must be held for sufficient time to bridge the transition time, tfc, of SCL. Figure 8. Control Port Timing - I²C Format

Data must be held for sufficient time to bridge the transition time of CCLK. Figure 9. Control Port Timing - SPI Format

DC ELECTRICAL CHARACTERISTICS (AGND = 0 V; all voltages with respect to ground.) Notes: 25. Normal operation is defined as RST = HI with a 997 Hz, 0 dBFS input to the DAC and AUX port, and a 1 kHz, -1 dB analog input to the ADC port sampled at the highest Fs for each speed mode. DAC outputs are open, unless otherwise specified. 26. IDT measured with no external loading on pin 64 (SDA). 27. Valid with the recommended capacitor values on FILT+ and VQ. Increasing the capacitance will also increase the PSRR. 28. Power Down Mode is defined as RST = LO with all clocks and data lines held static and no analog input. 29. Guaranteed by design. The DC current draw represents the allowed current draw from the VQ pin due to typical leakage through the electrolytic de-coupling capacitors. DIGITAL INTERFACE SPECIFICATIONS & CHARACTERISTICS Notes: 30. See “Digital I/O Pin Characteristics” on page 9 for serial and control port power rails. Parameters Symbol Min Typ Max Units Normal Operation (Note 25) Power Supply Current VA = 5.0 V VLS = VLC = VD = 3.3 V (Note 26) IA IDT 60.6 mA mA Power Dissipation All Supplies = 5 V 600 850 mW Power Supply Rejection Ratio 1 kHz (Note 27) 60 Hz PSRR dB dB Power-down Mode (Note 28) Power Dissipation All Supplies = VA = 5 V 1.25 mW VQ Characteristics Nominal Voltage Output Impedance DC current source/sink (Note 29) 0.5•VA V kΩ µA FILT+_ADC Nominal Voltage FILT+_DAC Nominal Voltage VA VA V V Parameters (Note 30) Symbol Min Typ Max Units High-Level Output Voltage at Io=2 mA Serial Port Control Port MUTEC VOH VLS-1.0 VLC-1.0 VA-1.0 V V V Low-Level Output Voltage at Io=2 mA Serial Port Control Port MUTEC VOL 0.4 0.4 0.4 V V V High-Level Input Voltage Serial Port Control Port VIH 0.7xVLS 0.7xVLC V V Low-Level Input Voltage Serial Port Control Port VIL 0.2xVLS 0.2xVLC V V Input Leakage Current Iin ±10 µA Input Capacitance (Note 22) pF MUTEC Drive Current mA

on page 49 for all bit selections. Refer to Figure 11 on page 27 for the internal ADC3 analog input topology. 4.2.3 High Pass Filter and DC Offset Calibration The high pass filter continuously subtracts a measure of the DC offset from the output of the dec- imation filter. If the high pass filter is disabled during normal operation, the current value of the DC offset for the corresponding channel is frozen and this DC offset will continue to be subtract- ed from the conversion result. This feature makes it possible to perform a system DC offset cal- ibration by: 1) Running the CS42448 with the high pass filter enabled until the filter settles. See the Digital Filter Characteristics for filter settling time. 2) Disabling the high pass filter and freezing the stored DC offset. The high pass filter for ADC1/ADC2 can be enabled and disabled. The high pass filter for ADC3 can be independently enabled and disabled. The high pass filters are controlled using the HPF_FREEZE bit in the register “ADC Control & DAC De-emphasis (address 05h)” on page 49. 4.3 Analog Outputs 4.3.1 Initialization The initialization and Power-Down sequence flow chart is shown in Figure 12 on page 29. The CS42448 enters a Power-Down state upon initial power-up. The interpolation & decimation fil- ters, delta-sigma modulators and control port registers are reset. The internal voltage reference, multi-bit digital-to-analog and analog-to-digital converters and switched-capacitor low-pass fil- ters are powered down. The device will remain in the Power-Down state until the RST pin is brought high. The control port is accessible once RST is high and the desired register settings can be loaded per the in- terface descriptions in the “Control Port Description and Timing” on page 38. Once MCLK is valid, VQ will ramp up to VA/2, and the internal voltage references, FILT+_ADC and FILT+_DAC, will begin powering up to normal operation. Power is applied to the D/A convert- ers and switched-capacitor filters, and the analog outputs are clamped to the quiescent voltage, VQ. Once LRCK is valid, MCLK occurrences are counted over one LRCK period to determine the MCLK/LRCK frequency ratio. After an approximate 2000 sample period delay, normal opera- tion begins. 4.3.2 Output Transient Control The CS42448 uses Popguard® technology to minimize the effects of output transients during power-up and power-down. This technique eliminates the audio transients commonly produced by single-ended single-supply converters when it is implemented with external DC-blocking ca- pacitors connected in series with the audio outputs. To make best use of this feature, it is nec- essary to understand its operation. See “Popguard®” on page 30 for details. A Mute Control pin is also available for use with an optional mute circuit to mask output tran- sients on the analog outputs. See “Mute Control” on page 30 for details. When changing clock ratio or sample rate it is recommended that zero data (or near zero data) be present on DAC_SDINx for at least 10 LRCK samples before the change is made. During the clocking change the DAC outputs will always be in a zero data state. If no zero audio is present at the time of switching, a slight click or pop may be heard as the DAC output automatically goes to it’s zero data state.

No audio signal generated.
Control Port Registers reset

Hardware Mode not supported.

Audio signal generated per register settings.
Aout bias = VQ + last audio sample.
DAC Modulators stop operation.
No audio signal generated.
No audio signal generated.
Control Port Registers retain

2000 LRCK delay

Figure 12. Audio Output Initialization Flow Chart

4.3.3 Popguard® 4.3.3a Power-up When the device is initially powered-up, the audio outputs, AOUTxx, are clamped to VQ which is initially low. After the RST pin is brought high and MCLK is applied, the outputs begin to ramp with VQ towards the nominal quiescent voltage. This ramp takes approx- imately 400 ms to complete. The gradual voltage ramping allows time for the external DC-blocking capacitors to charge to VQ, effectively blocking the quiescent DC voltage. Once valid DAC_LRCK, DAC_SCLK and DAC_SDINx are applied, audio output begins approximately 2000 sample periods later. 4.3.3b Power-down To prevent audio transients at power-down the DC-blocking capacitors must fully dis- charge before turning off the power. In order to do this, the PDN bit in register “Power Control (address 02h)” on page 45 must be set to ‘1’ for a period of about 250 ms before removing power. During this time, voltage on VQ and the audio outputs discharge grad- ually to AGND. If power is removed before this 250 ms time period has passed a tran- sient will occur when the VA supply drops below that of VQ. There is no minimum time for a power cycle. Power may be re-applied at any time. 4.3.4 Mute Control The Mute Control pin, MUTEC, is typically connected to an external mute control circuit. The use of external mute circuits is not mandatory but may be desired for designs requiring the absolute minimum in extraneous clicks and pops. MUTEC is in high impedance mode during power up or when the CS42448 is in power down mode by setting the PDN bit in the register “Power Control (address 02h)” on page 45 to a ‘1’. Once out of power-down mode the pin can be controlled by the user via the control port (see “MUTEC Pin Control (address 1Bh)” on page 55), or automatically asserted to the active state when zero data is present on all DAC inputs, when all DAC outputs are muted or when serial port clock errors occur. To prevent large transients on the output, it is recommended to mute the DAC outputs before the Mute Control pin is asserted. 4.3.5 Line-level Outputs and Filtering The CS42448 contains on-chip buffer amplifiers capable of producing line level differential as well as single-ended outputs on AOUT1-AOUT8. These amplifiers are biased to a quiescent DC level of approximately VQ. The delta-sigma conversion process produces high frequency noise beyond the audio pass- band, most of which is removed by the on-chip analog filters. The remaining out-of-band noise can be attenuated using an off-chip low pass filter. See “DAC Output Filter” on page 59 for recommended output filter. The active filter configuration accounts for the normally differing AC loads on the AOUTx+ and AOUTx- differential output pins. Also shown is a passive filter configuration which minimizes costs and the number of compo- nents. Figure 13 shows the full-scale analog output levels. All outputs are internally biased to VQ, ap- proximately VA/2.

be an integer multiple of, and synchronous with, the system sample rate, Fs. for required clock ratios. The SCLK to sample rate (LRCK) ratios are shown in Tables 5 - 8. Table 2. Single-Speed Mode Common Frequencies Table 3. Double-Speed Mode Common Frequencies Table 4. Quad-Speed Mode Common Frequencies

Table 5. I²S, LJ, RJ Clock Ratios Table 6. OLM#1 Clock Ratios Table 7. OLM#2 Clock Ratios Table 8. TDM Clock Ratios

Table 9. Serial Audio Interface Channel Allocations

Send MAP byte, auto increment off. Receive acknowledge bit. Send stop condition, aborting write. Send start condition. Send 10010xx1(chip address & read operation). Receive acknowledge bit. Receive byte, contents of selected register. Send acknowledge bit. Send stop condition. Setting the auto-increment bit in the MAP allows successive reads or writes of consecutive reg- isters. Each byte is separated by an acknowledge bit. 4.8 Interrupts The CS42448 has a comprehensive interrupt capability. The INT output pin is intended to drive the inter- rupt input pin on the host microcontroller. The INT pin may be configured as an active low or active high CMOS driver or an open-drain driver. This last mode is used for active low, wired-OR hook-ups, with mul- tiple peripherals connected to the microcontroller interrupt input pin. Many conditions can cause an interrupt, as listed in the interrupt status register descriptions. See “Status (address 19h) (Read Only)” on page 54. Each source may be masked off through mask register bits. In addition, each source may be set to rising edge, falling edge, or level sensitive. Combined with the option of level sensitive or edge sensitive modes within the microcontroller, many different configurations are possible, depending on the needs of the system designer. 4.9 Recommended Power-up Sequence 1) Hold RST low until the power supply is stable. In this state, the control port is reset to its de- fault settings and VQ will remain low. 2) Bring RST high. The device will initially be in a low power state with VQ low. All features will default as described in the “Register Quick Reference” on page 42. 3) Perform a write operation to the Power Control register (“Power Control (address 02h)” on page 45) to set bit 0 to a ‘1’b. This will place the device in a power down state. 4) Load the desired register settings while keeping the PDN bit set to ‘1’b. 5) Start MCLK to the appropriate frequency, as discussed in section 4.4 on page 32. The device will initiate the power up sequence. 6) Set the PDN bit in the power control register to ‘0’b. VQ will ramp to approximately VA/2 ac- cording to the Popguard® specification in section Note 4.3.3 on page 30. 7) Apply ADC/DAC_LRCK, ADC/DAC_SCLK and DAC_SDINx. Following approximately 2000 sample periods, the device is initialized and ready for normal operation. 4.10 Reset and Power-up It is recommended that reset be activated if the analog or digital supplies drop below the recommended operating condition to prevent power glitch related issues. The delta-sigma modulators settle in a matter of microseconds after the analog section is powered, either through the application of power or by setting the RST pin high. However, the voltage reference will take much longer to reach a final value due to the presence of external capacitance on the ADC/DAC_FILT+

pins. A time delay of approximately 400 ms is required after applying power to the device or after exiting a reset state. During this voltage reference ramp delay, all serial ports and DAC outputs will be automat- ically muted. 4.11 Power Supply, Grounding, and PCB layout As with any high resolution converter, the CS42448 requires careful attention to power supply and ground- ing arrangements if its potential performance is to be realized. Figure 1 shows the recommended power arrangements, with VA connected to clean supplies. VD, which powers the digital circuitry, may be run from the system logic supply. Alternatively, VD may be powered from the analog supply via a ferrite bead. In this case, no additional devices should be powered from VD. Extensive use of power and ground planes, ground plane fill in unused areas and surface mount decou- pling capacitors are recommended. Decoupling capacitors should be as near to the pins of the CS42448 as possible. The low value ceramic capacitor should be the nearest to the pin and should be mounted on the same side of the board as the CS42448 to minimize inductance effects. All signals, especially clocks, should be kept away from the ADC/DAC_FILT+, VQ pins in order to avoid unwanted coupling into the modulators. The ADC/DAC_FILT+ and VQ decoupling capacitors, particularly the 0.1 µF, must be posi- tioned to minimize the electrical path from ADC/DAC_FILT+ and AGND. The CDB42448 evaluation board demonstrates the optimum layout and power supply arrangements. For optimal heat dissipation from the package, it is recommended that the area directly under the part be filled with copper and tied to the ground plane. The use of vias connecting the topside ground to the back- side ground is also recommended.

NOTE: The default value in all “Reserved” registers must be preserved. Addr Function 01h ID Chip_ID3 Chip_ID2 Chip_ID1 Chip_ID0 Rev_ID3 Rev_ID2 Rev_ID1 Rev_ID0 p 44 default 02h Power Con- trol PDN_ADC3 PDN_ADC2 PDN_ADC1 PDN_DAC4 PDN_DAC3 PDN_DAC2 PDN_DAC1 PDN p 45 default 03h Functional Mode DAC_FM1 DAC_FM0 ADC_FM1 ADC_FM0 MFreq2 MFreq1 MFreq0 Reserved p 46 default 04h Interface Formats FREEZE AUX_DIF DAC_DIF2 DAC_DIF1 DAC_DIF0 ADC_DIF2 ADC_DIF1 ADC_DIF0 p 47 default 05h ADC Control (w/DAC_DEM) ADC1-2_HPF FREEZE ADC3_HPF FREEZE DAC_DEM ADC1 SINGLE ADC2 SINGLE ADC3 SINGLE AIN5_MUX AIN6_MUX p 49 default 06h Transition Control DAC_SNG VOL DAC_SZC1 DAC_SZC0 AMUTE MUTE ADC_SP ADC_SNG VOL ADC_SZC1 ADC_SZC0 p 50 default 07h Channel Mute AOUT8 MUTE AOUT7 MUTE AOUT6 MUTE AOUT5 MUTE AOUT4 MUTE AOUT3 MUTE AOUT2 MUTE AOUT1 MUTE p 52 default 08h Vol. Control AOUT1 AOUT1 VOL7 AOUT1 VOL6 AOUT1 VOL5 AOUT1 VOL4 AOUT1 VOL3 AOUT1 VOL2 AOUT1 VOL1 AOUT1 VOL0 p 52 default 09h Vol. Control AOUT2 AOUT2 VOL7 AOUT2 VOL6 AOUT2 VOL5 AOUT2 VOL4 AOUT2 VOL3 AOUT2 VOL2 AOUT2 VOL1 AOUT2 VOL0 p 52 default 0Ah Vol. Control AOUT3 AOUT3 VOL7 AOUT3 VOL6 AOUT3 VOL5 AOUT3 VOL4 AOUT3 VOL3 AOUT3 VOL2 AOUT3 VOL1 AOUT3 VOL0 p 52 default 0Bh Vol. Control AOUT4 AOUT4 VOL7 AOUT4 VOL6 AOUT4 VOL5 AOUT4 VOL4 AOUT4 VOL3 AOUT4 VOL2 AOUT4 VOL1 AOUT4 VOL0 p 52 default 0Ch Vol. Control AOUT5 AOUT5 VOL7 AOUT5 VOL6 AOUT5 VOL5 AOUT5 VOL4 AOUT5 VOL3 AOUT5 VOL2 AOUT5 VOL1 AOUT5 VOL0 p 52 default 0Dh Vol. Control AOUT6 AOUT6 VOL7 AOUT6 VOL6 AOUT6 VOL5 AOUT6 VOL4 AOUT6 VOL3 AOUT6 VOL2 AOUT6 VOL1 AOUT6 VOL0 p 52 default 0Eh Vol. Control AOUT7 AOUT7 VOL7 AOUT7 VOL6 AOUT7 VOL5 AOUT7 VOL4 AOUT7 VOL3 AOUT7 VOL2 AOUT7 VOL1 AOUT7 VOL0 p 52 default 0Fh Vol. Control AOUT8 AOUT8 VOL7 AOUT8 VOL6 AOUT8 VOL5 AOUT8 VOL4 AOUT8 VOL3 AOUT8 VOL2 AOUT8 VOL1 AOUT8 VOL0 p 52 default 10h DAC Chan- nel Invert INV_AOUT8 INV_AOUT7 INV_AOUT6 INV_AOUT5 INV_AOUT4 INV_AOUT3 INV_AOUT2 INV_AOUT1 p 53 default

Vol. Control AIN1 AIN1 VOL7 AIN1 VOL6 AIN1 VOL5 AIN1 VOL4 AIN1 VOL3 AIN1 VOL2 AIN1 VOL1 AIN1 VOL0 p 52 default 12h Vol. Control AIN2 AIN2 VOL7 AIN2 VOL6 AIN2 VOL5 AIN2 VOL4 AIN2 VOL3 AIN2 VOL2 AIN2 VOL1 AIN2 VOL0 p 53 default 13h Vol. Control AIN3 AIN3 VOL7 AIN3 VOL6 AIN3 VOL5 AIN3 VOL4 AIN3 VOL3 AIN3 VOL2 AIN3 VOL1 AIN3 VOL0 p 52 default 14h Vol. Control AIN4 AIN4 VOL7 AIN4 VOL6 AIN4 VOL5 AIN4 VOL4 AIN4 VOL3 AIN4 VOL2 AIN4 VOL1 AIN4 VOL0 p 53 default 15h Vol. Control AIN5 AIN5 VOL7 AIN5 VOL6 AIN5 VOL5 AIN5 VOL4 AIN5 VOL3 AIN5 VOL2 AIN5 VOL1 AIN5 VOL0 p 52 default 16h Vol. Control AIN6 AIN6 VOL7 AIN6 VOL6 AIN6 VOL5 AIN6 VOL4 AIN6 VOL3 AIN6 VOL2 AIN6 VOL1 AIN6 VOL0 p 53 default 17h ADC Chan- nel Invert Reserved Reserved INV_A6 INV_A5 INV_A4 INV_A3 INV_A2 INV_A1 p 53 default 18h Status Con- trol Reserved Reserved Reserved Reserved INT1 INT0 Reserved Reserved p 54 default 19h Status Reserved Reserved Reserved DAC_CLK Error ADC_CLK Error ADC3 OVFL ADC2 OVFL ADC1 OVFL p 54 default X X X X X 1Ah Status Mask Reserved Reserved Reserved DAC_CLK Error_M ADC_CLK Error_M ADC3 OVFL_M ADC2 OVFL_M ADC1 OVFL_M p 55 default 1Bh MUTEC Reserved Reserved Reserved Reserved Reserved Reserved MCPolarity MUTEC Active p 55 default Addr Function

All registers are read/write except for the I.D. and Revision Register and Interrupt Status Register which are read only. See the following bit definition tables for bit assignment information. The default state of each bit after a power-up sequence or reset is listed in each bit description. 6.1 MEMORY ADDRESS POINTER (MAP) Not a register 6.1.1 INCREMENT(INCR) Default = 1 Function: Memory address pointer auto increment control 0 - MAP is not incremented automatically. 1 - Internal MAP is automatically incremented after each read or write. 6.1.2 MEMORY ADDRESS POINTER (MAP[6:0]) Default = 0000001 Function: Memory address pointer (MAP). Sets the register address that will be read or written by the control port. 6.2 CHIP I.D. AND REVISION REGISTER (ADDRESS 01H) (READ ONLY) 6.2.1 CHIP I.D. (CHIP_ID[3:0]) Default = 0001 Function: I.D. code for the CS42448. Permanently set to 0001. 6.2.2 CHIP REVISION (REV_ID[3:0]) Default = 0001 Function: CS42448 revision level. Revision A is coded as 0001. INCR MAP6 MAP5 MAP4 MAP3 MAP2 MAP1 MAP0 Chip_ID3 Chip_ID2 Chip_ID1 Chip_ID0 Rev_ID3 Rev_ID2 Rev_ID1 Rev_ID0

6.3 POWER CONTROL (ADDRESS 02H) 6.3.1 POWER DOWN ADC PAIRS(PDN_ADCX) Default = 0 0 - Disable 1 - Enable Function: When enabled, the respective ADC channel pair (ADC1 - AIN1/AIN2; ADC2 - AIN3/AIN4; and ADC3 - AIN5/AIN6) will remain in a reset state. 6.3.2 POWER DOWN DAC PAIRS (PDN_DACX) Default = 0 0 - Disable 1 - Enable Function: When enabled, the respective DAC channel pair (DAC1 - AOUT1/AOUT2; DAC2 - AOUT3/AOUT4; DAC3 - AOUT5/AOUT6; and DAC4 - AOUT7/AOUT8) will remain in a reset state. It is advised that any change of these bits be made while the DACs are muted or the power down bit (PDN) is enabled to eliminate the possibility of audible artifacts. 6.3.3 POWER DOWN (PDN) Default = 0 0 - Disable 1 - Enable Function: The entire device will enter a low-power state when this function is enabled. The contents of the con- trol registers are retained in this mode. PDN_ADC3 PDN_ADC2 PDN_ADC1 PDN_DAC4 PDN_DAC3 PDN_DAC2 PDN_DAC1 PDN

6.4 FUNCTIONAL MODE (ADDRESS 03H) 6.4.1 DAC FUNCTIONAL MODE (DAC_FM[1:0]) Default = 11 Master Mode 00 - Single-Speed Mode (4 to 50 kHz sample rates) 01 - Double-Speed Mode (50 to 100 kHz sample rates) 10 - Quad-Speed Mode (100 to 200 kHz sample rates) Slave Mode 11 - (Auto-detect sample rates) Function: Selects the required range of sample rates for the DAC serial port. 6.4.2 ADC FUNCTIONAL MODE (ADC_FM[1:0]) Default = 11 Master Mode 00 - Single-Speed Mode (4 to 50 kHz sample rates) 01 - Double-Speed Mode (50 to 100 kHz sample rates) 10 - Quad-Speed Mode (100 to 200 kHz sample rates) Slave Mode 11 - (Auto-detect sample rates) Function: Selects the required range of sample rates for the ADC serial port. 6.4.3 MCLK FREQUENCY (MFREQ[2:0]) Default = 000 Function: Sets the appropriate frequency for the supplied MCLK. For TDM and OLM #2 operation, ADC/DAC_SCLK must equal 256Fs. For OLM #1 operation, ADC/DAC_SCLK must equal 128Fs. MCLK can be equal to or greater than the higher frequency of ADC_SCLK or DAC_SCLK. DAC_FM1 DAC_FM0 ADC_FM1 ADC_FM0 MFreq2 MFreq1 MFreq0 Reserved Ratio (xFs) MFreq2 MFreq1 MFreq0

Description

1.0290 MHz to 12.8000 MHz 256 128 1.5360 MHz to 19.2000 MHz 384 192 2.0480 MHz to 25.6000 MHz 512 256 128 3.0720 MHz to 38.4000 MHz 768 384 192 X X 4.0960 MHz to 51.2000 MHz 1024 512 256 Table 10. MCLK Frequency Settings for I²S, Left and Right Justified Interface Formats

6.5 INTERFACE FORMATS (ADDRESS 04H) 6.5.1 FREEZE CONTROLS (FREEZE) Default = 0 Function: This function will freeze the previous settings of, and allow modifications to be made to the channel mutes, the DAC and ADC Volume Control/Channel Invert registers without the changes taking effect until the FREEZE is disabled. To have multiple changes in these control port registers take effect si- multaneously, enable the FREEZE bit, make all register changes, then disable the FREEZE bit. 6.5.2 AUXILIARY DIGITAL INTERFACE FORMAT (AUX_DIF) Default = 0 0 - Left Justified 1 - I²S Function: This bit selects the digital interface format used for the AUX Serial Port. The required relationship be- tween the Left/Right clock, serial clock and serial data is defined by the Digital Interface Format and the options are detailed in Figures 21-22. 6.5.3 DAC DIGITAL INTERFACE FORMAT (DAC_DIF[2:0]) Default = 110 Function: These bits select the digital interface format used for the DAC Serial Port. The required relationship be- tween the Left/Right clock, serial clock and serial data is defined by the Digital Interface Format and the options are detailed in the section “CODEC Digital Interface Formats” on page 32. Refer to Table 9. “Serial Audio Interface Channel Allocations” on page 36. Ratio (xFs) MFreq2 MFreq1 MFreq0 1.0290 MHz to 12.8000 MHz 256 N/A N/A 1.5360 MHz to 19.2000 MHz 384 N/A N/A 2.0480 MHz to 25.6000 MHz 512 256 N/A 3.0720 MHz to 38.4000 MHz 768 384 N/A X X 4.0960 MHz to 51.2000 MHz 1024 512 256 Table 11. MCLK Frequency Settings for TDM & OLM Interface Formats

6.5.4 ADC DIGITAL INTERFACE FORMAT (ADC_DIF[2:0]) Default = 110 Function: These bits select the digital interface format used for the ADC serial port. The required relationship be- tween the Left/Right clock, serial clock and serial data is defined by the Digital Interface Format and the options are detailed in the section “CODEC Digital Interface Formats” on page 32. Refer to Table 9. “Serial Audio Interface Channel Allocations” on page 36. NOTE: The ADC does not meet Quad-Speed Mode timing specifications in the TDM interface format. DAC_DIF2 DAC_DIF1 DAC_DIF0 Left Justified, up to 24-bit data 16 on page 34 I2S, up to 24-bit data 15 on page 34 Right Justified, 24-bit data 17 on page 34 Right Justified, 16-bit data 17 on page 34 One-Line #1, 20-bit 18 on page 34 One-Line #2, 24-bit 19 on page 35 TDM Mode, 24-bit (slave only) 20 on page 35 Reserved Table 12. DAC Digital Interface Formats Left Justified, up to 24-bit data 16 on page 34 I2S, up to 24-bit data 15 on page 34 Right Justified, 24-bit data 17 on page 34 Right Justified, 16-bit data 17 on page 34 One-Line #1, 20-bit 18 on page 34 One-Line #2, 24-bit 19 on page 35 TDM Mode, 24-bit (slave only) 20 on page 35 Reserved Table 13. ADC Digital Interface Formats

6.6 ADC CONTROL & DAC DE-EMPHASIS (ADDRESS 05H) 6.6.1 ADC1-2 HIGH PASS FILTER FREEZE (ADC1-2_HPF FREEZE) Default = 0 Function: When this bit is set, the internal high-pass filter will be disabled for ADC1 and ADC2.The current DC offset value will be frozen and continue to be subtracted from the conversion result. See “ADC Digital Filter Characteristics” on page 14. 6.6.2 ADC3 HIGH PASS FILTER FREEZE (ADC3_HPF FREEZE) Default = 0 Function: When this bit is set, the internal high-pass filter will be disabled for ADC3.The current DC offset value will be frozen and continue to be subtracted from the conversion result. See “ADC Digital Filter Char- acteristics” on page 14. 6.6.3 DAC DE-EMPHASIS CONTROL (DAC_DEM) Default = 0 0 - No De-Emphasis 1 - De-Emphasis Enabled (Auto-Detect Fs) Function: Enables the digital filter to maintain the standard 15µs/50µs digital de-emphasis filter response at the auto-detected sample rate of either 32, 44.1, or 48 kHz. De-emphasis will not be enabled, regardless of this register setting, at any other sample rate. 6.6.4 ADC1 SINGLE-ENDED MODE (ADC1 SINGLE) Default = 0 0 - Disabled; Differential input to ADC1 1 - Enabled; Single-Ended input to ADC1 Function: When enabled, this bit allows the user to apply a single-ended input to the positive terminal of ADC1. +6 dB digital gain is automatically applied to the serial audio data of ADC1. The negative leg must be driven to the common mode of the ADC. See Figure 27 on page 56 for a graphical description. 6.6.5 ADC2 SINGLE-ENDED MODE (ADC2 SINGLE) Default = 0 0 - Disabled; Differential input to ADC2 1 - Enabled; Single-Ended input to ADC2 ADC1-2_HPF FREEZE ADC3_HPF FREEZE DAC_DEM ADC1 SINGLE ADC2 SINGLE ADC3 SINGLE AIN5_MUX AIN6_MUX

Function: When enabled, this bit allows the user to apply a single-ended input to the positive terminal of ADC2. +6 dB digital gain is automatically applied to the serial audio data of ADC2. The negative leg must be driven to the common mode of the ADC. See Figure 27 on page 56 for a graphical description. 6.6.6 ADC3 SINGLE-ENDED MODE (ADC3 SINGLE) Default = 0 0 - Disabled; Differential input to ADC 1 - Enabled; Single-Ended input to ADC Function: When disabled, this bit removes the 4:2 multiplexer from the signal path of ADC3 allowing a differen- tial input. When enabled, this bit allows the user to choose between 4 single-ended inputs to ADC3, using the AIN5_MUX and AIN6_MUX bits. See Figure 11 on page 27 and Figure 27 on page 56 for graphical descriptions. 6.6.7 ANALOG INPUT CH. 5 MULTIPLEXER (AIN5_MUX) Default = 0 0 - Single-Ended Input AIN5A 1 - Single-Ended Input AIN5B Function: ADC3 can accept single-ended input signals when the ADC3 SINGLE bit is enabled. The AIN5_MUX bit selects between two input channels (AIN5A or AIN5B) to be sent to ADC3 in single-ended mode. This bit is ignored when the ADC3_SINGLE bit is disabled. See Figure 11 on page 27 for a graphical description. 6.6.8 ANALOG INPUT CH. 6 MULTIPLEXER (AIN6_MUX) Default = 0 0 - Single-Ended Input AIN6A 1 - Single-Ended Input AIN6B Function: ADC3 can accept a single-ended input signal when the ADC3 SINGLE bit is enabled. The AIN6_MUX bit selects between two input channels (AIN6A or AIN6B) to be sent to ADC3 in single-ended mode. This bit is ignored when the ADC3_SINGLE bit is disabled. See Figure 11 on page 27 for a graphical description. 6.7 TRANSITION CONTROL (ADDRESS 06H) 6.7.1 SINGLE VOLUME CONTROL (DAC_SNGVOL, ADC_SNGVOL) Default = 0 DAC_SNGVOL DAC_SZC1 DAC_SZC0 AMUTE MUTE ADC_SP ADC_SNGVOL ADC_SZC1 ADC_SZC0

Function: The individual channel volume levels are independently controlled by their respective Volume Control registers when this function is disabled. When enabled, the volume on all channels is determined by the AOUT1 and AIN1 Volume Control register and the other Volume Control registers are ignored. 6.7.2 SOFT RAMP AND ZERO CROSS CONTROL (ADC_SZC[1:0], DAC_SZC[1:0]) Default = 00 00 - Immediate Change 01 - Zero Cross 10 - Soft Ramp 11 - Soft Ramp on Zero Crossings Function: Immediate Change When Immediate Change is selected all volume level changes will take effect immediately in one step. Zero Cross Zero Cross Enable dictates that signal level changes, either by gain changes, attenuation changes or muting, will occur on a signal zero crossing to minimize audible artifacts. The requested level change will occur after a timeout period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample rate) if the signal does not encounter a zero crossing. The zero cross function is independent- ly monitored and implemented for each channel. Soft Ramp Soft Ramp allows level changes, either by gain changes, attenuation changes or muting, to be imple- mented by incrementally ramping, in 1/8 dB steps, from the current level to the new level at a rate of 1 dB per 8 left/right clock periods. Soft Ramp on Zero Crossing Soft Ramp and Zero Cross Enable dictates that signal level changes, either by gain changes, atten- uation changes or muting, will occur in 1/8 dB steps and be implemented on a signal zero crossing. The 1/8 dB level change will occur after a timeout period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample rate) if the signal does not encounter a zero crossing. The zero cross function is independently monitored and implemented for each channel. 6.7.3 AUTO-MUTE (AMUTE) Default = 1 0 - Disabled 1 - Enabled Function: The Digital-to-Analog converters of the CS42448 will mute the output following the reception of 8192 consecutive audio samples of static 0 or -1. A single sample of non-static data will release the mute. Detection and muting is done independently for each channel. The quiescent voltage on the output will be retained and the MUTEC pin will go active during the mute period. The muting function is af- fected, similar to volume control changes, by the Soft and Zero Cross bits (SZC[1:0]).

When enabled, the ADC Serial Port will be muted. Zero Cross bits (DAC_SZC[1:0]). When all channels are muted, the MUTEC pin will become active. settings less than -127.5 dB are equivalent to enabling the AOUTx_MUTE bit for the given channel. Table 14. Example AOUT Volume Settings

When enabled, these bits will invert the signal polarity of their respective channels.

··
·· 0011 0000 +24 dB
··
·· 0000 0000 0 dB 1111 1111 -0.5 dB 1111 1110 -1 dB
··
·· 1000 0000 -64 dB

Table 15. Example AIN Volume Settings

Function: When enabled, these bits will invert the signal polarity of their respective channels. 6.13 STATUS CONTROL (ADDRESS 18H) 6.13.1 INTERRUPT PIN CONTROL (INT[1:0]) Default = 00 00 - Active high; high output indicates interrupt condition has occurred 01 - Active low, low output indicates an interrupt condition has occurred 10 - Open drain, active low. Requires an external pull-up resistor on the INT pin. 11 - Reserved Function: Determines how the Interrupt pin (INT) will indicate an interrupt condition. For DAC and ADC clock errors, the INT pin is set to “Level Active Mode” and will become active during the clock error. For the ADCx_OVFL error, the INT pin is set to Level Active Mode and will become active during the overflow error. 6.14 STATUS (ADDRESS 19H) (READ ONLY) For all bits in this register, a “1” means the associated error condition has occurred at least once since the register was last read. A”0” means the associated error condition has NOT occurred since the last reading of the register. Reading the register resets all bits to 0. Status bits that are masked off in the associated mask register will always be “0” in this register. 6.14.1 DAC CLOCK ERROR (DAC_CLK ERROR) Default = x Function: Indicates an invalid MCLK to DAC_LRCK ratio. This status flag is set to “Level Active Mode” and be- comes active during the error condition. See “System Clocking” on page 32 for valid clock ratios. 6.14.2 ADC CLOCK ERROR (ADC_CLK ERROR) Default = x Function: Indicates an invalid MCLK to ADC_LRCK ratio. This status flag is set to “Level Active Mode” and be- comes active during the error condition. See “System Clocking” on page 32 for valid clock ratios. Reserved Reserved Reserved Reserved INT1 INT0 Reserved Reserved Reserved Reserved Reserved DAC_CLK Error ADC_CLK Error ADC3_OVFL ADC2_OVFL ADC1_OVFL

6.14.3 ADC OVERFLOW (ADCX_OVFL) Default = x Function: Indicates that there is an over-range condition anywhere in the CS42448 ADC signal path of each of the associated ADC’s. These status flags become active on the arrival of the error condition. 6.15 STATUS MASK (ADDRESS 1AH) Default = 00000 Function: The bits of this register serve as a mask for the error sources found in the register “Status (address 19h) (Read Only)” on page 54. If a mask bit is set to 1, the error is unmasked, meaning that its occur- rence will affect the INT pin and the status register. If a mask bit is set to 0, the error is masked, mean- ing that its occurrence will not affect the INT pin or the status register. The bit positions align with the corresponding bits in the Status register. 6.16 MUTEC PIN CONTROL (ADDRESS 1BH) 6.16.1 MUTEC POLARITY SELECT (MCPOLARITY) Default = 0 0 - Active low 1 - Active high Function: Determines the polarity of the MUTEC pin. 6.16.2 MUTE CONTROL ACTIVE (MUTEC ACTIVE) Default = 0 0 - MUTEC pin is not active. 1 - MUTEC pin is active. Function: The MUTEC pin will go high or low (depending on the MUTEC Polarity Select bit) when this bit is en- abled. Reserved Reserved Reserved DAC_CLK Error_M ADC_CLK Error_M ADC3_OVFL_M ADC2_OVFL_M ADC1_OVFL_M Reserved Reserved Reserved Reserved Reserved Reserved MCPolarity MUTEC ACTIVE

Figure 29. Passive Input Filter w/Attenuation

10 PARAMETER DEFINITIONS

The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. Dynamic Range is a signal-to-noise ratio measurement over the specified band width made with a -60 dBFS signal. 60 dB is added to resulting measurement to refer the measurement to full-scale. This technique ensures that the distortion components are below the noise level and do not affect the measurement. This measurement technique has been accepted by the Audio Engineering Society, AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307. Expressed in decibels. Total Harmonic Distortion + Noise The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified band width (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels. Measured at -1 and -20 dBFS as suggested in AES17-1991 Annex A. Frequency Response A measure of the amplitude response variation from 10 Hz to 20 kHz relative to the amplitude response at 1 kHz. Units in decibels. Interchannel Isolation A measure of crosstalk between the left and right channel pairs. Measured for each channel at the con- verter's output with no signal to the input under test and a full-scale signal applied to the other channel. Units in decibels. Interchannel Gain Mismatch The gain difference between left and right channel pairs. Units in decibels. Gain Error The deviation from the nominal full-scale analog output for a full-scale digital input. Gain Drift The change in gain value with temperature. Units in ppm/°C. Offset Error

11 REFERENCES

1) Cirrus Logic, Audio Quality Measurement Specification, Version 1.0, 1997. http://www.cirrus.com/products/papers/meas/meas.html Cirrus Logic, AN18: Layout and Design Rules for Data Converters and Other Mixed Signal Devices, Version 6.0, February 1998. Cirrus Logic, Techniques to Measure and Maximize the Performance of a 120 dB, 96 kHz A/D Con- verter Integrated Circuit, by Steven Harris, Steven Green and Ka Leung. Presented at the 103rd Conven- tion of the Audio Engineering Society, September 1997. Cirrus Logic, A Stereo 16-bit delta-sigma A/D Converter for Digital Audio, by D.R. Welland, B.P. Del Convention of the Audio Engineering Society, November 1988. Cirrus Logic, The Effects of Sampling Clock Jitter on Nyquist Sampling Analog-to-Digital Converters, and on Oversampling Delta Sigma ADC's, by Steven Harris. Paper presented at the 87th Convention of the Audio Engineering Society, October 1989. Cirrus Logic, An 18-Bit Dual-Channel Oversampling delta-sigma A/D Converter, with 19-Bit Mono Ap- plication Example, by Clif Sanchez. Paper presented at the 87th Convention of the Audio Engineering So- ciety, October 1989. Cirrus Logic, How to Achieve Optimum Performance from delta-sigma A/D and D/A Converters,by Steven Harris. Presented at the 93rd Convention of the Audio Engineering Society, October 1992. Cirrus Logic, A Fifth-Order Delta-sigma Modulator with 110 dB Audio Dynamic Range, by I. Fujimori, K. Hamashita and E.J. Swanson. Paper presented at the 93rd Convention of the Audio Engineering So- ciety, October 1992. Philips Semiconductor, The I²C-Bus Specification: Version 2.1, January 2000. http://www.semicon- ductors.philips.com

12 PACKAGE INFORMATION

12.1 Thermal Characteristics INCHES MILLIMETERS DIM MIN NOM MAX MIN NOM MAX A --- 0.55 0.063 --- 1.40 1.60 0.002 0.004 0.006 0.05 0.10 0.15 B 0.007 0.008 0.011 0.17 0.20 0.27 D 0.461

0.472 BSC

0.484 11.70

12.0 BSC

12.30 0.390

0.393 BSC

0.398 9.90

10.0 BSC

10.10 E 0.461 0.484 11.70 12.30 0.390 0.398 9.90 10.10 0.016

0.020 BSC

0.024 0.40

0.50 BSC

0.60 L 0.018 0.024 0.030 0.45 0.60 0.75 0.000° 7.000° 0.00° 7.00° * Nominal pin pitch is 0.50 mm Controlling dimension is mm. JEDEC Designation: MS026 Parameter Symbol Min Typ Max Units Junction to Ambient Thermal Impedance

2 Layer Board

4 Layer Board

θJA θJA °C/Watt °C/Watt 64L LQFP PACKAGE DRAWING E D e L B A

13 ORDERING INFORMATION

Order # CS42448 6-in, 8-out CODEC for Sur- round Sound Apps 64L-LQFP YES Commercial -10° to +70° C Rail CS42448-CQZ Tape & Reel CS42448-CQZR Automotive -40° to +85° C Rail CS42448-DQZ Tape & Reel CS42448-DQZR CDB42448 CS42448 Evaluation Board CDB42448

14 REVISION HISTORY

Corrected I²C Address in section 4.7.2 on page 39. Initial Preliminary Product (PP) Release subject to legal notice below. Added pin numbers to “Typical Connection Diagram” on page 10. istics and Specifications” beginning on page 11. QSM in section “Characteristics and Specifications” beginning on page 11. section “Characteristics and Specifications” beginning on page 11. Changed ADC Quad-Speed Mode parameters. See Note 19 on page 21. Added section “De-Emphasis Filter” on page 31. Corrected section “TDM” on page 35. to -64 dB) in register “AINx Volume Control (AINx_VOL[7:0])” on page 53. Overflow (ADCX_OVFL)” on page 55 for the Active Mode setting. Added section “Ordering Information” on page 67. Table 16. Revision History

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Product Information

CDB42448 specifications and overview.

Summary

108 dB, 192 kHz 6-in, 8-out CODEC

Description

108 dB, 192 kHz 6-in, 8-out CODEC

Source title CDB42448 Datasheet(PDF) - Cirrus Logic

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