CDB42406 CIRRUS | Alldatasheet
Document overview
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Technical content
Features
Single-ended analog inputs and outputs CS8406 S/PDIF digital audio transmitter CS8416 S/PDIF digital audio receiver Header for optional external configuration of CS42406 Header for external DSP serial audio I/O 3.3 V to 5.0 V Logic Interface
14 Pre-defined Board Setup Options
Demonstrates recommended layout and grounding arrangements Windows compatible software interface to configure CS42406 and intra-board connections
ORDERING INFORMATION
Description
The CDB42406 demonstration board is an excellent means for evaluating the CS42406 CODEC. Evaluation requires an analog/digital signal source and analyzer, and power supplies. Optionally, a Windows PC compat- ible computer may be used to evaluate the CS42406 DAC in control port mode. System timing can be provided by the CS42406, by the CS8416 phase-locked to its S/PDIF input, by an I/O stake header or by an on-board oscillator. RCA phono jacks are provided for the CS42406 analog outputs and inputs. Digital data I/O is available via RCA phono or op- tical connectors to the CS8416 and CS8406. 14 pre- defined board setup options are selectable using a 4-po- sition DIP switch. The Windows software provides a GUI to make configu- ration of the DAC easy. The software communicates through the PC’s parallel port to configure the control port registers so that all features of the CS42406 can be evaluated. The evaluation board may also be configured to accept external timing and data signals for operation in a user application during system development. I CS42406 2-Ch. Single-Ended Analog Inputs DAC Control Port CS8406 S/PDIF Transmitter CS8416 S/PDIF Receiver DSP I/O Header Master Clock* S/PDIF Output S/PDIF Input CPLD Clock/Data Router *Master Clock is selectable between one of the following: 1) S/PDIF Receiver, 2) Crystal oscillator, or 3) DSP I/O Header. All selections are buffered. Crystal Oscillator 6-Ch. Single-Ended Analog Outputs PCM Clock/ Data I2C/SPI Board Setup DAC/ADC Setup AUG ‘03 DS614DB1
Contacting Cirrus Logic Support For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find one nearest you go to www.cirrus.com IIMPORTANT NOTICE Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is sub- ject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and con- ditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. No responsi- bility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. An export permit needs to be obtained from the competent authorities of the Japanese Government if any of the products or technologies described in this ma- terial and controlled under the "Foreign Exchange and Foreign Trade Law" is to be exported or taken out of Japan. An export license and/or quota needs to be obtained from the competent authorities of the Chinese Government if any of the products or technologies described in this material is subject to the PRC Foreign Trade Law and is to be exported or taken out of the PRC. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANT- ED FOR USE IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS (INCLUDING MEDICAL DEVICES, AIRCRAFT SYSTEMS OR COMPONENTS AND PERSONAL OR AUTOMOTIVE SAFETY OR SECURITY DEVICES). INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOM- ER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trade- marks or service marks of their respective owners. I2C is a registered trademark of Philips Semiconductor. Purchase of I2C Components of Cirrus Logic, Inc., or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use those components in a standard I2C system.
- SYSTEM OVERVIEW The CDB42406 demonstration board is an excellent means for evaluating the CS42406 stereo CODEC. Analog and digital audio signal interfaces are provided, as well as a DB-25 computer parallel port interface for use with the supplied Windows configuration software. The CDB42406 schematic set has been partitioned into 10 pages and is shown in Figures 16 through 25. 1.1 CS42406 Audio CODEC A complete description of the CS42406 is included in the CS42406 product data sheet. 1.2 CS8406 Digital Audio Transmitter The operation of the CS8406 transmitter (see Figure 18) and a discussion of the digital audio interface are included in the CS8406 data sheet. The CS8406 converts the PCM data generated by the CS42406 to the standard S/PDIF data stream. The CS8406 operates in slave mode and only accepts a 256Fs master clock on the OMCK input pin. The serial audio input data for the CS8406 is received from the serial audio output of the CS42406. Digital Interface format selection of either Left Justified or I2S can be made via the I2S/LJ position on switch S3 (see Table 2 for switch control options). 1.3 CS8416 Digital Audio Receiver The operation of the CS8416 receiver (see Figure 17) and a discussion of the digital audio interface are included in the CS8416 data sheet. The CS8416 converts the input S/PDIF data stream into PCM data for the CS42406. The CS8416 operates in master mode only. Digital Interface format selection of either Left Justi- fied or I2S can be made via the I2S or LJ position on S1(see Table 2 for switch control op- tions). The CS8416 contains an internal input multiplexer which must be set to receive the appropri- ate stream from the Optical or Coaxial input connector. This is done via the Coaxial or Optical position on switch S1.
1.4 Canned Oscillator Oscillator Y1 provides a System Clock. This clock can be routed through the CS8416 out the RMCK pin when the S/PDIF input is disconnected (refer to the CS8416 data sheet for details on OMCK operation). To use the canned oscillator as the source of the MCLK signal, select from one of the pre-defined options, detailed in section 1.7, using the SW[3:0] positions on switch S4. The oscillator is mounted in pin sockets, allowing easy removal or replacement. The board is shipped with a 12.2880 MHz crystal oscillator stuffed at Y1. 1.5 Analog Input RCA connectors supply the CS42406 analog inputs through unity gain, AC-coupled single- ended circuits. A 1 Vrms single-ended signal will drive the CS42406 inputs to full scale. 1.6 Analog Outputs The CS42406 analog outputs are routed through a single-pole RC filter. The corner frequen- cy can be extended to 190 kHz by simply removing one of the 1500 pF filter capacitors. 1.7 CPLD Board Setup The CPLD (U9) controls all digital signal routing between the CS42406, CS8416, CS8406, AUDIO MCLK (Y1), and DSP I/O HDR. The user may choose from 14 clock/data routing op- scription of each mode. Any combination can be realized in either stand-alone or control port mode.
details). The CS8406 is always clocked from the same source as the ADC. option, set DIP switch S4 (SW[3:0]) to ‘0000’b. Figure 1. S/PDIF IN/OUT - Setup 0
different MCLK and 2 different subclock sources for the ADC/DAC. Figure 4. Digital Loopback - Setup 3
implementation of this setup option, set DIP switch S4 (SW[3:0]) to ‘0110’b. There are 6 different setup options for routing MCLK, LRCK and SCLK for DSP control. and ADC. The user may also choose between 2 different MCLK sources. Figure 7. Digital Loopback - Setup 6
Figure 12. DSP Routing - Setup 11
1.8 Stand-Alone Control Switches S1-S4 allow signal routing and configuration of the CDB42406. Switch S1 controls the interface format of the CS8416 and allows selection between the OPTICAL and COAXIAL S/PDIF inputs. The DAC portion of the CS42406 may operate in either stand-alone (config- ured using switch S2) or control port mode (configured via the PC Parallel Port through a graphical user interface). The ADC portion of the CS42406 operates in stand-alone mode at all times and must be configured using switch S3. Switch S4 controls the routing of all clocks and data. See section 1.7 for a list of the various stand-alone options available. After setting any of these switches, the user must assert a reset by pressing the RESET button (S5). Operation in stand-alone mode requires the parallel port cable to remain disconnected from the DB-25 connector (J24). Connecting a cable to the connector will enable the PC control port, automatically disabling various controls on switch S2. 1.9 PC Parallel Port Control A graphical user interface is included with the CDB42406 to allow easy manipulation of the DAC registers of the CS42406. Connecting a cable to the DB-25 connector (J24) will enable the PC control port, automatically disabling various controls on switch S2. 1.10 External Control Headers The evaluation board has been designed to allow interfacing with external systems via the headers J15 and J26. The 32-pin header, J15, provides access to the serial audio signals required to interface with a DSP (see Figure 24). These signals are routed based on the setting of switch S4. See “CPLD Board Setup” in section 1.7 for various setup options for DSP routing. The 6-pin header, J26, allows the user bidirectional access to the SPI/I2C control signals. The signals on J26 default to outputs. When a cable is connected to the DB-25 connector (J24), the header (J26) may be used as an input. In this case, the control signals on J26 are routed to the corresponding control pins on the CS42406 and external control signals may be ap- plied.
1.11 Power Power must be supplied to the evaluation board through at least the +5.0 V binding post, (J1). Jumpers J3 and J6 connect the VD and VA supply, respectively, to a fixed +5.0 V or +3.3 V supply or to two separate binding posts (J4 and J7) for variable voltage settings. Jumper J5 allows the user to connect the VLS and VLC supplies of the CS42406 to a fixed +5.0 V or +3.3 V supply. All voltage inputs must be referenced to the single black banana- type ground connector (see Figure 25). WARNING:Please refer to the CS42406 data sheet for allowable voltage levels. 1.12 Grounding and Power Supply Decoupling The CS42406 requires careful attention to power supply and grounding arrangements to op- timize performance. Figure 15 provides an overview of the connections to the CS42406, Figure 26 shows the component placement, Figure 27 shows the top layout, and Figure 28 shows the bottom layout. The decoupling capacitors are located as close to the CS42406 as possible. Extensive use of ground plane fill in the evaluation board yields large reductions in radiated noise.
I/O for external SPI / I2C control port signals. Table 1. System Connections
Table 2. Jumper/Switch Settings
All selections are buffered. Figure 15. Block Diagram
Figure 16. CS42406
Figure 17. S/PDIF Input
Figure 18. S/PDIF Output
Figure 19. CPLD
Figure 20. Analog Input
Figure 21. Ch. 1 Analog Output
Figure 22. Ch. 2 Analog Output
Figure 23. Ch. 3 Analog Output
Figure 24. DAC Control Port and I/O Headers
Figure 25. Power
Figure 26. Silk Screen
Figure 27. Topside Layer
Figure 28. Bottomside Layer