CD54AC08 HARRIS | Alldatasheet
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Technical content
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper I.C. Handling Procedures. Copyright © Harris Corporation 1994 1 SEMICONDUCTOR CD54AC08/3A CD54ACT08/3A Quad 2-Input AND Gate Functional Diagram GND VCC
Description
The CD54AC08/3A and CD54ACT08/3A are quad 2-input AND gates that utilize the Harris Advanced CMOS Logic technology. The CD54AC08/3A and CD54ACT08/3A are supplied in 14 lead dual-in-line ceramic packages (F suffix). ACT INPUT LOAD TABLE INPUT UNIT LOAD (NOTE 1) All 0.3 NOTE: 1. Unit load isΔICC limit specified in DC Electrical Specifications Table, e.g., 2.4mA Max at +25oC. June 1997 File Number 3880 Absolute Maximum Ratings DC Input Diode Current, IIK DC Output Diode Current, IOK DC Output Source or Sink Current, Per Output Pin, IO DC V CC or GND Current, ICC or IGND For Up to 4 Outputs Per Device, Add±25mA For Each Power Dissipation Per Package, PD 8mW/ oC to 300mW Operating Temperature Range, TA Lead Temperature (During Soldering) At Distance 1/16in.± 1/32in. (1.59mm± 0.79mm) Unit Inserted Into a PC Board (Min Thickness 1/16in., 1.59mm) oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Recommended Operating Conditions Supply Voltage Range, VCC Unless Otherwise Specified, All Voltages Referenced to GND TA = Full Package Temperature Range DC Input or Output Voltage, V Input Rise and Fall Slew Rate, dt/dv COMING SOON! COMPLETE DATA SHEET