CD22402 HARRIS | Alldatasheet

Document overview

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Technical content

Features

  • Interlaced Composite Sync Output
  • Automatic Genlock Capability
  • Crystal Oscillator Operation
  • 525 or 625 Line Operation
  • Vertical Reset Option

Applications

  • Cameras
  • Monitors and Displays
  • C A T V
  • Teletext
  • Video Games
  • Sync Restorer
  • Video Service Instruments

Description

The Harris CD22402 (Note) is a CMOS LSI sync generator that produces all the timing signals required to drive a fully 2-to-1 interlaced 525-line 30-frame/second, or 625-line 25-frame/sec- ond TV camera or video processing system. A complete sync waveform is produced which begins each field with six serrated vertical sync pulses, preceded and followed by six half-width double frequency equalizing pulses. The sync output is gated by the master clock to preserve horizontal phase continuity during the vertical interval. The CD22402 can be operated either in “genlock” mode, in which it is synchronized with a reference sync pulse train from another TV camera, or in “stand-alone” mode, in which it is syn- chronized with a local on-chip crystal oscillator (the crystal and two passive components are off chip). Also, the circuit can sense the presence or absence of a reference sync pulse train and automatically select the “genlock” or “stand-alone” mode. A frame sync pulse is produced at the beginning of every odd field. The vertical counter can be reset to either the first equalizing pulse or the first vertical sync pulse of the vertical interval. The interlaced sync provided by the CD22402 differs from RS-170 by having slightly narrower sync and equalizing pulses. The clock frequency of 32 times horizontal rate allows for approximately 4µs horizontal pulse widths and 2µs equalizing pulses. Otherwise operation can be phase locked to a color sub-carrier for a full interlaced operating system. The CD22402 is operable with a single supply over a voltage range of 4V to 15V. Pinout CD22402 (PDIP, SBDIP) TOP VIEW Part Number Information PART NUMBER TEMP. RANGE ( oC) PACKAGE PKG. NO. CD22402D -55 to 125 24 Ld SBDIP D24.6 CD22402E -40 to 85 24 Ld PDIP E24.6 MIXED SYNC OUTPUT VERTICAL DRIVE OUTPUT HORIZONTAL CLAMP OUTPUT FRAME SYNC OUTPUT (ODD FIELD) HORIZONTAL PROCESSING BLANKING OUTPUT MIXED PROCESSING BLANKING OUTPUT MASTER FREQUENCY INPUT DELAY, GENLOCK TO CRYSTAL OSCILLATOR CRYSTAL OSCILLATOR FEEDBACK TAP HORIZONTAL DRIVE OUTPUT MIXED BEAM BLANKING OUTPUT GENLOCK OSCILLATOR CAPACITOR CONNECTION VERTICAL COUNTER RESET TO FIRST EQUALIZING PULSE VERTICAL RESET TO FIRST VERTICAL SYNC PULSE SHORT VERTICAL DRIVE OUTPUT

525 LINE TO 625 LINE OPERATION SWITCH

VERTICAL PROCESSING BLANKING OUTPUT R-C CONNECTION FOR GENLOCK OSCILLATOR DELAY, GENLOCK TO CRYSTAL OSCILLATOR GENLOCK INPUT (COMPOSITE SYNC) RESISTOR CONNECTION FOR GENLOCK OSCILLATOR VSS VSS VDD CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © Harris Corporation 1999 File Number 1686.5 [ /Title (CD2240 /Subject (Sync Genera- tor for TV Applica- tions and Video Process- OBSOLETE PRODUCT NO RECOMMENDED REPLA CEMENT Call Central Applications 1-800-442-7747or email: centapp@harris.com

PIN NO. SYMBOL DESCRIPTION 1 XRC Delay, Genlock to Crystal Oscillator.Resistor, diode and capacitor connection for delay that automatically turns on the crystal oscillator when the genlock input is removed. When the signal on Terminal 1 is high the crys- tal oscillator is inhibited. Typical values for R and C are 1MΩ and 0.001µF . For operation as a crystal controlled stand alone sync generator without genlock, Terminal 1 should be hardwired to V SS . 2 XTP Crystal Oscillator Feedback Tap.Feedback connection (tap) for crystal oscillator. When a crystal (shunted by a1 MΩ resistor) is connected between this terminal and Terminal 23, and a 100pF capacitor is connected from this terminal to VSS , the sync generator creates its own master frequency. For a 525-line, 30-frame/second ras- ter, the crystal frequency is 504.000kHz (Note 1); and for a 625-line, 25-frame/second raster, the crystal frequen- cy is 500.000kHz (Note 1). SS Negative Power Supply Voltage. This terminal must be hardwired to Terminal 12 (VSS ). 4H D Horizontal Drive Output 5M S Mixed Sync Output 6C Capacitor Connection for R-C Genlock Oscillator

7 MBB Mixed Beam Blanking Output

8 VRE Vertical Counter Reset to First Equalizing Pulse.A low level signal on this terminal resets the vertical counter to the first equalizing pulse of a field. When not in use this terminal should be connected to VDD . 9V D Vertical Drive Output 10 VRV Vertical Counter Reset to First Vertical Sync Pulse.A low level signal on this terminal resets the sync gen- erator to the first vertical sync pulse of a field. For genlock operation, Terminal 10 is used as a resistor and ca- pacitor connection for an integrator network that detects vertical sync pulses in a master sync waveform to which the sync generator is to be genlocked. R is 22kΩ , and C is 0.001µF . When not in use this terminal should be connected to V DD .

11 HC Horizontal Clamp Output

12 V SS Negative Power Supply Voltage

13 MPB Mixed Processing Blanking Output

14 HPB Horizontal Processing Blanking Output

15 FS2 Frame Sync Output (Odd Field).A pulse coinciding with the first equalizing pulse is produced at the beginning of every odd field.

16 SVD Short Vertical Drive Output

17 VPB Vertical Processing Blanking Output

18 SW Operation Switch for 525-Line or 625-Line Raster.A high level signal on Terminal 18 causes the sync gener- ator to generate a 625-line raster. An internal pulldown resistor is connected to Terminal 18, so in the absence of an applied input to this terminal, a 525-line raster is produced. 19 V DD Positive Power Supply Voltage. VDD can be any voltage between +4 and +15 relative to VSS . 20 GEN Genlock Input Composite Sync.A negative going reference mixed sync waveform applied to Terminal 20 dis- ables the crystal oscillator and locks the R-C genlock oscillator to the horizontal pulses of the reference sync waveform. Vertical sync detection is achieved by an R-C integrator connected from Terminal 20 to Terminal 10 (vertical reset to first vertical sync pulse). An internal pull-up resistor is connected to Terminal 20 so that in the absence of an applied input the crystal oscillator is enabled and the R-C genlock oscillator is disabled. 21 XR Delay, Genlock to Crystal Oscillator, Resistor and Diode Connection for Delay, Genlock to Crystal Oscil- lator. Automatically turns on the crystal oscillator when the input to Terminal 20 is removed. 22 RC Resistor and Capacitor Connection for Genlock Oscillator.If the genlock oscillator is not used this terminal should be connected to V SS . C should be 100pF , and R should be a 10kΩ potentiometer. 23 XIN Master Frequency Input. 24 R Resistor Connection for Genlock Oscillator. NOTE: 32 times horizontal frequency. CD22402

CD22402 MONOCHROME TV SYNC GENERATOR WITH AUTOMATIC GENLOCK R-C GENLOCK OSCILLATOR COMPOSITE DECODER AUTOMATIC GENLOCK CONTROL CRYSTAL OSCILLATOR FRAME SYNC DECODER FIELD DECODER HORIZONTAL COUNTER ÷16 VERTICAL COUNTER ÷525/625 LINE DECODER 14 11 4 5 13 7 15 16 9 17 24 22 6 8 18 HPB HC HD MS MPB MBB FS2 SVD VD VPB XTP XIN XRC XR GEN R VRV RC C VRE SW VSS = PINS 3 AND 12 VDD = PIN 19 CD22402

Absolute Maximum Ratings Thermal Information Operating Conditions Temperature Range Thermal Resistance (Typical, Note 1)θJA (oC/W) θJC (oC/W) oC (SOIC - Lead Tips Only) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. θJA is measured with the component mounted on an evaluation PC board in free air. 2. To prevent damage to the input protection circuit, input signals should never be greater than VDD nor less than VSS . Input currents must not exceed 10mA even when the power is off. 3. A connection must be provided at every input terminal. All unused inputs must be connected to VDD or VSS , whichever is appropriate. Electrical SpecificationsValues at -55oC, 25oC, 125oC Apply to D Package Values at -40oC, 25oC, 85oC Apply to E Package PARAMETER SYMBOL TEST CONDITIONS -55oC -40 oC8 5 oC 125 oC 25oC UNITS VO (V) VDD (V) MIN TYP MAX DC ELECTRICAL SPECIFICATIONS Quiescent Device Current I - 1 0 ---- 1 . 5 2 2 . 5 m A - 1 5 ---- 3 4 5 m A Output Low (Sink) Current I OL (Min) 0.5 5 100 96 66 56 80 160 - µA 5 5 1200 1155 787 672 960 1920 - µA 0.5 10 248 239 164 140 200 400 - µA 10 10 3000 2868 1968 1680 2400 4800 - µA Output High (Source) Cur- rent IOH (Min) 4.5 5 -100 -96 -66 -56 -80 -160 - µA 0 5 -1200 -1155 -787 -672 -960 -1920 - µA 9.5 10 -248 -239 -164 -140 -200 -400 - µA 0 10 -3000 -2868 -1968 -1680 -2400 -4800 - µA 1, 9 10 3 3 2.9 2.9 - 4.5 3 V 1, 9 10 7.1 7.1 7 7 7 4.5 - V Input Current I IN (Max) - - ---- - 1 0 - p A Refer to the CD4000B Series data book 250.5 for general operating and application considerations. CD22402

  1. The characteristics given are defined for unbuffered gate in the CMOS process of the CD22402.

32 TIMES

  1. Pin 21 high when pin 20 is high (or open).
  2. Pin 1 high inhibits clock.

FIGURE 1. DETAIL OF THE OSCILLATOR/GENLOCK PORTION OF THE CD22402

FIGURE 6. EXPANDED VERTICAL-TIMING WAVEFORM DETAIL OF SYNC GENERATOR TIMING (VERTICAL DRIVE - PIN 9) FIGURE 7. EXPANDED VERTICAL-TIMING WAVEFORM DETAIL OF SYNC GENERATOR TIMING (VERTICAL PROCESSING

1 CLK

2 CLKS

14 CLKS

FIGURE 8. EXPANDED VERTICAL-TIMING WAVEFORM DETAIL OF SYNC GENERATOR TIMING (MIXED PROCESSING FIGURE 9. EXPANDED VERTICAL-TIMING WAVEFORM DETAIL OF SYNC GENERATOR TIMING

6 CLKS

2 CLKS 2 CLKS

  1. Waveforms shown are for 525 line/60Hz, line number in parenthesis are for (625 line/50Hz).
  2. Timing widths by clock count; for 525 line, 1 CLK = 1.98µs; for 625 line, 1 CLK = 2µs; 1 horizontal period = 32 CLKS.

FIGURE 10. EXPANDED VERTICAL-TIMING WAVEFORM DETAIL OF SYNC GENERATOR TIMING (MIXED BEAM BLANKING - PIN 7)

16 CLKS

4 CLKS 2 CLKS

15 CLKS

4 CLKS2 CLKS

FIGURE 11. TYPICAL APPLICATION IN A TV CAMERA

0.5 TO 2VP-P

Application Note AN-8742 for additional information. FIGURE 12. SUGGESTED SYNC-SEPARATOR CIRCUIT USING THE CA5470 BIMOS-E QUAD OP AMP IN THE V DD RANGE