CD22354A

CD22354A HARRIS | Alldatasheet

Document overview

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• PDF pages: 10

Technical content

Features

• Meets or Exceeds All AT&T D3/D4 Specifications and CCITT Recommendations
• Complete CODEC and Filtering Systems: No External Components for Sample-and-Hold and Auto-Zero Functions. Receive Output Fil- ter with (SIN X)/X Correction and Additional 8kHz Suppression
• Receiver Includes Power-Up Click Filter
• TTL or CMOS-Compatible Logic
• ESD Protection on All Inputs and Outputs

Applications

• PABX
• Central Office Switching Systems
• Accurate A/D and D/A Conversions
• Digital Telephones
• Cellular Telephone Switching Systems
• Voice Scramblers - Descramblers
• T1 Conference Bridges
• Voice Storage and Retrieval Systems
• Sound Based Security Systems
• Computerized Voice Analysis
• Mobile Radio Telephone Systems
• Microwave Telephone Networks
• Fiber-Optic Telephone Networks [ /Title (CD22 354A, CD223 57A) /Sub- ject (CMO S Sin- gle- Chip, Full- Fea- ture PCM CODE Author /Key- words (Har- ris Semi- con- ductor, RSLIC 18, Tele- com, SLICs, SLACs , Tele- phone, Tele- phony, WLL, Wire- less Local Loop, OBSOLETE PRODUCT NO RECOMMENDED REPLA CEMENT Call Central Applications 1-800-442-7747or email: centapp@harris.com

CD22354A, CD22357A Absolute Maximum Ratings Thermal Information DC Input Diode Current, I DC Output Diode Current, I DC Drain Current, Per Output I Power Dissipation Per Package (PD ): to 300mW Operating Conditions CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Electrical SpecificationsAt TA = 25oC PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS STATIC SPECIFICATIONS Positive Power Supply V+ 4.75 5 5.25 V Negative Power Supply V- -4.75 -5 -5.25 V Power Dissipation (Operating) P OPR V+ = 5V - 75 90 mW Power Dissipation (Standby) P STBY V- = -5V - 9 15 mW Electrical SpecificationsAt TA = 0oC to 70oC; V+ = 5V±5%, V- = -5V±5% PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS STATIC SPECIFICATIONS Analog Input Resistance R INA 10 - - M Ω Input Capacitance C IN All Logic and Analog Inputs - 5 - pF Input Leakage Current, Digital I I VI = 0V or V+ -10 - 10 µA Low Level Input Voltage V IL IIL =±10µA (Max) - - 0.8 V High Level Input Voltage V IH IIH =±10µA (Max) 2 - - V Low Level Output Voltage V OL IOL = 3.2mA - - 0.4 V High Level Output Voltage V OH IOH = 1.0mA 2.4 - - V Open State Output Current I OZ GND < D X < V+ -10 - 10 µA Input Leakage Current, Analog I I -2.5V≤ VFX < 2.5V -200 - 200 nA

CD22354A, CD22357A Electrical SpecificationsV+ = 5V±5%, V- = -5V± 5%, BCLKR = BCLKX = MCLKX = 1.544MHz, VIN = 0dBm0, TA = 0oC to 70oC PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS TRANSMIT AND RECEIVE FILTER TRANSFER CHARACTERISTICS Transmit Gain (Relative to Gain at 1020Hz) Input Amplifier Set to Unity Gain G RX f = 16Hz - - -40 dB f = 50Hz - - -30 dB f = 60Hz - - -26 dB f = 200Hz -1.8 - -0.1 dB f = 300Hz to 3000Hz -0.15 - 0.15 dB f = 3300Hz -0.35 - 0.05 dB f = 3400Hz -0.7 - 0 dB f = 4000Hz - - -14 dB f≥ 4600Hz, Measure 0 - 4kHz Response - - -32 dB Receive Gain (Relative to Gain at 1020Hz) (Includes (SIN X)/X Compensation) G RR f = 0Hz to 3000Hz -0.15 - 0.15 dB f = 3300Hz -0.35 - 0.05 dB f = 3400Hz -0.9 - 0 dB f = 4000Hz - - -14 dB AC Specifications Definition Unless otherwise specified, the following conditions apply: GND A, GNDD = 0V, FFX = 1020Hz at 0dBm0 Transmit input amplifier operating in a unity gain configuration oC to 70oC Receive output is measured single-ended. All output levels are (SIN X)/X corrected. AMPLITUDE RESPONSE Absolute Levels Definition: V REF = -2.5V 1.2276VRMS Maximum Overload Level: 2.49V A-Law AC Specifications Encoding Format at DX Output CD22354A µ-LAW CD22357A A-LAW (INCLUDES EVEN BIT INVERSION) VIN (at GSX) = +Full-Scale 1 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 VIN (at GSX) = 0 V 1111111111010101 0111111101010101 VIN (at GSX) = -Full-Scale 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0

CD22354A, CD22357A Electrical Specifications PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS AC DISTORTION Signal to Total Distortion Xmit or R CV STD X, STDR Level = +3dBm0 33 - - dBc Level = 0 to -30dBm0 36 - - dBc Level = -40dBm0 30 - - dBc Level = -55dBm0, XMT 14 - - dBc Level = -55dBm0, R CV 15 - - dBc Single Frequency Distortion Xmit or RCV SFD X, SFDR - - -46 dBc Intermodulation (End-to-End Measurement) 2-Tone IMD V FX = -4dBm0 to -21dBm0 f1, f2 from 300 to 3400Hz - - -41 dB Transmit Delay, Absolute t DAX f = 1600Hz - 280 315 µs Transmit Envelope Delay Relative to tDAX tDEX f = 500-600Hz - 170 220 µs f = 600-1000Hz - 70 145 µs f = 1000-2600Hz - 40 75 µs f = 2600-2800Hz - 90 105 µs Receive Delay, Absolute t DAR f = 1600Hz - 180 200 µs Receive Envelope Delay Relative to tDAR tDER f = 500-600Hz -40 -25 - µs f = 600-1000Hz -40 -25 - µs f = 1000-2600Hz - 60 90 µs f = 2600-2800Hz - 110 125 µs Electrical Specifications PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS AC GAIN TRACKING Transmit Gain Tracking Error GTX +3 to -40dBm0 - - ±0.2 dB -40 to -50dBm0 - - ±0.4 dB -50 to -55dBm0 - - ±1.2 dB Receive Gain Tracking Error GTR +3 to -40dBm0 - - ±0.2 dB -40 to -50dBm0 - - ±0.4 dB -50 to -55dBm0 - - ±1.2 dB Transmit Input Amplifier Gain, Open Loop A OL R L ≥ 1MΩ at GSX 68 - - dB

CD22354A, CD22357A Transmit Input Amplifier Gain, Unity ACL Unity Gain Configuration Inverting or Non-Inverting R L ≥ 10K, CL ≤ 50pF -0.01 - 0.01 dB Transmit Gain, Absolute G XA R L ≥ 10K, CL ≤ 50pF -0.15 - 0.15 dB Receive Gain, Absolute G RA R L ≥ 600Ω , CL ≤ 500pF -0.15 - 0.15 dB Electrical Specifications PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS AC NOISE Transmit Noise N X VF XI- = GND - 12 15 dBrnc0 VF XI+ = GND - -74 -67 dBrn0p Receive Noise N R PCM Code Equivalent to 0V - 7 11 dBrnc0 - -83 -79 dBrn0p V+ Power Supply Rejection Transmit PSRR VF XI+ = 0V V+ = 5V + (100mVRMS ) f = 0kHz to 50kHz 40 - - dBc V- Power Supply Rejection Transmit PSRR VF XI- = 0V V- = -5V + (100mVRMS ) f = 0kHz to 50kHz 40 - - dBc V+ Power Supply Rejection Receive PSRR PCM Code = All 1 Code V+ = 5V + (100mVRMS ) f = 0kHz to 4kHz 40 - - dBc f = 4kHz to 25kHz 37 - - dB f = 25kHz to 50kHz 36 - - dB V- Power Supply Rejection Receive PSRR PCM Code = All 1 Code V- = -5V + (100mVRMS ) f = 0kHz to 4kHz 40 - - dBc f = 4kHz to 25kHz 40 - - dB f = 25kHz to 50kHz 36 - - dB Cross Talk Transmit to Receive CT XR VF XI- = 0dBm0 at 1020Hz - -80 -70 dB Cross Talk Receive to Transmit CT RX D R = 0dBm0 at 1020Hz, VF XI- = 0V - -76 -70 dB Electrical Specifications(Continued) PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

CD22354A, CD22357A Electrical Specifications PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS AC TIMING Frequency of Master Clocks 1/t PM Depends on the Device Used and the BCLKR /CLKSEL Pin - 1.536 - MHz - 1.544 - MHz MCLK X and MCLKR - 2.048 - MHz Width of Master Clock High t WMH MCLK X and MCLKR 160 - - ns Width of Master Clock Low t WML MCLK X and MCLKR 160 - - ns Rise Time of Master Clock t RM MCLK X and MCLKR - - 50 ns Fall Time of Master Clock t FM MCLK X and MCLKR - - 50 ns Set-up Time from BCLKX High (and FSX in Long Frame Sync Mode) to MCLKX Falling Edge tSBFM First Bit Clock after the Leading Edge of FSX 100 - - ns Period of Bit Clock t PB 485 488 15,725 ns Width of Bit Clock High t WBH VIH = 2.2V 160 - - ns Width of Bit Clock Low t WBL VIL = 0.6V 160 - - ns Rise Time of Bit Clock t RB tPB = 488ns - - 50 ns Fall Time of Bit Clock t FB tPB = 488ns - - 50 ns Hold Time from Bit Clock Low to Frame Sync tHBF Long Frame Only 0 - - ns Hold Time from Bit Clock High to Frame Sync tHOLD Short Frame Only 0 - - ns Set-up Time from Frame Sync to Bit Clock Low tSFB Long Frame Only 80 - - ns Delay Time from BCLKX High to Data Valid tDBD Load = 150pF plus 2 LSTTL Loads 0 - 180 ns Delay Time toTS X Low t XDP Load = 150pF plus 2 LSTTL Loads - - 140 ns Delay Time from BCLKX Low or FS X Low to Data Output Disabled tDZC 50 - 165 ns Delay Time to Valid Data from FS X or BCLKX, Whichever Comes Later tDZF C L = 0pF to 150pF 20 - 165 ns Set-up Time from DR Valid to BCLK R/X Low tSDB 50 - - ns Hold Time from BCLKR/X Low to D R Invalid tHBD 50 - - ns Set-up Time from FSX/R to BCLK X/R Low tSF Short Frame Sync Pulse (1 or 2 Bit Clock Periods Long) (Note 1) 50 - - ns Hold Time from BCLK X/R Low to FS X/R Low tHF Short Frame Sync Pulse (1 or 2 Bit Clock Periods Long) (Note 1) 100 - - ns

CD22354A, CD22357A Hold Time from 3rd Period of Bit Clock Low to Frame Sync (FS X or FSR ) tHBFI Long Frame Sync Pulse (from 3 to 8-Bit Clock Periods Long) 100 - - ns Minimum Width of the Frame Sync Pulse (Low Level) tWFL 64K Bit/s Operating Mode 160 - - ns NOTE: 1. For short frame sync timing, FSX and FSR must go high while their respective bit clocks are high. Pin Descriptions PIN NO. SYMBOL DESCRIPTION 1 V- Negative power supply, V- = -5V ±5%. 2 GND Analog and digital ground. All signals referenced to this pin. 3V F R O Analog output of RECEIVE FILTER. 4 V+ Positive power supply, V+ = 5V ±5%. 5F S R Receive Frame Sync Pulse which enables BCLKR to shift PCM data into DR . FSR is an 8kHz PULSE TRAIN. 6D R Receive Data Input. PCM data is shifted into DR following the FSR leading edge.

7 BCLK R /CLK-

The Receive Bit Clock, which shifts data into DR after the frame sync leading edge, may vary from 64kHz to 2.048MHz. Alternatively, the leading edge may be a logic input which selects either 1.536MHz/ 1.544MHz or 2.048MHz for Master Clock in synchronous mode and BCLK X is used for both transmit and receive directions. but best performance is realized from synchronous operation. When this pin is continuously connected low, MCLK X is selected for all internal timing. When this pin is continuously connected high, the device is powered down. but best performance is realized from synchronous operation. 10 BCLK X The Bit Clock which shifts out the PCM Data on DX. May vary from 64kHz to 2.048MHz, but must be syn- chronous with MCLKX. 11 D X The THREE-STATE PCM Data Output which is enabled by FSX. 12 FS X Transmit Frame Sync Pulse input which enables BCLKX to shift out the data on DX. FSX is an 8kHz PULSE TRAIN. 13 TS X Open drain output which pulses low during the encoder time slot. 14 GS X Transmit gain adjust. 15 VF XI- Inverting input of the transmit input amplifier. 16 VF XI+ Non-inverting input of the transmit input amplifier. Electrical Specifications(Continued) PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

CD22354A, CD22357A Functional Description Power Supply Sequencing Do not apply input signal or load on output before powering up VCC supply. Care must be taken to ensure that DX pin goes on common back plane (with other DX pins from other chips). DX pin cannot drive >50mA before Power-Up. This will cause the part to latch up. Power-Up When power is first applied, the Power-On reset circuitry ini- tializes the CODEC and places it in a Power-Down mode. When the CODEC returns to an active state from the Power- Down mode, the receive output is muted briefly to minimize turn-on “click”. To power up the device, there are two methods available. 1. A logical zero atMCLK R /PDN will power up the device, provided FSX or FSR pulses are present. 2. Alternatively, a clock (MCLKR ) must be applied toMCLK R / PDN and FSX or FSR pulses must be present. Power-Down Two power-down modes are available. 1. A logical 1 atMCLK R /PDN,after approximately 0.5ms, will power down the device. 2. Alternatively, hold both FSX and FSR continuously low, the device will power down approximately 0.5ms after the last FS X or FSR pulse. Synchronous Operation (Transmit and Receive Sections use the Same Master Clock) The same master clock and bit-clock should be used for the receive and transmit sections. MCLK X (pin 9) is used to pro- vide the master clock for the transmit section; the receive section will use the same master clock if the MCLK R /PDN (pin 8) is grounded (synchronous operation), or at V+ (power-down mode). MCLK R /PDN may be clocked only if a clock is provided at BCLKR /CLKSEL (pin 7) as in asynchro- nous operation. The BCLK X (pin 10) is used to provide the bit clock to the transmit section. In synchronous operation, this bit clock is also used for the receive section if MCLK R /PDN (pin 8) is grounded. BCLKR /CLKSEL (pin 7) is then used to select the proper internal frequency division for 1.544MHz, 1.536MHz or 2.048MHz operation (see Table below). For 1.544MHz operation, the device automatically compensates for the 193rd clock pulse each frame. Each FS X pulse begins the encoding cycle and the PCM data from the previous encode cycle is shifted out of the enabled D X output on the leading edge of BCLKX. After 8 bit- clock periods, the tristate DX output is returned to a high impedance state. With an FSR pulse, PCM data is latched via the DR input on the negative edge of the BCLKX.F SX and FSR must be synchronous with MCLKX. Asynchronous Operation (Transmit and Receive Sections use Separate Master Clocks) For the CD22357A, the MCLK X and MCLK R must be 2.048MHz and for the CD22354A must be 1.536MHz or 1.544MHz. These clocks need not be synchronous. However, for best transmission performance, it is recommended that MCLK X and MCLKR be synchronous. For 1.544MHz operation the device automatically compensates for the 193rd clock pulse each frame. FSX starts the encoding operation and must be synchronous with MCLKX and BCLKX. FSR starts the decoding operation and must be synchronous with BCLKR . BCLKR must be clocked in asynchronous opera- tion. BCLKX and BCLKR may be between 64kHz - 2.04MHz. Short-Frame Sync Mode When the power is first applied, the power initialization circuitry places the CODEC in a short-frame sync mode. In this mode both frame sync pulses must be 1 bit-clock period long, with the timing relationship shown in Figure 1. With FS X high during the falling edge of the BCLKX, the next rising edge of BCLKX enables the DX tristate output buffer, which will output the sign bit. The following rising seven edges clock out the remaining seven bits upon which the next falling edge will disable the D X output. With FSR high during the falling edge of the BCLKR (BCLKX in synchronous mode), the next falling edge of BCLKR latches in the sign bit. The following seven edges latch in the seven remaining bits. Long-Frame Sync Mode In this mode of operation, both of the frame sync pulses must be three or more bit-clock periods long with the timing relation- ship shown in Figure 2. Based on the transmit frame sync FS X, the CODEC will sense whether short or long-frame sync pulses are being used. For 64kHz operation the frame sync pulse must be kept low for a minimum of 160ns. The DX tristate output buffer is enabled with the rising edge of FSX or the rising edge of the BCLKX, whichever comes later and the first bit clocked out is the sign bit. The following seven rising edges of the BCLK X clock out the remaining seven bits. The DX output is disabled by the next falling edge of the BCLKX following the 8th rising edge or by FSX going low whichever comes later. CLOCKING OPTIONS MODE BCLK R /CLKSEL (PIN 7) MASTER CLOCK FREQUENCY SELECTED CD22354A (µ) CD22357A (A) Asynchronous or Synchronous Clocked 1.536MHz or 1.544MHz 2.048MHz Synchronous 0 2.048MHz 1.536MHz or 1.544MHz Synchronous 1(or open circuit) 1.536MHz or 1.544MHz 2.048MHz

well as to compensate for the (SIN X)/X distortion. filter capable of driving a 600Ω load to a level of 7.2dBm. FIGURE 1. SHORT FRAME-SYNC TIMING

FIGURE 2. LONG FRAME-SYNC TIMING