CD22100

CD22100 HARRIS | Alldatasheet

Document overview

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• PDF pages: 10

Technical content

Features

• “Built-In” Control Latches DD /2
• 10MHz Switch Bandwidth
• Matched Switch CharacteristicsΔR ON =1 8Ω (Typ) at VDD = 12V
• High Linearity - 0.5% Distortion (Typ) at f = 1kHz, VIN = 5VP-P, VDD = 10V, and RL = 1kΩ
• Standard CMOS Noise Immunity
• 100% Tested for Maximum Quiescent Current at 20V

Ordering Information

TEMP. RANGE (oC) PACKAGE PKG. NO. CD22100E -40 to 85 16 Ld PDIP E16.3 CD22100F -55 to 125 16 Ld CERDIP F16.3 February 1999 Pinout CD22100 (PDIP, CERDIP) TOP VIEW Functional Diagram VDD VSS STROBE DATA IN C D B A ADDRESS 4-LINE TO 16-LINE DECODER

16 CONTROL LATCHES

A B C D X1 X2 X3 X4 9 1 12 13 CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © Harris Corporation 1999 File Number 1076.4 CD22100 CMOS 4 x 4 Crosspoint Switch with Control Memory High-Voltage Type (20V Rating) [ /Title (CD22 100) /Sub- ject (CMO S4x4 Cross- point Switch with Con- trol Mem- ory High- V olt- age Type (20V Rat- ing)) Author /Key- words (Har- ris Semi- con- ductor, Tele- com, SLICs, SLACs , Tele- phone, OBSOLETE PRODUCT NO RECOMMENDED REPLA CEMENT Call Central Applications 1-800-442-7747or email: centapp@harris.com

Absolute Maximum Ratings Thermal Information Power Dissipation For TA = 60oC to 85oC For TA = 100oC to 125oC Device Dissipation per Transmission Gate Operating Conditions Temperature Range Supply Voltage Range CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Electrical SpecificationsValues at -55oC, 25oC, 125oC Apply to F Package Values at -40oC, 25oC, 85oC Apply to E Package PARAMETER SYMBOL TEST CONDITIONS -55 oC -40 oC8 5 oC 125 oC2 5 oC UNITSFIG. VDD (V) MAX MAX MAX MAX MIN TYP MAX STATIC CROSSPOINTS Quiescent Device Current I DD (Max) 1 5 5 5 150 150 - 0.04 5 µA 1 10 10 10 300 300 - 0.04 10 µA 1 15 20 20 600 600 - 0.04 20 µA 1 20 100 100 3000 3000 - 0.08 100 µA On Resistance R ON (Max)Any Switch VIS = 0 to VDD 11 5 475 500 725 800 - 225 600 Ω 12 10 135 145 205 230 - 85 180 Ω - 12 100 110 155 175 - 75 135 Ω 13 15 70 75 110 125 - 65 95 Ω ΔR ON Resistance ΔR ON Between any two switches - 5 --- - - 2 5- Ω OFF Switch Leakage Current IL (Max) All switches OFF , VIS = 18V 31 8 ±100 ±1000 - ±1 ±100 (Note 2) nA STATIC CONTROLS Input Low Voltage V IL (Max) OFF switch IL < 0.2µA - 5 1.5 - - 1.5 V -1 0 3 - - 3 V -1 5 4 - - 4 V Input High Voltage V IH (Min) ON switch see RON characteristic - 5 3.5 3.5 - - V -1 0 7 7 - - V -1 5 1 1 1 1 - - V Input Current I IN (Max) Any control VIN = 0, 18V NOTES: 1. Maximum current through transmission gates (switches) = 25mA. 2. Determined by minimum feasible leakage measurement for automatic testing.

Electrical SpecificationsTA = 25oC PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITSFIGURE fIS (kHz) R L (kΩ ) VIS (V) (Note 3) VDD (V) DYNAMIC CROSSPOINTS Propagation Delay Time, (Switch ON) Signal Input to Output t PHL , tPLH 5 - 10 5 5 - 30 60 ns 10 10 - 15 30 ns 15 15 - 10 20 ns C L = 50pF; tR , tF = 20ns Frequency Response (Any Switch ON) f3dB 16 1 1 5 10 - 40 - MHz Sine Wave Input, Sine Wave Response (Distortion) THD 1 1 5 10 - 0.5 - % Feedthrough (All switches OFF) FDT 1.6 1 5 10 - -80 - dB Sine Wave Input Frequency for Signal Crosstalk FCT 7-1 1 0 1 0 Attenuation of 40dB Sine Wave Input - 1.5 - MHz Attenuation of 110dB - - - - - 0.1 - kHz Capacitance: C IS Xn to Ground - - - 5 - 15 - 18 - pF Yn to Ground - - - 5 - 15 - 30 - pF Feedthrough C DYNAMIC CONTROLS Propagation Delay Time: t PZH 8R L = 1kΩ , C L = 50pF, tR , tF = 20ns 5 - 300 600 ns Strobe to Output (Switch Turn-ON to High Level) 10 - 125 250 ns 15 - 80 160 ns Propagation Delay Time: t PZH 9R L = 1kΩ , C L = 50pF, tR , tF = 20ns 5 - 110 220 ns Data-In to Output (Turn-ON to High Level) 10 - 40 80 ns 15 - 25 50 ns Propagation Delay Time: t PZH 10 R L = 1kΩ , C L = 50pF, tR , tF = 20ns 5 - 350 700 ns Address to Output (Turn-ON to High Level) 10 - 135 270 ns 15 - 90 180 ns Propagation Delay Time: t PHZ 8R L = 1kΩ , C L = 50pF, tR , tF = 20ns 5 - 165 330 ns Strobe to Output (Switch Turn-OFF) 10 - 85 170 ns 15 - 70 140 ns Propagation Delay Time: t PZL 9R L = 1kΩ , C L = 50pF, tR , tF = 20ns 5 - 210 420 ns Data-In to Output (Turn-ON to Low Level) 10 - 110 220 ns 15 - 100 200 ns Propagation Delay Time: t PHZ 10 R L = 1kΩ , C L = 50pF, tR , tF = 20ns 5 - 435 870 ns Address to Output (Turn-OFF) 10 - 210 420 ns 15 - 160 320 ns 20 log V OS V IS

Data-In to Strobe, Address tS 8, 10 R L = 1kΩ , C L = 50pF, tR , tF = 20ns 5 - 95 190 ns 10 - 25 50 ns 15 - 15 30 ns Minimum Hold Time Data-In to Strobe, Address t H 8, 10 R L = 1kΩ , C L = 50pF, tR , tF = 20ns 5 - 180 360 ns 10 - 110 220 ns 15 - 35 70 ns Maximum Switching Frequency f Ø R L = 1kΩ , C L = 50pF, tR , tF = 20ns 5 0.6 1.2 - MHz 10 1.6 3.2 - MHz 15 2.5 5 - MHz Minimum Strobe Pulse Width t W 8 5 - 300 600 ns 10 - 120 240 ns 15 - 90 180 ns Control Crosstalk, Data-In, Address or Strobe to Output

6 Square Wave Input;

t R , tF = 20ns 10 - 75 - mV PEAK -1 0 1 0 Input Capacitance C IN Any Control Input - - 5 7.5 pF NOTE: 3. Peak-to-peak voltage symmetrical about . Electrical SpecificationsTA = 25oC (Continued) PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITSFIGURE fIS (kHz) R L (kΩ ) VIS (V) (Note 3) VDD (V) V DD

0000 X1Y1 0001 X1Y3

1000 X2Y1 1001 X2Y3

0100 X3Y1 0101 X3Y3

1100 X4Y1 1101 X4Y3

0010 X1Y2 0011 X1Y4

1010 X2Y2 1011 X2Y4

0110 X3Y2 0111 X3Y4

1110 X4Y2 1111 X4Y4

(NOTE) A A A (NOTE) B B B (NOTE) C C C (NOTE) D D D VSS VDD A B C D DQ ø ø LATCH ø = 1 ENABLES DATA TG TG TG TG TG TG TG TG TG TG TG TG TG TG TG TG 9 1 12 13 X4X3X2X1 DQ ø ø p n ø ø p n DETAIL OF LATCHES TO OTHER DECODER GATES/LATCHES VDD VDD VSS IN OUT Q DETAIL OF TRANSMISSION GATES (NOTE) STROBE (NOTE) DATA IN VDD VSS NOTE: INPUTS PROTECTED BY COS/MOS PROTECTION NETWORK (1 OF 16) LEVEL TRIGGERED

FIGURE 1. QUIESCENT CURRENT TEST CIRCUIT FIGURE 2. INPUT CURRENT TEST CIRCUIT