CAP3001A

CAP3001A MICRONAS | Alldatasheet

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Edition April 4, 1996 6251-365-1DS PRELIMINARY DATA SHEET MICRONAS INTERMETALL MICRONAS

Contents, continued Page Section Title 31 4. Starting the Processor 31 5. Synthesizer 32 6. Application Notes 33 7. Typical Application Circuit 34 8. Index 36 9. Data Sheet History

1. Introduction The CAP 3001 A Car Audio Processor presents the one- chip solution for a highly integrated car radio concept. It is housed in a 68-pin Plastic Leaded Chip Carrier Pack- age. The CAP 3001 A Car Audio Processor is a new CMOS processor to be used for car radio systems. The application consists essentially of the following components: – conventional FM tuner, FM–IF stage and FM demodu- lation – conventional AM tuner and IF stage – Car Audio Processor CAP 3001 A – microcontroller – analog audio sources – digital audio source 1.1. Features – stereo decoder – baseband audio processing – ignition noise canceller – synthesizer with fast tuning – AM tuning for 450 to 460 kHz or 10.7 MHz IF – AM IF processing (450 to 460 kHz) – AM stereo (C-QUAM) demodulation – ARI/RDS processing – PDAI Programmable Digital Audio Interface – A/D converter – D/A converter with eightfold oversampling filter. 2. Functional Description 2.1. Architecture The architecture of the CAP 3001 A processor com- prises three main function blocks: 2.1.1. DSP Block The DSP block consists of a “General Purpose16-Bit Digital Signal Processor” which handles 24 million in- structions per second. The data word length is 16 bits and the hardware multiplier operates with an initial word length of 1610 with a 20-bit result. The memory covers 2561625610 bit RAM and 2 k instruction ROM. 2.1.2. Digital Part A main portion consists of hardwired digital filters, such as decimation filters for the A/D converters and interpo- lation filters for D/A converters. The modulators for ARI/ RDS and pilot tone, as well as the complete circuitry for the ignition noise canceller are realized digitally. The log- ical conclusion for a higher integration is the incorpora- tion of the synthesizer for AM and FM tuning into this hardware block. Naturally the customary serial inter- faces for digital audio signals are also included. 2.1.3. Analog Part In the analog part various input switches, A/D converters and D/A converters are combined. Five A/D converters handle the conversion of analog signals into digital sig- nals. Two of these are specially designed for high quali- ty, one in particular for the conversion of an independent signal path for ARI/RDS signals and the remaining two to be used for the evaluation of analog signals of a lower quality standard (information on field strength and infor- mation from potentiometers). Two D/A converters, each equipped with an eightfold oversampling filter, generate analog output signals. These two outputs can be split up and distributed via four independently adjustable vol- ume control switches into four output stages.

Fig. 2–1: CAP 3001 A block diagram DSP Output Buffer LF LR RF RR Over- sampled D/A Over- sampled D/A Analog Volume Analog Volume Analog Volume Analog Volume WSO SDIN2 SDOUT SCLKOProgrammable Digital Audio Interface ERR WSI SCLKI SDIN1 DSP Core Stereo Matrix Tone Control Pilot Filter Loudness Deemphasis Volume Balance Soft Blend Beep Generator Stereo Detection Stereo PLL Filter Blank Search Multipath Detection FM/AM-Level Detection ARI Decoding (SK + DK) RDS Demodulation DSP Input Buffer FM-Noise Reduction FM-Noise Detection Pilot Mixer ARI/RDS Mixer A/D 0 A/D 1 A/D 2 A/D3 A/D 4 Input Select Input Select Input Select L+R L – R ClockIM-Bus/I Interface Auxiliary Digital Outputs Auxiliary Digital InputsSynthesizer CLKOUT QX1 AMLEVEL MPLEVEL FMLEVEL POT5/AVC POT4 POT3 POT2 AUXL AUXR TAPEL MPX0 MPX Decoder AM- Mixer AMR AML or AMIF TAPER POT1/MPX1 FMIN AMIN FM TUNOUT AMTUNOUT TI1 TI2 TI3 TO1 TO2 TO3 IMDATA IMCLOCK IMIDENT AMIF L–R L+R High Blend CQUAM Demodulation Noise Reduction Listed features depending on software version QX2/ECLK

2.1.4. Operating Modes The CAP 3001 A possesses 4 main operating modes: 1) MPX-mode In this mode, the CAP 3001 A receives the multiplex sig- nal of an FM transmission, containing sum and differ- ence channel, the pilot tone and the signals needed for travel information (ARI, RDS). The FM-demodulation has to take place inside the conventional tuner. The mix- ing of the difference band is done by an analog mixer in front of the A/D-converters in order to achieve the neces- sary quality for FM stereo. The ARI and RDS signals and the pilot tone are extracted digitally. 2) AF-mode In this mode the CAP 3001 A works transparently; the in- coming signals are only A/D-converted and then trans- mitted to the DSP core. 3) XDS-mode In this mode there is an external digital source (XDS, e.g. a CD player) which sends its digital data to the CAP 3001 A for further processing and for the reconverting to ana- log signals. The CAP 3001 A can be adapted to the sam- pling rate prescribed by the external digital source; in addition the input systems of the CAP 3001 A remain ac- tive in order to monitor the traffic information (ARI/RDS). 4) AM-IF mode In this mode, the CAP 3001 A receives input signals in the AM-IF range (i.e. 450 to 460 kHz). By a special ana- log mixer in front of the A/D conversion, the AM signal is mixed down to a frequency of 19 kHz. AM mono and ste- reo (C-QUAM) are demodulated in the DSP software. CAP 3001 A FM FM Tuner IF AM Tuner & IF AMIF MPX FMLEVEL FMTUNOUT FMOSCIN AMOSCIN AMTUNOUT µController Fig. 2–2: CAP 3001 A system overview LF LR RF RR

After buffering (ABUF) and switching (AMUX) in the AF- mode the signals are converted into digital form by 2 A/D converters (ADCs). Their output is 1 bit at a rate of 8.208 MHz; in each of the two channels in the CAP 3001 A there is a cascade of 3 lowpass filters (LPF02, LPF23 and LPF34), which suppresses the high-frequency noise produced by the ADCs. The outputs of the filters LPF34 are 16 bits wide and are sampled with 38 kHz; these samples are transmitted via the input buffer to the DSP core. After processing in the DSP, the samples are interpolated to the eightfold sampling rate and converted into analog shape by 2 D/A converters (DACs), filtered (ALPF) and optionally attenuated (AVOL) to feed the power amplifiers which produce the signals for four loud- speakers. It is assumed that the process of stereo multiplexing used in radio broadcasting is known. The main FM-mod- ulator can be modulated by the sum signal of left and right channel (in baseband), a pilot tone, the difference channel (AM-modulated, suppressed carrier), an op- tional ARI signal (AM-modulated, unsuppressed carrier) and optionally up to 3 SCA signals (FM-modulated). The composite signal is the so-called MPX signal. So a vari- ety of signals ride “piggy-back” on the main carrier, which was originally assigned only for monophonic transmission. In the CAP 3001 A, the SCA signals are regarded as disturbing signals while the others are re- garded as useful. In the MPX-mode there is an analog mixer AMIX in front of the ADCs. It mixes the difference band down to base- band. The sum channel and the difference channel are then treated like the other baseband signals. Digital quadrature mixers ARIMX and PILMX extract the ARI- information and the information of the pilot signal, re- spectively. By means of digital mixers the pilot tone and the ARI sig- nal are mixed down to zero intermediate frequency in quadrature representation, where their information is sampled and sent to the DSP core. The demodulation of the ARI signal is done by the DSP software. The band- width of this ARI channel is sufficient to allow demodula- tion of an RDS (Radio Data System) signal by DSP soft- ware as well. Beside these main blocks, there are other systems. The analog field strength information FS deliv- ered by AM and FM tuners is A/D-converted; after low- pass-filtering (LPF06) the samples are sent to the DSP core, where the information could be used to control some parameters of the entire system. Other input sig- nals, such as signals from an external microphone and from external potentiometers are selected by an analog multiplexer, A/D-converted, lowpass-filtered and sent to the DSP or to the controller via the IM-bus interface (IMIF). The IM-bus interface is also able to receive data from the external microcontroller and to control the sys- tems on the CAP 3001 A. 2.1.5. Analog Input Systems Fig. 2–3 shows all analog inputs and functions of the switches S0 to S3. MPX0 AML TAPEL AUXL AMR TAPER AUXR MPX1 POT2 POT3 POT4 POT5/ AVC FMLEVEL MPLEVEL AMLEVEL Main 1 Main 2 ARI/RDS Pot Level Fig. 2–3: Analog input systems 420 to 430 kHz 38 kHz POT1/ 2.1.6. Buffers ABUF The analog input buffers have to adjust the individual de- sired input levels in order to cover the entire volume range of the A/D-converters. The inputs can be divided into two groups: those which have to be connected via external capacitors, and those that are DC-coupled. One of these inputs, the POT5/ AVC-input, uses the same pin, but is DC-coupled if used as POT5, and AC-coupled if used as AVC. Note: Input pins POT2 to POT5 are switchable to digital outputs via the IM-bus interface. This feature is made possible by open drain transistors and external pull-up resistors down to 1 kΩ .

2.1.7. Stereo Mixer AMIX This analog demodulator mixes the incoming multiplex signal with the PLL-synchronized 38 kHz subcarrier in order to get the difference channel in baseband. The phase of the mixer signal is locked to the phase of the digital pilot demodulator; the phase shift between the two signals has to be compensated by the signal proces- sor’s Stereo PLL software. The realized modulator consists of an analog multiplex- er switching among the original input signal, the inverted input signal and zero input. Fig. 2–4: Difference channel mixing signal m(t) /C00421 T_0 T_0 T_0/C00431/f_0/C00431 The desired fundamental 38 kHz component includes an additional factor of 1.10266 which has to be taken into account in the dematrix-software of the signal proces- sor. 2.1.8. AM Mixer AMMIX This analog modulator mixes the incoming AM-IF signal down to approximately 19 kHz. Just like the AMIX stereo mixer it uses an amplitude discrete signal instead of a si- nusoidal signal. The realized modulator consists of an analog multiplex- er switching among the original input signal and the in- verted input signal. The mixing frequency of this mixer is typically between 430 and 440 kHz and can be se- lected in approximately 2 kHz steps in order to choose the desired AM IF frequency. 2.1.9. Multiplexers AMUX The analog multiplexers allow the selection of one of the input signals for each signal path. 2.1.10. A/D-Converters ADC The A/D-converters are realized as pulse density modu- lators (PDMs) running at a clock frequency of f_s0/C00438.208 MHz. The ADC0, ADC1 and the ADC2 are high quality double-loop PDMs with one external capaci- tor whereas ADC3 and ADC4 are low quality PDMs with- out any external capacitor. 2.1.11. Digital Signal Processing Block 2.1.12. Digital Filter Sections After analog to digital conversion, the input signals are filtered by means of digital filters in order to decimate the high frequency PDM signals to an appropriate sampling rate. The second purpose of these filters is to suppress unwanted out-of-band signals and to shape the input signals to the desired response. After being processed in the DSP section, the digital samples are interpolated to a higher rate before being converted to the analog do- main. The individual filter blocks can be seen in Fig. 2–5 and 2–6. Fig. 2–5 shows filter sections for the A/D side whereas in Fig. 2–6, filter blocks for the interpolation pro- cess on the D/A side can be seen. In the text of the CAP

3001 A data sheet, the filter blocks are referred to with

the names indicated in the schematics. Most of the filters are designed as multirate FIR blocks. Fig. 2–7 shows the overall (A/D to D/A) passband char- acteristics of the main channels in TAPE or AUX mode. The shown 3 dB bandwidth is more than 18 kHz. Fig. 2–8 shows the same for the MPX case. An additional pilot notch filter (19 kHz) suppresses higher frequencies. In case of a locked stereo PLL, the suppression is ideal. Fig. 2–9 depicts the characteristics of the ARI/RDS bandpass. The near-by difference channel is attenuated sufficiently in order to minimize disturbing effects in the weak ARI/RDS signal. An additional lowpass with roll-off characteristics is done in the DSP software. In order to suppress out-of-band signals, the CAP 3001 A is equipped with digital interpolation filters. These filters attenuate alias frequencies of up to eight times the sampling frequency by at least 50 dB. The in- terpolation block consists of three cascaded linear phase FIR filters. A simple sample and hold filter serves for the interpolation to the operating rate of the D/A con- verter. The overall interpolation rate is therefore 32. See Fig. 2–10 for the passband characteristics of the inter- polation filter (plotted for 44.1 kHz sampling rate) and Fig. 2–11 for the stopband characteristics.

2.1.13. Digital Mixing Systems 2.1.13.1. Pilot Demodulator PILMX The entire system is synchronized with the pilot tone of the FM-stereo channel. In the pilot-demodulator 2 mix- ers working in quadrature are used. The quadrature mix- er is the phase detector of the PLL; the other parts of the PLL (loop filter and VCO) are realized in the DSP. The inphase mixer outputs information concerning the level of the pilot tone to the DSP to allow a decision “FM-ste- reo” or “FM-mono”. The time relation between the mixer sequences of stereo-demodulator and pilot-demodula- tors is fixed. A D LPF 02 36 A D A D ASU LPF 23 3 LPF 34 2LPF 02 36 ASU LPF 23 3 LPF 34 2 ASU HIGH PASS ASU DETECT LPF LPF 35 8LPF 35 8 PILMIX PILMIX LPF 01 18 LPF 12 2 LPF 24 6ARI MIX LPF 45 4LPF 24 6ARI MIX LPF 45 4 A D LPF 06 540 A D LPF 05 864 PILOT NOTCH AMMIX DSP AMMIX Main 1 Main 2 ARI/ RDS Level POT PILOT NOTCH Fig. 2–5: Digital signal processing blocks, input side INT

2 INT

A INT D A DSP Fig. 2–6: Digital signal processing blocks, output side NOISE SHA- PING

Fig. 2–7: Overall response TAPE/AUX channel /C00423 02 8 1 2 1 6 1 84 6 10 14 19 kHz dB f gain Fig. 2–8: Overall MPX response sum channel /C00423 f 2 8 12 16 184 6 10 14 19 kHz gain dB Fig. 2–9: ARI/RDS bandpass characteristic /C004250 /C0042100 0 50 100 kHz f gain dB

Fig. 2–10: Digital interpolation filter, passband characteristic /C00423 f dB gain Fig. 2–11: Digital interpolation filter, attenuation /C004250 /C004280 0.0 50 100 150 200 350 kHz 250 300 f dB gain 2.1.13.2. ARI Mixer ARIMX The ARI-information in the range of 57 kHz is mixed down to a zero intermediate frequency by the two ARI mixers, whose mixer signals are again in quadrature. The reason for using two paths is that the demodulation is asynchronous in general; in the DSP there should be an operation which performs the square root of the sum of the squares of the two input signals. The quality re- quirements of the square rooting should not be very high. Because of the phase lock of pilot tone and ARI carrier in the FM-stereo-mode, a synchronous demodu- lation seems to be possible; in this case the demodu- lated ARI signal would be identical with the signal of the inphase path. The chosen structure has another potential advantage, for processing the radio data system (RDS) in Europe. This signal is a part of the MPX-signal; its subcarrier fre- quency is the same as that of the ARI-signal but it is rec- ommended that the two subcarriers are in quadrature. So the two paths of the ARI demodulation subsystem make the information of the ARI-signal and of the RDS- signal available to the DSP, where both can be demodu- lated if desired.

2.1.14. FM Noise Canceller (ASU) The FM Noise Canceller removes peak noise from the audio signal. No external circuitry is required. All filters, delays and the control section are implemented digitally. The function is split into two sections: – The noise detection searches for energy in the non- audio range by means of a highpass filter. The output of this filter is compared with a DSP-controlled thresh- old. If this threshold is exceeded the interpolation unit is triggered. The 19 kHz pilot tone is removed before the audio signal enters the detection highpass. Pro- grammable delay adjustment makes sure of the cor- rect timing between peak detection and peak inter- polation. – The interpolation circuit substitutes a peak-corrupted sample by the mean value of the non-corrupted adja- cent samples. Once a trigger comes from the detec- tion circuit, a programmable number (0 to 15) of successive samples is interpolated. All functions work on a 228 kHz sampling rate. At this rate the peaks are still small enough (not widened by the final decimation filters) to be removed effectively. 2.1.15. Analog Output Systems 2.1.16. D/A-Converters DAC The D/A-converters used are of the oversampling type. The samples to be converted at their sampling rate f_s are first interpolated to 8 x the sampling rate and then oversampled to a higher rate f_NS where noise shaping is performed. The output of the noise shaper is then con- verted using a highly linear D/A-converter. Its noise pow- er density increases with increasing frequency, the re- sidual noise in the baseband is very low. Within this application the DAC has to be adapted to the different modes. The digital sources (e.g. CD-player) must supply the proper clock rate in order to drive the DAC with a stable clock rate locked to the sampling rate. The clock is derived from the clock line SCLK of the PDAI bus. 2.1.17. Lowpass-Filters ALPF The analog lowpass-filters behind the DACs eliminate the high-frequent noise in order to avoid any distortions in the AM frequency range. 2.1.18. Volume Control AVOL The analog volume control together with the digital vol- ume control implemented in the digital signal proces- sor’s software provide a large volume control range. The analog volume control itself covers a range of 45 dB in 1.5 dB steps and includes an additional mute position. A sensible splitting of the total gain v_tot between the digital gain v_dig and the analog gain v_anlg is: v_tot v_anlg v_dig v_tot/C01190 dB 0 dB v_tot /C004245 dB/C0116v_tot/C01160 dB v_tot 0 dB v_tot/C0116/C004245 dB /C004245 dB v_tot45 dB All control bits for the hardware section are first ad- dressed to the DSP core program. In case of hardware read-registers the bits are transmitted to the DSP core, stored in the DSP RAM and so they are available for the controller via the DSP’s IM-bus interface.

2.1.19. CAP 3001 A - Programmable Digital Audio In- terface (PDAI) The PDAI is the digital audio interface between the CAP

3001 A and external digital sources such as CD/DAT

player or additional external processors. It offers a large variety of modes and should therefore cover most of the digital audio standards (I 2S-compatible formats). Fig. 2–12 shows a standard application with an external digital source and a second CAP 3001 A. The interface is split into the input section and the output section: SDOUT SCLKO SDIN2 WSO analog input analog output CD-PLAYER CAP 3001 A CAP 3001 A or ext. Proc. ERR WSISCLKI SDIN1 Fig. 2–12: System Configuration CLKOUT Input Section: – SCLKI serial clock input – SDIN1 serial data input 1 – WSI word select input – ERR error line input Output Section: – SCLKO serial clock output – SDOUT serial data output – SDIN2 serial data input 2 – WSO word select output Fig. 2–13 shows the timing of the signals and the pro- grammable features. The programming is done by writ- ing the correct bit patterns into the DSP output buffer. This must be handled by the DSP software.

SCLK_IN/OUT WS_IN/OUT 16, 24, 32 x Tbck Tbck

1 Tbck: programmable

MSB/LSB first programmable 0, 8, 16 x Tbck: programmable delay polarity programmable Tbck/C00431/Fbck Fbck/C004332/C0064Fsaudio or Fbck/C004348/C0064Fsaudio or Fbck/C004364/C0064Fsaudio Fig. 2–13: Timing of the signals ERR The modes are: – 16-bit wordframe in this case the programmable delay is set to zero; – 24-bit wordframe in this case the programmable delay is set either to 0 or to 8/C0032Tbck; this allows left or right adjusted handling of the 16 data bits – 32-bit wordframe in this case the programmable delay is set either to 0 or to 16/C0032Tbck; this allows left or right adjusted handling of the 16 data bits. In all modes: MSB or LSB-first can be selected; one bit delay between active slope of WSI/O and first wordframe bit is programmable; the polarity of WSI/O can be programmed ; in the 24 and 32-bit wordframes the open data bit loca- tions are MSB or LSB extended (depends on left or right adjustment). Input format and output format can be programmed sep- arately. The restrictions are: A 24-bit wordframe can only be sent if a 24-bit word- frame is also received. In the analog input mode, the 24-bit wordframe output is not allowed.

2.1.20. The IM Bus Interface of the CAP 3001 A MSB LSB shift MSB LSB shift IM Bus Control IMDATA ÍÍÍ ÍÍÍ ÍÍÍ ÍÍÍ ÍÍÍ ÍÍÍ ÍÍÍ ÍÍÍ IABF IDBF Data Bus IMCLK IMIDENT Fig. 2–14: IM-bus interface The buffer part consists of a unidirectional address buff- er IABF with a word length of 10 bit and the bidirectional data buffer IDBF with a word length of 16 bit. It is only possible to write to the address buffer from the peripher- al equipment. By means of the IM-bus interface it is possible, for exam- ple, to alter the filter coefficients of the CAP 3001 A. For this purpose the microcomputer writes an address and a data word to the appropriate buffers IABF and IDBF. The 10-bit address contains an address part of 8 bits (bit 9 to bit 2), a read/write bit (bit 0) and an additional bit (bit 1) which may be used, for example, for select- ing one of the two address counter banks (Fig. 2–15). Bits 0 and 1 have the following effect: ABNK /C00430 selects address counter bank 1 ABNK /C00431 selects address counter bank 2 R/W /C00430 selects Write, microcomputer wants to write R/W /C00431 selects Read, microcomputer wants to read MSB R/W ABNKLSBAddress Fig. 2–15: Address format The following convention is applicable to the data trans- fer: The last bit written always becomes the MSB of IABF or IDBF. If fewer bits are transferred than the respective buffer size, the unused bits are set to zero in IDBF but remain undefined in IABF. For the output: the first bit out- put is always the LSB of the IDBF. 2.1.21. Description of the IM Bus The IM-bus consists of three lines for the signals Ident (IMIDENT), Clock (IMCLK) and Data (IMDATA). The clock frequency range is 50 Hz to 1 MHz. Ident and clock are unidirectional from the controller to the slave ICs, Data is bidirectional. Bidirectionality is achieved by us- ing open-drain outputs with on-resistances of 150 Ohm maximum. The 2.5 kΩ pull-up resistor common to all out- puts is incorporated in the controller. The timing of a complete IM-bus transaction is shown in Fig. 2–16. In the non-operative state the signals of all three bus lines are High. To start a transaction, the con- troller sets the ID signal to Low level, indicating an ad- dress transmission, sets the CL signal to Low level and switches the first bit on the Data line. Then 10 address bits are transmitted, beginning with the LSB. Data take- over in the slave ICs occurs at the positive edge of the clock signal. At the end of the address byte the ID signal goes High, initiating the address comparison in the slave circuits. In the addressed slave the IM-bus interface switches over to Data read or write, because these func- tions are correlated to the address. In the case of a read operation, a fixed wait period has to be observed. This period is defined by the IM-bus han- dler in the DSP software. For practical reasons this part of the program does not run at the full sampling rate. It is recommended to place the IM-bus handler in a “low speed” time slice in order to save processing power. For a write operation this wait period does not have to be observed, but please note that the maximum rate of IM- bus transmissions is normally limited by the DSP soft- ware. Also controlled by the address the controller now trans- mits sixteen clock pulses, and accordingly two Bytes of data are written into the addressed IC or read out from it, beginning with the LSB. The completion of the bus transaction is signalled by a short Low state pulse of the ID signal. This initiates the storing of the transferred data. A bus transaction may be interrupted for up to 10 ms.

H L H L H L Ident Clock Data 12 34 6789 1 0 1 1 1 2 1 3 LSB Address MSB LSBData MSB A B C Section A Section B Section C H L Data H L Clock H L Ident Address LSB Address MSB Data MSB tIM1 tIM3 tIM2 tIM7 tIM8 tIM9 tIM4 tIM5 tIM6 tIM10 Fig. 2–16: IM Bus waveforms

2.1.22. Clock Generation The CAP 3001 A processor has an integrated clock os- cillator which is crystal-controlled and oscillates with the frequency f ECLK /C004316.416 MHz. All components of the oscillator are integrated except for the quartz crystal. This is connected to the QX1 and QX2 oscillator pins. The crystal input QX2/ECLK can be used to supply the CAP 3001 A externally with the required clock. In this case no crystal is needed. Following the clock oscillator is a frequency multiplier with a factor of 3. The output of the frequency multiplier delivers the f ICLK internal clock frequency, by which the DSP Core is clocked. There is the possibility of pulling the fECLK oscillator fre- quency in a range of 350 ppm, depending on the applica- tion and the used crystal. This makes it possible to syn- chronize the CAP 3001 A to the incoming pilot tone signal in the case of MPX reception. Table 2–1: Oscillator characteristics DCO Content Frequency 011111111B 000000000B 100000000B fECLKmin fECLK fECLKmax DCO Clock Control Register Clock Oscillator Frequency Multiplier Clock Pulse Shaper and Frequency Divider Φ 1 Φ 2 Φ 3 Φ 4 fICLK CLKOUT fECLK Fig. 2–17: Clock generator connections GNDD 1 nF ECLK 100 nF external option

1. Specifications 3.1. Outline Dimensions Fig. 3–1: 68-Pin Plastic Leaded Chip Carrier Package (PLCC68 ) Weight approximately 4.8 g Dimensions in mm 1.2 x 45° 24.2 0.1± 25+0.25 4327 25+0.25 619 x 45° 0.4570.2 0.711 1.9 1.5 4.05 0.1 4.75±0.15 1.27 0.1± 2.4 1.27 0.1± 24.2 0.1± 1+0.2 2.4 3.1.1. Pin Connections and Short Descriptions NC = not connected; leave vacant LV = if not used, leave vacant S.T.B. = shorted to BAGNDI if not used DVSS = if not used, connect to DVSS X = obligatory; connect as described in circuit diagram AHVSS = connect to AHVSS Pin No. Connection Pin Name Type Short Description PLCC 68-pin (if not used)

1 GNDA FMLEVEL IN FM fieldstrength input

2 GNDA POT5/AVC IN/OUT DC voltage input

3 GNDA POT4 IN/OUT DC voltage input

4 GNDA POT3 IN/OUT DC voltage input

5 GNDA POT2 IN/OUT DC voltage input

6 GNDA POT1/MPX1 IN/OUT DC voltage input

7 AGNDC MPX0 IN FM MPX signal input

8 AGNDC AML IN AM left baseband input

9 BAGNDC AMR IN AM right baseband input

10 BAGNDC AUXR IN Auxiliary audio input right

11 BAGNDC AUXL IN Auxiliary audio input left

12 BAGNDC TAPER IN Analog tape input right

Pin Connections and Short Descriptions, continued Pin No. Connection Pin Name Type Short Description PLCC 68-pin (if not used)

13 BAGNDC TAPEL IN Analog Tape input left

14 BAGNDC PDMC3 EXT PDM capacitor connection

15 BAGNDC PDMC2 EXT PDM capacitor connection

16 BAGNDC PDMC1 EXT PDM capacitor connection

17 LV BAGNDC OUT Buffered internal ground

18 X AGNDC EXT Internal analog ground

19 X VREF1 IN Analog ground reference

20 X GNDA SUPPLY Analog ground

21 X VSUPA SUPPLY Analog supply voltage

22 LV LF OUT Analog output left front

23 LV LR OUT Analog output left rear

24 LV RR OUT Analog output right rear

25 LV RF OUT Analog output right front

26 X VREF2 IN Analog ground reference synthesizer

27 LV FMTUNOUT OUT FM tuning voltage output

28 LV TUNFB IN Tuning voltage feedback input

29 LV AMTUNOUT OUT AM tuning voltage output

30 VREF2 VSUP2 SUPPLY Analog supply voltage synthesizer

31 VREF2 VSUP1 SUPPLY Analog supply voltage synthesizer

32 LV AMOSCREF EXT AMOSC capacitor connection

33 LV AMOSCIN IN AM oscillator signal input

34 LV FMOSCREF EXT FMOSC capacitor connection

35 LV FMOSCIN IN FM oscillator signal input

36 X GNDS1 SUPPLY Analog ground synthesizer

37 GNDD TESTEN IN Test Mode Enable

38 X QX1 IN Crystal

39 X QX2/ECLK IN Crystal/External clock input

40 X RESET IN Reset input

41 X IMDATA IN/OUT IM-bus/I2C data input/output

42 X IMCLK IN IM-bus/I2C clock input

Pin Connections and Short Descriptions, continued Pin No. Connection Pin Name Type Short Description PLCC 68-pin (if not used)

43 X IMIDENT IN IM-bus ident input

44 GNDD TEOSC IN Test purpose

45 LV REFCLK IN Synthesizer Ref. Frequency input

46 LV1) TI1 IN Static digital input 1

47 LV1) TI2 IN Static digital input 2

48 LV1) TI3 IN Static digital input 3

49 LV SCLKO OUT Serial clock output

50 LV WSO OUT Serial word select output

51 LV SDOUT OUT Serial data output

52 LV SDIN2 IN Serial data input 2

53 LV ERR IN Serial error input

54 LV SCLKI IN Serial clock input

55 LV WSI IN Serial word select input

56 LV SDIN1 IN Serial data input 1

57 LV TO1 OUT Digital output 1

58 LV TO2 OUT Digital output 2

59 LV TO3 OUT Digital output 3

60 X GNDD SUPPLY Digital ground

61 X VSUPD SUPPLY Digital supply voltage

62 LV CLKOUT OUT Clock output

63 GNDD TP3 IN Test purpose

64 LV TP2 OUT Test purpose

65 LV TP4 OUT Test purpose

66 GNDD TP1 IN Test purpose

67 GNDA AMLEVEL IN AM fieldstrength input

68 GNDA MPLEVEL IN Multipath signal input

1) Depending on software version.

3.1.2. Pin Descriptions Pin1 – FMLEVEL Input for the FM field strength information. Pins 2 to 6 – POT5/AVC, POT4, POT3, POT2, POT1/MPX1 Inputs for a DC-control voltage (0V to V SUP ). These pins can also be used as digital outputs with an external pull- up resistor; the function and selection is controlled via IM/I 2C-bus. POT1/MPX1 also serves as a second MPX input for ARI/ RDS. POT5/AVC also serves as a highly sensitive microphone input. Pin 7 – MPX0 Input for the MPX signal in case of FM reception. Pin 8 – AML Input for left channel baseband audio; or for AM IF (450 to 460 kHz). Pin 9 – AMR Input for right channel baseband audio. Pin 10 – AUXR Input for additional audio sources, right channel. Pin 11 – AUXL Input for additional audio sources, left channel. Pin 12 – TAPER Input for right tape channel. Pin 13 – TAPEL Input for left tape channel. Pins 14 to 16 – PDMC3, PDMC2, PDMC1 Capacitor pins for the feedback loop of the high quality pulse-density modulators. Pin 17 – BAGNDC Buffered internal ground. This pin is the buffered internal ground connection for the external PDM capacitors. Pin 18 – AGNDC This pin serves as internal ground connection for the analog circuitry. It must be connected to analog ground with a 4.7 µF and a 100 nF capacitor in parallel. Pin 19 – VREF1 This pin must be connected separately to the single ground point. It serves as ground connection for the ana- log bias circuits. Pin 20 – GNDA This pin serves as ground connection for the analog sig- nals and NF parts of the synthesizer section. Pin 21 – VSUPA Analog supply voltage; power for the analog circuitry of the CAP 3001 A is supplied via this pin. Pin 22 – LF Left front speaker output. Pin 23 – LR Left rear speaker output. Pin 24 – RR Right rear speaker output. Pin 25 – RF Right front speaker output. Pin 26 – VREF2 This pin serves as ground connection for the synthesizer bias circuits and must be connected separately to the ground point of the tuner. Pin 27 – FMTUNOUT Tuning voltage for the FM oscillator. Pin 28 – TUNFB Feedback input for tuning voltage amplifier. Pin 29 – AMTUNOUT Tuning voltage for the AM oscillator. Pin 30 – VSUP2 Synthesizer supply voltage 2; power is supplied via this pin for the synthesizer output circuitry of the CAP 3001 A. Pin 31 – VSUP1 Synthesizer supply voltage 1; power is supplied via this pin for the synthesizer circuitry of the CAP 3001 A. Pin 32 – AMOSCREF Capacitor pin for AMOSCIN reference voltage. Pin 33 – AMOSCIN Input for the AM oscillator signal. Pin 34 – FMOSCREF Capacitor pin for FMOSCIN reference voltage. Pin 35 – FMOSCIN Input for the FM oscillator signal. Pin 36 – GNDS1 This pin serves as ground connection for the HF parts of the synthesizer section. Pin 37 – TESTEN Test mode enable Pin 38 – QX1 Crystal pin. This pin has to be connected with the crystal.

Pin 39 – QX2/ECLK Crystal pin. This pin has to be connected with the crystal or with an external clock signal. Pin 40 – RESET In the steady state, high level is required at this pin. A low level resets the CAP 3001 A. Pins 41 to 43 – IMDATA, IMCLK, IMIDENT Via these pins the CAP 3001 A sends and receives data to and from the controller. Pin 44 – TEOSC Test purpose. Pin 45 – REFCLK Input for the synthesizer reference frequency. Pins 46 to 48 – TI1, TI2, TI3 Static digital inputs; these signals can be used as a branch condition in the DSP software. If not used, they must be connected to GND. Pin 49 – SCLKO DAI-Bus: serial clock output. Pin 50 – WSO DAI-Bus: word select output; this is a control line to sep- arated left and right channel in the serial DAI stream. Pin 51 – SDOUT DAI-Bus: serial data output. Pin 52 – SDIN2 DAI-Bus: serial data input 2. Pin 53 – ERR DAI-Bus: error input. Pin 54 – SCLKI DAI-Bus: serial clock input. Pin 55 – WSI DAI-Bus: word select input; this is a control line to sepa- rate left and right channel in the serial DAI stream. Pin 56 – SDIN1 DAI-Bus: serial data input 1. Pins 57 to 59 – TO1, TO2, TO3 Digital outputs; the logical state can be defined by the DSP software. Pin 60 – GNDD This pin serves as ground connection for the digital sig- nals. Pin 61 – VSUPD Digital supply voltage. Power is supplied via this pin for the digital circuitry of the CAP 3001 A. Pin 62 – CLKOUT This output is used for clocking external hardware. Pin 63 – TP3 Test purpose. Pin 64 – TP2 Test purpose. Pin 65 – TP4 Test purpose. Pin 66 – TP1 Test purpose. Pin 67 – AMLEVEL Input for the AM field strength information. Pin 68 – MPLEVEL Input for the multipath information.

3.1.3. Pin Configuration 78910 29 30 31 32 33 34 35 36 37 38 39 27 28 654321 43424140 68 67 66 65 64 63 62 61 FMLEVEL POT5/AVC POT4 POT3 POT2 AUXR AUXL TAPER TAPEL PDMC3 PDMC2 PDMC1 AGNDC VREF1 GNDA VSUPA LF LR RR RF VREF2 FMTUNOUT TUNFB AMTUNOUT VSUP2 VSUP1 AMOSCREF AMOSCIN FMOSCREF GNDS1 TESTEN QX1 QX2/ECLK RESET IMDATA IMCLK IMIDENT TEOSC REFCLK TI1 TI2 TI3 SCLKO WSO SDOUT SDIN2 ERR SCLKI WSI SDIN1 TO1 TO2 TO3 GNDD VSUPD CLKOUT TP3 TP2 TP4 TP1 AMLEVEL MPLEVEL CAP 3001 A MPX0 AML AMR BAGNDC POT1/MPX1 Fig. 3–2: Pinning of the CAP 3001 A in PLCC68 package, top view FMOSCIN

3.1.4. Electrical Characteristics All voltages refer to ground. 3.1.5. Absolute Maximum Ratings Symbol Parameter Pin No. Min. Max. Unit TA Ambient Operating Temperature – /C004220 85 °C TS Storage Temperature – /C004255 125 °C VSUP Supply Voltage 21, 61 /C00420.3 1) 6 V VSUP1 Supply Voltage 31 /C00420.3 1) 6 V VSUP2 Supply Voltage 30 /C00420.3 1) 12 V PTOT Chip Power Dissipation 68-pin PLCC without heatspreader 21, 61, 30, 31 – 1300 mW dVSUP Voltage between VSUPA, VSUPD and VSUP1 21, 61, /C0042 0.5 0.5 V VI Input Voltage, all Inputs 1 to 17, 28, 32 to 35, 38, 39, 41 to 48, 52 to 56, 67, 68 /C00420.3 VSUP 0.3 V IO Output Current, all Outputs 22 to 25, 27, 29, 41, 49 to 51, 57 to 59, – 2) 1) Reversed supply 200 ms maximum. 2) The outputs are short-circuit proof (max. 5 seconds) with respect to supply and ground. 3) Total chip power dissipation must not exceed absolute maximum ratings. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only. Functional operation of the device at these or any other conditions beyond those indicated in the Recommended Operating Conditions/Characteristics of this specification is not implied. Exposure to absolute maxi- mum ratings conditions for extended periods may affect device reliability. 3.1.6. Recommended Operating Conditions at T A/C0043/C004220 to 85 °C, fECLK /C004316.416 MHz, typical values at Tj = 27 °C, duty cycle = 50 % Symbol Parameter Pin No. Min. Typ. Max. Unit VSUP Supply Voltage 21, 61 4.75 5.0 5.25 V VSUP1 Supply Voltage 31 4.75 5.0 5.25 V VSUP2 Supply Voltage 30 7.5 8.5 9.5 V

Recommended Operating Conditions, continued Symbol Parameter Pin No. Min. Typ. Max. Unit VECLKL ECLK Clock Input Low Voltage 39 – – 1.5 V VECLKH ECLK Clock Input High Voltage VSUP /C00421.5 – – V tECLKH tECLKL ECLK Clock Input High/Low Ratio 0.9 1.0 1.1 – fECLK ECLK Clock Input Frequency (see also chapter 3.1.7.) – 16.416 – MHz VREFCLKH Reference Clock Input High Voltage45 VSUPD –1.5 – – V VREFCLKL Reference Clock Input Low Voltage – – 1.5 V VREFCLK0 Reference Clock Input Open Circuit Voltage VSUP fREFCLK Refence Clock Input Frequency 1 16 MHz VFS DC Input Voltage FM, AM, MP level1, 67, 68 0 VSUP – VPOT/ MPXI DC Input Voltage POT5, POT4, POT3, POT2, POT1 (with I/C011820 mA) 2 to 6 0 VSUP – VIH High Level, Digital Inputs 46 to 50, 52 to 56 2.0 V VIL Low Level, Digital Inputs 0.8 V VREIL Reset Input Low Voltage 40 – – 0.8 V VREIH Reset Input High Voltage VSUP – 0.8V – – – VIMIL IM Bus Input Low Voltage 41 to 43 – – 1.5 V VIMIH IM Bus Input High Voltage 3.0 – – V fΦ I Φ I IM Bus Clock Frequency 0.05 – 1000 kHz tIM1 Φ I Clock Input Delay Time after IM Bus Ident Input 0 – – – tIM2 Φ I Clock Input Low Pulse Time 0.5 – – µs tIM3 Φ I Clock Input High Pulse Time 0.5 – – µs tIM4 Φ I Clock Input Setup Time before Ident Input High 0 – – – tIM5 write data Φ I Clock Input Hold Time after Ident Input High 0.25 – – µs tIM5 read data Φ I Clock Input Hold Time after Ident Input High defined by DSP software µs tIM6 Φ I Clock Input Setup Time before Ident End-Pulse Input 41 to 43 1.0 – – µs

Recommended Operating Conditions, continued Symbol Parameter Pin No. Min. Typ. Max. Unit tIM7 IM Bus Data Input Delay after Φ I Time Clock Input 0 – – – tIM8 IM Bus Data Input Setup Time before Φ I Clock Input 0 – – – tIM9 IM Bus Data Input Hold Time after Φ I Clock Input 0 – – – tIM10 IM Bus Ident End-Pulse Low Time 1.0 – – µs C PDM PDM Capacitor (Low Loss Type) 14 to 16 /C00425% 680 /C00415% pF C AGNDC AGNDC-Filter-Capacitor 18 3.3 µF Ceramic Capacitor in parallel 100 nF fSCLKI Input SCLKI Frequency 54 – – 3.1 MHz tSIJ Input SCLKI Phase Jitter – – 250 ps tSIW Input SCLKI Pulse Width 40 50 60 % tIDS Input Data Setup Time 56, 52 40 – – ns tIDH Input Data Hold Time 0 – – – tWSS Input WSI Setup Time Output WSO Setup Time 50, 55 40 – – ns tWSH Input WSI Hold Time Output WSO Hold Time 0 – – – 3.1.7. Recommended Crystal Characteristics Symbol Parameter Min. Typ. Max. Unit TA Ambient Operating Temperature /C004220 – /C004185 °C fP Parallel Resonance Frequency – 16.4161) – MHz ΔfS fS Accuracy of Adjustment – – /C003620 ppm ΔfS fS Frequency Deviation versus Tem- perature – – /C003640 ppm R r Series Resistance – – 15 Ω C 0 Shunt Capacitance 5.5 – 7 pF C 1 Motional Capacitance 25 30 – fF df Frequency pulling range 350 – – ppm 1) at CL/C004310.7 pF. Remark on defining the external load capacitance: Ex- ternal capacitors at each crystal pin to ground are re- quired. The higher the capacity, the lower the clock fre- quency results. Due to different layouts of customer PCBs, the matching capacitor size should be defined in the application.

MHz, typical values at VSUP and VSUP1 /C00435.0 V, VSUP2 /C00438.5 V, Tj= 27°C and duty cycle = 50 %. Symbol Parameter Pin No. Min. Typ. Max. Unit ZAII1 Analog Input Impedance (fsignal/C00431kHz, i/C004310 µA) AVC, MPX1, MPX0, AM, AUX, TAPE at Tj = 27°C at Tj = /C004220 to 85 °C 2, 6 to 13 35 43 kΩ ZAII2 Analog Input Impedance FM, AM, MP level 1, 67, 68 200 kΩ ZPOT Analog Input Impedance POT1...52 to 6 200 kΩ VOSCI0 Open Circuit Voltage FMOSCIN, AMOSCIN 33, 35 VSUP1 R OPOT Output Resistance POT1 to 5 as outputs, i/C01185 mA 2 to 6 80 Ω R OSCI Analog Input Resistance FMOSCIN, AMOSCIN, FMOSCREF, AMOSCREF at T j =27 °C at Tj =/C004220 to 85 °C 33, 35 3.2 2.1 3.6 3.6 4.2 6.5 kΩ kΩ pF R AO Analog Output Resistance LF, LR, RR, RF (f signal/C00431kHz, i/C00431 mA) at Tj = 27°C, at Tj =/C004220 to85 °C 22 to 25 470 440 600 730 790 Ω VMPX0/1I Input Voltage MPX0, MPX1 7, 6 2.0 VPP VAML/RI Input Voltage AML, AMR 8, 9 1.1 VRMS VTAPER/ TAPELI Input Voltage TAPER, TAPEL 12, 13 1.6 VRMS VAUXR/LI Input Voltage AUXR, AUXL 10, 11 1.1 VRMS VAVCI Input Voltage AVC 2 0.007 VRMS VAICL Analog Audio Input Clipping Level (defines 0 dBr) 6 to 13 Max. Input Voltage Max. Input Voltage +1 dB Max. Input Voltage + 2 dB ZAOL Analog Output Load 22 to 25 6 0.005 1 kΩ nF VAOV Maximum Analog Output Voltage LF, LR, RR, RF (output attenuation /C00430 dB, analog output load /C0117 100 kΩ ) Analog Input Digital Input 22 to 25 0.8 0.9 0.9 1.0 1.0 1.1 VRMS VAMOSC AM OSC Input Voltage 33 40 300 mV RMS fAMOSCI AM OSC Input Frequency Range 0.5 20 MHz

Characteristics, continued Symbol Parameter Pin No. Min. Typ. Max. Unit VFMOSCI FM OSC Input Voltage 35 40 300 mV RMS fFMOSCI FM OSC Input Frequency Range 60 150 MHz SNR AD SNR A/D (Noise measurement RMS un- weighted, BW/C004320 to 18000 Hz, input level/C0043/C004220 dBr, f signal/C00431kHz) 7 to 13 82 85 dB SNR DA SNR D/A Analog Attenuation/C00430 dB Analog Attenuation/C004345 dB in MUTE position (RMS, unweighted, BW/C004320 to 20000 Hz 1), input level/C0043/C004220 dBFS, fsignal/C00431kHz) 22 to 25 110 dB dB dB SNR RDS1 SNR A/D selected MPX ARI/RDS channel (Noise measurement RMS, un- weighted, BW/C004355 to 59 kHz, input level/C004355 mVPP fsignal/C004357 kHz) 6, 7 38 dB THD AD THD A/D (RMS, unweighted, BW/C004320 to 18000, input level/C0043/C00423 dBr, fsignal/C00431 kHz) 7 to 13 0.03 % THD DA THD D/A (BW /C004320 to 20000 Hz1), input level/C0043/C00423 dBFS, fsignal/C00431kHz, analog attenuation/C00430 dB) 22 to 25 0.01 % IMD AD Intermodulation Distortion A/D (fsignal/C004314 kHz15 kHz, input level sum/C00423 dBr, measuring 1 kHz intermodulation)2) 7 to 13 0.01 % XTALK1 Crosstalk attenuation within active audio channel pair (input level /C0043/C00423 dBr, f signal/C00431kHz, measur- ing with bandpass at 1 kHz)2) 8 to 13 70 dB XTALK2 Crosstalk attenuation from a non- selected audio input pair (input level/C0043/C00423 dBr, f signal/C00431kHz, measuring with bandpass at 1 kHz) 7 to 13 80 dB XTALK3 Crosstalk attenuation between audio input/output pairs (input lev- el/C0043/C00423 dBr, f signal/C00431kHz, mea- suring with bandpass at 1 kHz)2) 7 to 13, 22 to 25 100 dB

Characteristics, continued Symbol Parameter Pin No. Min. Typ. Max. Unit CHSEP MPX Stereo separation MPX 250 Hz to 6.3 kHz 6.3 kHz to 12.5 kHz (coupling capacitor on MPX input at least 1µF) dB dB SNR MPX 19 kHz Suppression of unwanted signals in MPX stereo reception: 19 kHz 38 kHz 57 kHz 114 kHz measuring with bandpass at f signal dB dB dB dB SNR RDS2 Alias Band Suppression in RDS Channel signal/C004357 kHz, input level/C004355 mVPP ) @ 171 kHz @ 285 kHz 6, 7 dB dB SNR AVC SNR A/D3 selected AVC channel (Noise measurement RMS unweighted, BW/C00430 to 4 kHz, input level/C0043/C004220 dBr, f signal/C00431 kHz) 2 40 dB SNR AD4 SNR A/D4 (Noise measurement RMS unweighted, BW/C00430 to 7 kHz, input level/C0043/C004220 dBr, f signal/C00431 kHz) 1, 67, 68 50 dB THD AVC THD A/D3 selected AVC channel (RMS unweighted, BW/C00430 to 4 kHz, input level/C0043/C00423 dBr, f signal/C00431 kHz) 2 2.2 % THD AD4 THD A/D4 (RMS unweighted, BW/C00430 to 7 kHz, input level/C0043/C00423 dBr, fsignal/C00431 kHz 1, 67, 68 3.2 % BW ADDA 3 dB Bandwidth A/D to D/A TAPE, AUX (not provided in production test) 10 to 13, 22 to 25 18 kHz BW DA 3 dB Bandwidth D/A @f s=32 kHz @f s=44.1 kHz (not provided in production test) 22 to 25 kHz kHz dG AD Channel deviation within active input pair: AUX, TAPE AM 8 to 13 0.5 0.7 dB dG DA Channel deviation within each output of: RR, RF, LR, LF Analog attenuation = 0 to/C004230 dB = /C004231.5 to/C004245 dB 22 to 25 0.5 0.9 dB

Characteristics, continued Symbol Parameter Pin No. Min. Typ. Max. Unit dG AVOL Analog Volume Step Size (/C004245 dB to 0 dB) 22 to 25 1.4 1.5 1.6 dB IREIL Reset Input Leakage Current 40 /C004210 – 10 µA ISUP Supply Current VSUPD VSUPA VSUP1 VSUP2 1.4 2.2 110 mA VIMOL IM Bus Data Output Low Voltage 41 – – 0.4 V VIMOH IM Bus Data Output High Voltage 2.8 – – V IIMOHL IM Bus Data Output High-Impedance Leakage Current /C004210 – 10 µA IIMIL IM Bus Input Leakage Current /C004210 – 10 µA VTOH VTOL Digital Output High Voltage Digital Output Low Voltage 57 to 59 4.0 – 0.4 V VTIH VTIL Digital Input High Voltage Digital Input Low Voltage 46 to 48 2.4 – 0.8 V VTUNOUT Synthesizer Output Voltage AMTUNOUT, FMTUNOUT 27, 29 1.1 – VSUP2 /C00421.1 V VAGNDC0 AGNDC Open Circuit Voltage 18 2.15 2.25 2.35 V R OUTAGND AGNDC Output Resistance at 27 °C at /C004220 to 85 °C 18 110 125 140 230 kΩ kΩ dVBAGNDC Dev. of BAGNDC from AGNDC Vol. 17, 18 /C004220 20 mV R OUTBAGND BAGNDC Output Resistance (fsignal/C00431kHz, i/C00430.1 mA) 17 6 Ω dVDAC Deviation of DC Level at Audio Out- puts from AGNDC Voltage 18, 22 to /C004220 20 mV IOUTSYNTH Synthesizer Current Source Accuracy 27, 29 3.3 330 500 6.5 740 µA PSRR Power Supply Rejection Ratio 1 kHz

20 Hz to 20 kHz

21, 61, 31, 30, 22 to 25 dB dVTUNOUT Residual Noise of Synthes. Output Volt. (BW 22Hz to 22 kHz, i/C00435 µA) 2.2 µV 1) CD-Mode, fs/C004344.1 kHz 2) unused analog inputs connected to ground

1. Starting the Processor After power-up, the crystal oscillator has to have been started before the Reset reaches high level. An addition- al wait time of 0.4 ms has to be taken into account be- cause of a DSP-internal self-test algorithm. Then a de- fined start of the system can take place. Fig. 4–1 shows the complete startup sequence of the typical application. The DCO register is loaded with a precisely defined- mean value. 2.4 V

4.75 VVSUPD

Reset > 0.4 ms> 1 ms Fig. 4–1: Startup sequence 5. Synthesizer With the synthesizer block in the CAP 3001 A, a PLL tun- ing system can be implemented for FM and AM receiv- ers. The signal picked up from the mixing oscillators of the FM and AM tuners can be fed to the synthesizer block by means of highly sensitive input pins. Freely pro- grammable dividers, operating with frequencies up to and over 100 MHz, scale the incoming signals to a refer- ence frequency of 25 kHz. This holds true even in the case of AM, which gives AM tuning a considerable speed improvement over common designs. In order to get a tuning step size of down to 300 Hz, the reference divider is also programmable. Incoming frequencies in the range of 0.5 MHz up to more than 100 MHz can be handled, so that the designer is free to choose either a

10.7 MHz or a 450 to 460 kHz IF frequency for the AM

case. The common reference frequency for AM and FM allows the implementation of a common PLL filter for the tuning output. FMOSCIN Programmable Divider (16 bit) Φ Reference Clock 16.416 MHz or external REFCLK Current Source Gain adjust AMOSCIN /C0042 /C0042 Filter Filter FMTUNOUT AMTUNOUT Program- mable Divider (10 bit) Fig. 5–1: Synthesizer block diagram FMOSCREF AMOSCREF

1. Application Notes CAP 3001 A AM audio MPX FM FMTUNOUT FMOSCIN AMOSCIN AMTUNOUT FM Preselection FM IF FMLEVEL AM Preselection

10.7 MHz

Osc. 455 kHzOsc.Osc. Fig. 6–1: CAP 3001 A application for 10.7 MHz AM-IF in detail AM IF AMLEVEL

1. Typical Application Circuit CAP 3001 A These values have to be adjusted to achieve the neccessary pulling range (compensa- tion of the parasitic boardcapacities). These ground nets are connected together to the main ground under the IC, close to the pin VREF1. Pin VREF2 is the reference for the tuning synthesizer. It is connected to the tuner ground and has no direct connection to the main ground under the IC. This is the ground at the tuner. It has a separate connection to the main ground under the IC. Keep these leads as short as possible!k. s. k. s k. s k. s k. s k. s k. s

1. Index A A/D Converters, 8 Absolute Maximum Ratings, 24 Analog Input Signals, 7 Analog Outputs, 12 Analog Volume Control, 12 Application Circuit, 33 ARI Travel Information, 11 ASU Noise Canceller, 12 B Block Diagram CAP 3001 A, 5 C Characteristics, 27 Clock Generation, 17 Crystal, 17, 27 D D/A Converters, 12 DCO, 17 Decimation, 8 Digital Audio Interface, 13 Digital Filters, 8 DSP , 4, 5 F FM/AM Tuning, 31 I I2S-bus, 13 IM-Bus Interface, 15 Input Signals, 7 Interpolation, 8 M MPX Signal, 6, 7 O Operating Modes, 6 Oscillator, 17 Outline Dimensions, 18 Oversampling, 12 P Pilot Tone, 9 Pin Configuration, 23 Pin Connections and Short Descriptions, 18 Potentiometer Inputs, 7 Power-Up Sequence, 31 R RDS, 6, 7, 11 Recommended Operating Conditions, 24 Reset, 31 S SNR, 28 Stereo Mixer, 8 Stereo PLL, 8 Synthesizer, 31 T THD+N, 28 Tuning System, 31, 32 V Volume Control, 12

1. Data Sheet History: 1. Final data sheet: “CAP 3001 A Car Audio Processor Hardware”, April 4, 1996, 6251-365-1DS. First release of the final data sheet. MICRONAS INTERMETALL GmbH Hans-Bunte-Strasse 19 D-79108 Freiburg (Germany) P.O. Box 840 D-79008 Freiburg (Germany) Tel. +49-761-517-0 Fax +49-761-517-2174 E-mail: docservice@intermetall.de Internet: http://www.intermetall.de Printed in Germany by Simon Druck GmbH & Co., Freiburg (04/96) Order No. 6251-365-1DS All information and data contained in this data sheet are with- out any commitment, are not to be considered as an offer for conclusion of a contract nor shall they be construed as to create any liability. Any new issue of this data sheet invalidates previous issues. Product availability and delivery dates are ex- clusively subject to our respective order confirmation form; the same applies to orders based on development samples deliv- ered. By this publication, MICRONAS INTERMETALL GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Reprinting is generally permitted, indicating the source. How- ever, our prior consent must be obtained in all cases.