CA3493 HARRIS | Alldatasheet

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waanis RCA. GE anTERSHL CA3493A, CA3493 May 1990 eee BiMOS Precision Operational Amplifiers Features: Applications: 1m Low Vio: 200 LV max. (CA3493A) = Thermocouple preamplifiers 500 uV max. (CA3493A) = Strain-gauge bridge amplifiers @ Low AV/O/AT: 3 UVC max. (CA3493A) = Summing amplifiers 5 pVAC max. (CA3493) ® Differential amplifiers ® Low lig and ly § Bilateral current sources @ Low AM/QJAT: 150 pA/PC max. (CA3493) = Log amplifiers mw Low AMAT: 3.7 nAC max. (CA3493) = Differential voltmeters '® Precision voltage references Active fiters = Buflers w Integrators = Sample-and-hold circuits = Low frequency filters Tee The CA3493A and CA3493 are ultra~stable, precision The op amps are functionally identical. The CA3493 and instrumentation, operational amplifiers that employ both CA3493A ‘operate from supply voltage of +3.5 V to +18 V and PMOS and bipolar transistors on a single monolithic chip. The have operating temperature ranges of OPC to +70°C and CA3493A and CA3493 amplifiers are internally phase -25°C to +85°C, respectively. Pr arsated and Provide a gain-bandwidth product of 1.2 These types are supplied in standard 8-lead TO-S-style (T MHz. They are pin compatible with the industrial types such as m iH 725, 108A, OP-7, LM11 and LM714 where positive nulling is. suffix), B-lead dual-in-line formed lead TO-S~style (DIL-CAN. employed. " ' § suffix) and 8-lead dual-in-line plastic (Mini-DIP E suffix) . Packages. Because of their low offset voltage and low offset voltage- " versus-temperature coefficient the CA3493A and CAgag3 Cifcult Description amplifiers have a wider range of applications than most Op The block diagram of the CA3493 amplifier, Fig. 2, shows the amps and are particularly well suited for use as thermocouple. voltage gain and supply current for each of its four amplifier amplifiers, high gain filters, buffer, strain gauge bridge stages. Simplified and complete schematic diagrams of the amplifiers and precision voltage references. CA3493 amplifier are shown in Figs. 3 and 4, respectively. SSS Copy © Hares Corporation 1880 File Number 1290 3-224

CA3493A, CA3493 Absolute-Maximum Ratings, Absolute-Maximum Values at Ta =25°C CA3493A CA3493 OC Supply Voltage . see . . cence ees 218 28 OV Differential-Mode Input Voltage : 35 25 ‘Common-Mode DC Input Voltage . . Wt -4,V> (V+-4,V> OV Device Dissipation Without Heat Sink Up to 55°C . we 630 630 mw Above 55°C wee . . Derate Linearly 6.67 mWic Temperature Range... : = 25 to 85 010 70°C Output Short-Circuit Duration * - Indefinite Indefinite Lead Temperature (During Soldering) at distance of 1/16 in, + 1/92 in (1.59 + 0.79 mm} from case for 10 secondsmax. ... : £265 2265 °C *Short circuit may be applied to ground or to either supply. orrse — aw _To? view oie G Ov oreser@_| orrser a, OF] Otis os 4 Inv, + Ze WA wot >A Wann Pe eur s NOTE. PIN 415 CONNECTED 10 CASE e sure 8 aNo T surFIx Fig. 1 - Functional diagram of CA3493A and CAS4S9. - 234 ‘as NETWORK Due ao a | Naa 950 pao wa ir zoo 18% 600 4 anput | &= 2000. 25K) AST ax S : cutout @ | nnd fond | | oor + 4 _ of) Oerse a itt Fig, 2- Block diagram of CA3499A and CA3493. Circuit Description (cont'd) overall offset-voltage characteristics of the amplifier. High load impedances for the input-stage differential pair (Q1,Q2) A quad of physically cross-connected are provided by the cascode-connected n-p-n transistors comprise the input-stage ist 03,05 d 04.06, differential pair (Q1,Q2 in Figs. 3 and 4), pn aneriouing ro the high walt ‘ this arrangement contributes to the low thereby contributing 0 the high gain input oftset-voltage characteristics of the Gevelaped in the stage. amptifier. The ultra-high gain provided in The second stage of the amplifier con- the first stage ensures that subsequent _ sists of a differential amplifier employing stages cannot significantly influence the PMOSIFETs (Q7,Q8 in Figs. 3 and 4) with 3-225

CA3493A, CA3493 ELECTRICAL CHARACTERISTICS at Ta=25°C, V+ =15V and V- =15V unless otherwise specified. [mits [evn a a Voltage, |Vio| ia Input Offset Voit- age Temp.Coetti- cient, AViO/AT (Over specitied 3 Aes temperature range for each device) Input Offset Current, lio ee ee Input Offset Current Temp. Coefficient, Alig/AT (Over 0.10 nArc specified temp- erature range for each device) fae EICeS Input Bias Current Temp. 7 AlAT. Input Noise Voltage, en p-p wWpp (0.1 to 10 Hz) Input Noise Volt age Density, en fo =10 Hz 25 fo =100 Hz 25 fo = 1000 Hz 24 aw fo = 10 kHz 24 Viz fo = 100 kHz 22 input Noise {0.1 to 10 Hz) input Noise Cur- rent Density, in fo =10 Hz 0.83 — )083 fo = 100 Hz 0.80 — |oso to = 1000 Hz 0.75 — 1075 pal fo =10 kHz 0.72 — |o7z Viz fo = 100 kHz 0.60 - 0.60 3-226

CA3493A, CA3493 ELECTRICAL CHARACTERISTICS at Ta=25°C, V+ =15Vand V- =15V (Cont'd) unless otherwise specified. [casassa_ | casas units ‘Common-Mode =135 Input Voltage to | to} v Range, VICR 15 Rejection Ratio, 78 316 To Tay ra wow=won | [ve [>st [se [ny Power Supply Re- wows | || Pele AViQitv* Maximum Output (R22 Ka) Large-Signal Voltage Gain Ze (Wo = +10) ee RL>1 KQ - gz RL>2 KO 110 5: RL210 KQ 115 Short-Circuit Output Current to “7 “7 the Opposite Rail | om*. |om~ Slew Rate, SR Unity Gain Voltage Follower) Gain-Bandwidth Product, ft AOL=0dB RL =2kQ MHz CL = 100 pF Vin =20 f=1kHz Smali-Signal Transient Re- ‘sponse, ty “ss (Vin =20 mV pp, t=1kHz ‘Supply Current, RL=© 38 23 | 35 vt =i5, Vo =-15 ea de CE Range 3-227

CA3493A, CA3493 iv on 88 —<A 7 8 Qo jae oe 60.0 ae 75K ©)ourPut WE ont S000 or - a thar, asl ® 1 os wr Q os, 3 am 6000 OK os Oh Fig. = CA3499 simplied schematic diagram o ? or | ° al | 0 on ourear 4 ar oe iS ee a T Yor . | ng m = bia! ae! 4 ozs bY os" As, 4 —_l @ Fig. 4 Scnematic diagram of CAS4894 and CA34S0, 3-228

CA3493A, CA3493 Circult Description (cont'd) across the 60-ohm resistors adjacent to ‘the output terminal (R9 and R10, Fig. 4). appropriate drain loading. Since Q7 and When the voltage drop developed across Q8 are MOSI/FETs, their loading on the either of these resistors reaches a poten- first stage is quite low, thereby making an tial equal to 1 \\be the respective protec- additional contribution to the high gain tive transistor (Q12 or Q13) is activated developed in the first stage. The second and shunts the base drive from the bases stage is also configured to convert its dif- of the output stage transistors (Q14 and ferential signal to a habianduaniedr9. 17) Q15,Q16). ‘signal by means of current mirror 09, Internal frequenc: + in 3y compensation for the (figs, 3 and 4) to drive subsequent gain .a34a3 amplifier is provided by two in- ge. ternal networks, a 6-pF capacitor con- The third stage of the amplifier consists nected between the input-stage transistor of Darlington-connected n-p-n transistors collectors and the node between the third (Q17,Q19 in Figs. 3 and 4), driving the and output stages and a second network, quasicomplementary Class AB output consisting of a 20-pF capacitor in series ‘stage (Q14 and Q15,Q16 in Figs. 3 and 4). with a 7.5-KQ resistor connected between Output-stage short-circuit protection is the input and output nodes of the third activated by voltage drops developed stage. "| eae es Ret = |S 28 SES Cee| fee 5 fai diaesectat rag coz oc] tesa end cpset oe See Scie eee Pegs ieeared ess tend atti i Sate pS es, Fig. 5- Typical input oftset-voltage temperature characteristic for CA3493A and CA3493. Fig. 6 — Input offset voitage vs. time. oad Sasguasccsasessitessantstgustatenss seeizseess suas: Ug seteseages S203 03d eget geeestace fppetstaa aa E coe ie Pa rete an eee ee ce eet Pett ees a Ais re HE TEA Atlas Meee i Fig. 7— Typical input bias current vs. tempera- Fig, 8 — Typical input offset current vs ture temperature 3-229

CA3493A, CA3493 (Oya ry (pee CEE de[ - jo ¢| |= Hera ATA AES ae {BERS Seen iF * 3) |p SSS a Te peel tf) eet a PI Dk ea 3 | 3 eat Fi HE i ‘ Le ia A Fig. 9 — Input noise voltage and current density vs. frequency. Fig. 10 — Power supply voltage (V+ ,V~)vs. = = ‘supply current. wR 0 *[ awe veneavae eve] | 2 Ld bt vot oS ti! H doo ee A 3 ao SS \\so js2ses tesezsseeat tata esti sests seen: bestia H Fig. 11 - Open-toop gain and phase-shift Powen Supey WAGE WA) reaponse (or OA3403. Fig. 12— Openioop gain vs. power-supply pire eed uu te eu Et volege ® Ee Poof ES hte eee a y] ans Tewreearone ps2 SESE jcoim Et3sagdk tate eedt Sei Feg nee ete azel HE see ee rere ee oe | Baeble claaiakaiadadl fo eee @ EYSEEESHE ci casegs ow Pe ss ce Sa a OE 8 GEE TREE oe marek 3. Toe =a ere eg pp Ea ee Ep SETS) 0S: 100k it ce L sees 55 Ogi des see arent) aes sony ? - Open-loop gain vs. temperature PS ce = Se ae eee Sa 9 re CAaASIA and CA3KOD, i fee — — > SSeS Slant mare noe He Ses See eieees| es oe {ite Seer Et | § 4 a coo ae s ee ace Ff LJSSS 27°) o + ¢ @ 6 @ @ Hn \\ iN common-mode input-oltage v8. aye tage ies a, supply voltage. Fig. 14 — Maximum undistorted output voltage vs, lrequency 3-230

CA3493A, CA3493 Offset Voltage Nulling the other two circuits shown below may The input offset voltage can be nulled to be used, thus providing simpler improved zero by any of the three methods shown in resolution for all types. the table below. A 10K potentiometer be- tween terminals 1 and 8, with its wiper CAUTION: The CA3493 amplifiers will be returned to V+, will provide a gross null- damaged if they are plugged into op-amp ing for all types. For finer nulling, either of Circuits employing nulling with respect to the V— supply bus. Offset Voltage Nulling Offset i” . Nulling AA evs « th M | Type | Resistor R Value | Resistor R Value | Resistor R Value CA3493A 50K 10K CA3493 20K 5K Gross Offset Finer Offset Adjustment Adjustments ze Tost Circuits 35 ox veo g= a oe FE 415 v y L © wong {. a - = 15 ¥ ~ Fig. 16 Input offset voltage test circuit —wy pee | sey s10vd cr < ae Your + + Lf + Your "Yn a - ——— TOP TRACE : INPUT VOLTAGE | BOTTOM TRACE : OUTPUT VOLTAGE ° ; vert: OY vteisy _—— Div yo e-8V someone lms 4 —_ =10K t HOR: “Diy RL of bedefef | ‘= > Fig. 17- Inverting amplitier (@) test circuit (0) response to kHz, 20-V pp square wave 3-231

CA3493A, CA3493 if 200 or i i a staat ro H BOTTOM TRACE © OUTPUT VOLTAGE ° i i verT.to¥ Ve sis sae v7 = I5V i i ims | Se eee - Hor lms . i Div Ru+ 2k °| a oan | ia | Lal b Fig. 18- Voltage follower (a} test circuit (0) response to 20-V pp, FHE square-wave input. 2.2mn Pass GH Pass RSE PLE v oe gt Ne 3 eae in | ' | fe ' @! @! -—<« ' \\ Orso Liye Li tee [1 ¢ ‘ oa nro @ @ Varurce | | Tua TR Sstoance 1093 1000 oY | aT i 1 Be | pode di T's i ba-=4 LWT if we | na worse « By a wr TT fas TT ton! TT Tag tried tt “t ied i wine + eich oan oe oe b € Fig. 19+ Low frequency noise (a) test cir cuit—0.1 t0 10 Hz (b) output A waveform—0to 10 Hz noise (c) output B waveform—0 to 10 Hz noise. 3-232

CA3493A, CA3493 Application Circuits ae o 6 Oy 4 2] v 2 (on casaad 6 oT ix Be, By i a 3k 3 a “our Re Re ; \\ R241) Bh oy, (Bay Er vour Ye (rt!) as G52) WEN Vour #tva-¥) (S24 a THE MATCHING OR MISMATCHING OF THIS NETWORK $< Fig. 20- Typical two-op amp bridge-type dMterentias ampiter Fig. 21-Diforntiatampitier (imple subtracton ° ting CADIS 418 w 3 ny a, TOR § its 3, on (0M TOs0Kn SPL 4] ! ‘st zen: aL 1 | 1 Ls : (hve eae Bua) ALL RESISTORS ARE 1% Rr Re IF RIS RS AND R2=AS+RS THEN our 2 i FOR R, VALUES OF OM TO SER WITH YsIY ALL RESISTANCE VALUES ARE IN OHMS: TOO RTRD ‘TEmmni Fu "500 KA Fig, 22- Using ©A3490 a8 a bilateral curent Fig, 29- Typical summing amplifier 3-233

CA3493A, CA3493 The CA3493 is an excellent choice for use The three 22-megohm resistors will provide with themocouples. In Fig. 24, the CA3493_full-scale output if the thermocouple opens. amplifies the signal generated 500 times. oe IN ovat Fig 24- The CAD uted in a themocounie 3-234